PHILIPS 74F50728 Synchronizing cascaded dual positive edge-triggered D-type flip-flop handbook
Contents
1. Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included OUTLINE VERSION REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE SOT27 1 050G04 MO 001AA EJO 2 H 95 03 11 1990 Sep 14 Philips Semiconductors Product specification Synchronizing cascaded dual positive edge triggered 74F50728 D type flip flop S014 plastic small outline package 14 leads body width 3 9 mm SOT108 1 a 2 5 scale DIMENSIONS inch dimensions are derived from the original mm dimensions inches Note 1 Plastic or metal protrusions of 0 15 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC EIAJ PROJECTION SOT 108 1 076E068 MS 012AB E 97 05 22 ISSUE DATE 1990 Sep 14 10 Philips Semiconductors Product specification Synchronizing cascaded dual positive edge triggered D type flip flop oes NOTES 1990 Sep 14 11 Philips Semiconductors Product specification Synchronizing cascaded dual positive edge triggered D type flip flop G Data sheet status Data sheet Product Definition 1 status status Objective Development This data sheet contains the design target or goal specifications for product development specification Specification may change in any manner without notice Preliminary Q2. 0 INTEGRATED CIRCUITS DATA SAHEET 74F50728 Synchronizing cascaded dual positive edge triggered D type flip flop Positive specification 1990 Sep 14 IC15 Data Handbook Philips PHILIPS Semiconductors l LI DS Philips Semiconductors Product specification E Synchronizing cascaded dual positive edge triggered D type flip flop 74F50728 FEATURES Metastable immune characteristics Output skew less than 1 5ns See 74F5074 for synchronizing dual D type flip flop See 74F50109 for synchronizing dual J K positive edge triggered flip flop See 74F50729 for synchronizing dual dual D type flip flop with edge triggered set and reset Industrial temperature range available 40 C to 85 C DESCRIPTION The 74F50728 is a cascaded dual positive edge triggered D type featuring individual data clock set and reset inputs also true and complementary outputs Set SDn and reset RDn are asynchronous active low inputs and operate independently of the clock CPn input They set and reset both flip flops of a cascaded pair simultaneously Data must be stable just one setup time prior to the low to high transition of the clock for guaranteed propagation delays ORDERING INFORMATION Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive going pulse Following the hold time interval data at the Dn input may be changed without affecting the lev
3. 08 sec SF00610 Figure 2 September 14 1990 4 Philips Semiconductors Product specification Synchronizing cascaded dual positive edge triggered D type flip flop 74F50728 FUNCTION TABLE INTERNAL o Tp TS INPUTS REGISTER OPERATING MODE Son Ron crn on NOTES NC No change from the previous setup H High voltage level X Dontcare h High voltage level one setup time prior to low to high This setup is unstable and will change when either set of clock transition reset return to the high level L Low voltage level T Low to high clock transition Low voltage level one setup time prior to low to high Data entering the flip flop requires two clock cycles to clock transition arrive at the output see logic diagram ABSOLUTE MAXIMUM RATINGS Operation beyond the limit set forth in this table may impair the useful life of the device Unless otherwise noted these limits are over the operating free air temperature range Supply voltage Current applied to output in low output state Tamb Operating free air temperature range Industrial range 40 to 85 Storage temperature range 65 to 150 RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS ee ee ee Industrial range 40 September 14 1990 5 Philips Semiconductors Product specification Synchronizing cascaded dual positive edge triggered D type flip flop 74F50728 DC ELECTRICAL CHARACTERISTICS Over recommended
4. 0V Vec 5 0V 10 Vec 5 0V 10 CONDITION C 50pF C 50pF C 50pF R 500Q R 5002 Maximum clock frequency 10 tPLH Propagation delay CPn to Qn or Qn Waveform 1 PLH Propagation delay PHL SDn RDn to Qn or Qn Output skew 2 NOTES TO AC ELECTRICAL CHARACTERISTICS 1 tp 4 actual tpy actual for any one output compare to any other output where N and M are either LH or HL 2 Skew lines are valid only under same conditions temperature Vcc loading etc Waveform 2 September 14 1990 6 Philips Semiconductors Product specification Synchronizing cascaded dual positive edge triggered D type flip flop 74F50728 AC SETUP REQUIREMENTS a Tamb 0 C to Tamb 40 C to 85 C 70 C SYMBOL PARAMETER TEST 45 Vec 5 0V 10 Vec 5 0V 10 CONDITION 50pF Cu 50pF CL 50pF E E a a a oF Setup time high or low 5 Dn to CPn Waveform 1 15 ni Hold time high or low 0 0 Dn to CPn Waveform 1 0 0 ai CPn pulse width 3 0 high or low ANelo 4 0 1 Recovery time E ems i ee e m AC WAVEFORMS Waveform 2 Propagation delay for set and reset to output Waveform 1 Propagation delay for data to output data setup set and reset pulse width time and hold times and clock width and maximum clock frequency SDn or RDn VM SF00590 Waveform 4 Output skew SF00603 Waveform 3 Recovery time for set or reset to output NOTES F
5. e PHILIPS
6. e normal propagation delay Product specification 74F50728 Suppose a designer wants to use the flop for synchronizing asynchronous data that is arriving at 1OMHz as measured by a frequency counter and is using a clock frequency of 50MHz He simply plugs his number into the equation below MTBF et Tofgfj In this formula fc is the frequency of the clock f is the average input event frequency and t is the period of the clock input 20 nanoseconds In this situation the f will be twice the data frequency of 20 MHz because input events consist of both of low and high data transitions From Fig 2 it is clear that the MTBF is greater than 1041 seconds Using the above formula the actual MTBF is 2 23 X 1042 seconds or about 7 X 10 4 years TYPICAL VALUES FOR t AND Ty AT VARIOUS VccS AND TEMPERATURES 125ps 1 0X sec 138ps 5 4X mc sec 160ps 1 7X 7 sec Voc 5 0V 115ps 1 3 X 1010 sec 135ps 9 8 X 106 sec 167ps 3 9 X 104 sec 3 4 X 1013 sec Voc 4 5V 115ps 132ps 5 1 X 108 sec 175ps 7 3 X 104 sec MEAN TIME BETWEEN FAILURES VERSUS DATA FREQUENCY AT VARIOUS CLOCK FREQUENCY Clock 40MHz nn Mean time between failures seconds Clock 50MHz a a a Clock 650MHz Clock 70MHz e S Clock 80MHz 1 billion years T ft Cloc 100MHz 1010 1000 100K Data frequency Hz NOTE Voc 5V Tamb 25 C t 135ps To 9 8 X 1
7. e the incoming IEC J EEE SYMBOL data and two separate flip flops are required to produce the cascaded flop circuit In order to assist the designer of synchronizing circuits Philips Semiconductors is offering the 74F50728 Qo Q0 Qi Q1 O O Voc Pin 14 GND Pin 7 SF00606 Q OUTPUT Q OUTPUT SF00609 Figure 1 The 50728 consists of two pair of cascaded D type flip flops with metastable immune features and is pin compatible with the 74F74 Because the flops are cascaded on a single part the metastability SF00607 September 14 1990 3 Philips Semiconductors Synchronizing cascaded dual positive edge triggered D type flip flop characteristics are greatly improved over using two separate flops that are cascaded The pin compatibility with the 74F74 allows for plug in retrofitting of previously designed systems Because the probability of failure of the 74F50728 is so remote the metastability characteristics of the part were empirically determined based on the characteristics of its sister part the 74F5074 The table below shows the 74F5074 metastability characteristics Having determined the To and t of the flop calculating the mean time between failures MTBF for the 74F50728 is simple It is however somewhat different than calculating MTBF for a typical part because data requires two clock pulses to transit from the input to the output Also in this case a failure is considered of the output beyond th
8. els of the output Data entering the 74F50728 requires two clock cycles to arrive at the outputs The 74F50728 is designed so that the outputs can never display a metastable state due to setup and hold time violations If setup time and hold time are violated the propagation delays may be extended beyond the specifications but the outputs will not glitch or display a metastable state Typical metastability parameters for the 74F50728 are t 135ps and To 9 8 X 10 sec where t represents a function of the rate at which a latch in a metastable state resolves that condition and To represents a function of the measurement of the propensity of a latch to enter a metastable state TYPICAL SUPPLY TYPE TYPICAL fmax CURRENT TOTAL 74F50728 145 MHz ORDER CODE COMMERCIAL RANGE Vee 5V 410 Tamb 0 C to 70 C DESCRIPTION INDUSTRIAL RANGE Vec 5V 10 Tamb 40 C to 85 C 14 pin plastic DIP N74F50728N 174F50728N SOT27 1 14 pin plastic SO N74F50728D 174F50728D SOT108 1 INPUT AND OUTPUT LOADING AND FAN OUT TABLE 74F U L HIGH LOAD VALUE HIGH CPO CP1 Clock inputs active rising edge 1 0 1 0 20uA 20uA 20uA 20uA SDO SD1 Set inputs active low 1 0 1 0 RDO RD1 Reset inputs active low 1 0 1 0 20uA 20uA Q0 Q1 Q0 Q1 50 33 1 0MA 20MA NOTE One 1 0 FAST unit load is defined as 20A in the high state and 0 6mA in the low state September 14 1990 2 853 1389 00421 Philips Semiconductors Product speci
9. esentation or warranty that such applications will be suitable for the specified use without further testing or modification Disclaimers Life support These products are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application Right to make changes Philips Semiconductors reserves the right to make changes without notice in the products including circuits standard cells and or software described or contained herein in order to improve design and or performance Philips Semiconductors assumes no responsibility or liability for the use of any of these products conveys no license or title under any patent copyright or mask work right to these products and makes no representations or warranties that these products are free from patent copyright or mask work right infringement unless otherwise specified Philips Semiconductors Copyright Philips Electronics North America Corporation 1998 811 East Arques Avenue All rights reserved Printed in U S A P O Box 3409 Sunnyvale California 94088 3409 print code Date of release 10 98 Telephone 800 234 7381 Document order number 9397 750 05215 Lett make things beter e
10. fication Synchronizing cascaded dual positive edge triggered D type flip flop 74F50728 PIN CONFIGURATION LOGIC DIAGRAM Voc Pin 14 GND Pin7 SF00608 SF00605 NOTE Data entering the flip flop requires two clock cycles to arrive at the output LOGIC SYMBOL SYNCHRONIZING SOLUTIONS Synchronizing incoming signals to a system clock has proven to be costly either in terms of time delays or hardware The reason for this is that in order to synchronize the signals a flip flop must be used to capture the incoming signal While this is perhaps the only way to synchronize a signal to this point there have been problems with this method Whenever the flop s setup or hold times are violated the flop can enter a metastable state causing the outputs in turn to glitch oscillate enter an intermediate state or change state in some abnormal fashion Any of these conditions could be responsible for causing a system crash To minimize this risk flip flops are often cascaded so that the input signal is captured on the first clock pulse and released on the second clock pulse see Fig 1 This gives the first flop about one clock period minus the flop delay and minus the second flop s clock to Q setup time to resolve any metastable condition This method greatly reduces the probability of the outputs of the synchronizing device displaying an abnormal state but the trade off is that one clock cycle is lost to synchroniz
11. operating free air temperature range unless otherwise noted SYMBOL PARAMETER TEST LIMITS UNIT CONDITIONS PMN J rvez WAX Vou High level output voltage Voc MIN Viy MIN loy MAX 10 Voc Fes v VoL Low level output voltage vee MIN Vic lol MAX 10 Vcc oso oso v Ph Input current at maximum input voltage Voc MAX V 7 0V OTES High level input current Voc MAX V 2 7V Oo Oo Low level input current Dn Voc MAX V 0 5V Ero i oe 60 aa Short circuit output current Vcc MAX Vo 2 25V Supply current total Voc MAX N 1 For conditions shown as MIN or MAX use the appropriate value specified under recommended operating conditions for the applicable type 2 All typical values are at Voc 5V Tamb 25 C 3 Not more than one output should be shorted at a time For testing los the use of high speed test apparatus and or sample and hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests In any sequence of parameter tests log tests should be performed last 4 Measure Icc with the clock input grounded and all outputs open then with Q and Q outputs high in turn AC ELECTRICAL CHARACTERISTICS Tamb 25 C Tamb 0 C to 70 C SYMBOL PARAMETER TEST Vcc 5
12. or all waveforms Vy 1 5V The shaded areas indicate when the input is permitted to change for predictable output performance September 14 1990 7 Philips Semiconductors Synchronizing cascaded dual positive edge triggered D type flip flop TEST CIRCUIT AND WAVEFORMS NEGATIVE PULSE PULSE GENERATOR POSITIVE PULSE Test Circuit for Totem Pole Outputs DEFINITIONS Product specification 74F50728 tw Input Pulse Definition RL Load resistor see AC ELECTRICAL CHARACTERISTICS for value CL Load capacitance includes jig and probe capacitance see AC ELECTRICAL CHARACTERISTICS for value INPUT PULSE REQUIREMENTS amplitude Vm rep rate tw tTLH RT Termination resistance should be equal to Zour of pulse generators 3 0V 1MHz 2 5ns September 14 1990 8 SF00006 Philips Semiconductors Synchronizing cascaded dual positive edge triggered D type flip flop DIP14 plastic dual in line package 14 leads 300 mil seating plane in 1 index a 5 scale DIMENSIONS inch dimensions are derived from the original mm dimensions Product specification 74F50728 SOT27 1 A UNIT ae Ay min A2 max by p e0 4 2 0 51 3 2 19 50 6 48 18 55 6 20 inches 0 17 0 020 0 13 0 77 0 73 0 26 0 24
13. ualification This data sheet contains preliminary data and supplementary data will be published at a later date specification Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product Product Production This data sheet contains final specifications Philips Semiconductors reserves the right to make specification changes at any time without notice in order to improve design and supply the best possible product 1 Please consult the most recently issued datasheet before initiating or completing a design Definitions Short form specification The data in a short form specification is extracted from a full data sheet with the same type number and title For detailed information see the relevant data sheet or data handbook Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System IEC 134 Stress above one or more of the limiting values may cause permanent damage to the device These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied Exposure to limiting values for extended periods may affect device reliability Application information Applications that are described herein for any of these products are for illustrative purposes only Philips Semiconductors make no repr
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PHILIPS 74F50728 Synchronizing cascaded dual positive edge triggered D type flip flop handbook