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PHILIPS BUK101-50DL handbook

1. Normalised Power Derating D amp IDM A BUK101 50DL Overload protection characteristics not shown Fig 2 Normalised power dissipation Fig 4 Safe operating area Tm 25 C Pp 100 P Pp 25 C T m Ip amp lom f Vos Iom Single pulse parameter t Normalised Current Derating Zth K W BUK101 50D 0 01 Pea ee a eee 20 40 60 80 100 120 140 1E 07 1E 05 1E 03 1E 01 1E 01 Tmb C Is Fig 3 Normalised continuous drain current Fig 5 Transient thermal impedance lo 100 1p lp 25 C f T mp conditions Vis 5 V Zn mo f t parameter D t T April 1993 5 Rev 1 100 Philips Semiconductors PowerMOS transistor Logic level TOPFET BUK101 50DL 0 1 2 3 4 5 VDS V Fig
2. 54 2 54 Fig 22 TO220AB pin 2 connected to mounting base Notes 1 Refer to mounting instructions for TO220 envelopes 2 Epoxy meets UL94 VO at 1 8 April 1993 9 Rev 1 100 Philips Semiconductors Product specification PowerMOS transistor BUK101 50DL Logic level TOPFET DEFINITIONS Data sheet status This data sheet contains target or goal specifications for product development This data sheet contains preliminary data supplementary data may be published later This data sheet contains final product specifications Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System IEC 134 Stress above one or more of the limiting values may cause permanent damage to the device These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied Exposure to limiting values for extended periods may affect device reliability Application information Where application information is given it is advisory and does not form part of the specification Philips Electronics N V 1996 All rights are reserved Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner The information presented in this document does not form part of any quotation or contract it is believed to be accurate and reliable and may be changed without
3. 6 Typical on state characteristics T 25 C ID f Vps parameter Vig t 2 ms RDS mOhm BUK101 50DL m VIS V 3 5 40 ID A Fig 7 Typical on state resistance T 25 C Roson f lp parameter Vic t 2 ms Normalised RDS ON Tj 0 60 40 20 0 20 40 60 80 100 120 140 Tj C Fig 8 _ Normalised drain source on state resistance a Rosron Rosiom29 C I T l 13 A Vis 5 V April 1993 Product specification BUK101 50DL td sc ms BUK101 50DL 1 10 PDS kW Fig 9 Typical overload protection characteristics tase f Pps conditions Vis 2 4 V T 25 C PDSM 20 40 60 80 100 120 140 Tmb C Fig 10 Normalised limiting overload dissipation Pos 100 Posw Posu 25 C T mo Energy amp Time BUK101 50DL Energy J Tj TO 20 60 100 140 180 220 Tmb C Fig 11 Typical overload protection characteristics Conditions Vpp 13 V Vis 5 V SC load 30 mQ Rev
4. Vig 0 V T 125 C Drain source on state Vis 5 V lpm 13 A t lt 300 us resistance 5 lt 0 01 OVERLOAD PROTECTION CHARACTERISTICS TOPFET switches off when one of the overload thresholds is reached It remains latched off until reset by the input em ae eg RE ppg e e ir Short circuit load protection H R 10 mQ Overload threshold energy J Response time 3 ms Drain current A Peak drain current 105 A Over temperature protection Threshold junction temperature Vis 5 V from 2 1 A 150 TRANSFER CHARACTERISTIC Tp 25 C SYMBOL PARAMETER CONDITIONS MIN TYP max UNIT Forward transconductance Vos 10 V lbw 13 A t lt 300 ps ee eel jee 5 lt 0 01 1 Continuous input voltage The specified pulse width is for the drain current 2 Refer to OVERLOAD PROTECTION LIMITING VALUES 3 Continuous drain source supply voltage Pulsed input voltage 4 Continuous input voltage Momentary short circuit load connection The higher peak current is due to the effect of capacitance Cgd 5 The over temperature protection feature requires a minimum on state drain source voltage for correct operation The specified minimum Ip ensures this condition April 1993 3 Rev 1 100 Philips Semiconductors Product specification PowerMOS transistor BUK101 50DL Logic level TOPFET INPUT CHARACTERISTICS Tm 25 C unless otherwise specified The supply for the logic and overload protection is
5. notice No liability will be accepted by the publisher for any consequence of its use Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances devices or systems where malfunction of these products can be reasonably expected to result in personal injury Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale April 1993 10 Rev 1 100
6. 1 100 Philips Semiconductors PowerMOS transistor Logic level TOPFET BUK101 50DL 60 70 VIS V Fig 12 Typical clamping characteristics 25 C Ip f Vps conditions Vig 0 V t lt 50 us VIS TO V pa 60 40 20 0 20 40 60 80 100 120 140 Tj C Fig 13 Input threshold voltage Viso f T conditions p 1 MA Vps 5 V IISL amp IIS uA BUK101 50DL PROTECTION LATCHED 0 2 4 6 VIS V Fig 14 Typical DC input characteristics T 25 C lig amp lis Vig protection latched amp normal operation April 1993 Product specification BUK101 50DL BUK101 50DL 0 0 2 1 VSD V Fig 15 Typical reverse diode current T 25 C ls f Vsps conditions Vis 0 V D TOPFET __ jaz TY D U T S ID measure o OV OR1 Fig 16 Test circuit for resistive load switching times VIS V amp VDS V BUK101 50DL 200 400 i 600 time us Fig 17 Typical switching waveforms resistive load Vo 13 V R 2 1 Q R 50 Q T 25 C Rev 1 100 Philips Semiconductor
7. NS MN M Vo Electrostatic discharge capacitor Human body model voltage C 250 pF R 1 5 KQ 1 Prior to the onset of overvoltage clamping For voltages above this value safe operation is limited by the overvoltage clamping energy 2 A higher T is allowed as an overload condition but at the threshold Tro the over temperature trip operates to protect the switch 3 The input voltage for which the overload protection circuits are functional 4 For further information refer to OVERLOAD PROTECTION CHARACTERISTICS 5 The short circuit load protection is able to save the device providing the instantaneous on state dissipation is less than the limiting value for Posu Which is always the case when Vps is less than Vpop Maximum April 1993 2 Rev 1 100 Philips Semiconductors Product specification PowerMOS transistor BUK101 50DL Logic level TOPFET THERMAL CHARACTERISTICS srweor paramere GONDMIONS mn WP max unr Thermal resistance Junction to mounting base 1 3 1 67 K W Junction to ambient in free air 60 K W STATIC CHARACTERISTICS Tm 25 C unless otherwise specified sveo eanaweren_____ eonownons un 0 wn Drain source clamping voltage Vis O V lp gt 10mA Drain source clamping voltage Vis 0 V Ipy 2 A t lt 300 us 5 lt 0 01 Zero input voltage drain current Vpg 12 V Vis 0 V Zero input voltage drain current Vps 50 V Vis O V Zero input voltage drain current Vos 40 V
8. O0 O BUK101 50DL 9 O Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK101 50DL DESCRIPTION Monolithic temperature and overload protected logic level power MOSFET in a 3 pin plastic envelope intended as a general purpose switch for automotive systems and other applications APPLICATIONS General controller for driving e e solenoids e heaters FEATURES e Vertical power DMOS output stage e Low on state resistance e Overload protection against over temperature e Overload protection against short circuit load e Latched overload protection reset by input e 5 V logic compatible input level e Control of power MOSFET and supply of overload protection circuits derived from input e Lower operating input current permits direct drive by micro controller e ESD protection on input pin e Overvoltage clamping for turn off of inductive loads PINNING TO220AB DESCRIPTION input drain source drain April 1993 QUICK REFERENCE DATA SYMBOL PARAMETER Continuous drain source voltage Continuous drain current Total power dissipation Continuous junction temperature Drain source on state resistance Input supply current Vs 5V FUNCTIONAL BLOCK DIAGRAM POWER MOSFET LOGIC AND PROTECTION SOURCE Fig 1 Elements of the TOPFET PIN CONFIG
9. URATION SYMBOL TOPFET _ Pa i JH 1 Rev 1 100 Philips Semiconductors Product specification PowerMOS transistor BUK101 50DL Logic level TOPFET LIMITING VALUES Limiting values in accordance with the Absolute Maximum Rating System IEC 134 smo Jpanaweren __ _ eowomons an ma va Continuous drain source voltage Continuous input voltage Continuous drain current Continuous drain current fom N Repetitive peak on state drain current Total power dissipation Storage temperature Continuous junction temperature normal operation IA IA IA IA O OQEPPDP lt lt Lead temperature during soldering OVERLOAD PROTECTION LIMITING VALUES With the protection supply provided via the input pin TOPFET can protect itself from two types of overload CO ee _ Over ee protection ke le Le Short circuit load protection Protected drain source supply voltage Vis 5 V Instantaneous overload dissipation OVERVOLTAGE CLAMPING LIMITING VALUES At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients srweo paramere conomons MIN max UNTT A Repetitive peak clamping current Vs 0V Non repetitive clamping energy Tmo lt 25 C lbu 26 A Vop lt 20 V inductive load Repetitive clamping energy Tmo lt 95 C loy 8 A Vbp lt 20 V f 250 Hz ESD LIMITING VALUE SYMBOL PARAMETER CONDITIO
10. s PowerMOS transistor Logic level TOPFET EDSM 0 120 140 Fig 18 Normalised clamping energy rating Ensm f T mb conditions lp 26 A Vig 5 V D TOPFET_ A i dls PHH C t Schottky Fig 19 Clamping energy test circuit Ris 50 Q Epsu 0 5 LI i Vcenpss Vcnpss Vpp April 1993 Product specification BUK101 50DL 100 nA 0 20 40 6 80 120 140 T C Fig 20 Typical off state leakage current loss f T Conditions Vps 40 V ls 0 V liso amp lisl normalised to 25 C 0 5 60 20 20 60 100 140 180 Tj C Fig 21 Normalised input currents normal amp latched lso liso25 C amp Ingi h 28 C f T Vig 5 V Rev 1 100 Philips Semiconductors Product specification PowerMOS transistor BUK101 50DL Logic level TOPFET MECHANICAL DATA Dimensions in mm Net Mass 2 g 3 0 max not tinned Ta max 1L 2x gt a 0 9 max 3x gt A 2
11. taken from the input sec Jpanaweren ____ coomons wn rve wax unr Input threshold voltage Vbs 5 Vi b 1 mA Input supply current normal operation Protection reset voltage Input supply current protection latched Input breakdown voltage l 10 mA Input series resistance to gate of power MOSFET SWITCHING CHARACTERISTICS Tw 25 C Ri 50 Q Refer to waveform figure and test circuit SYMBOL PARAMETER conomons MIN TYP max unr resistive load R 2 1 Q resistive load R 2 1 Q REVERSE DIODE LIMITING VALUE smoot eanaweren _ eonomons Tans mac T unr REVERSE DIODE CHARACTERISTICS Twa 25 C svmeo PARAMETER oonomons mm TWP max Jun Vspo Forward voltage ls 26 A Vis 0 V t 300 us 1 0 1 5 V ty Reverse recovery time not applicable 1 The input voltage below which the overload protection circuits will be reset 2 The reverse diode of this type is not intended for applications requiring fast reverse recovery April 1993 4 Rev 1 100 Philips Semiconductors Product specification PowerMOS transistor BUK101 50DL Logic level TOPFET ENVELOPE CHARACTERISTICS armeon Paraweren _Teonomons Town ve on To Internal drain inductance Measured from contact screw on tab to centre of die Internal drain inductance Measured from drain lead 6 mm from package to centre of die Internal source inductance Measured from source lead 6 mm from package to source bond pad

PHILIPS BUK101-50DL handbook

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