National Semiconductor LMC6032 CMOS Dual Operational Amplifier handbook
Contents
1. 6 C 0 1 MAS lt I mA 100 pF OUTPUT SOURCING 1 mA 100 pF OUTPUT SINKING 1 mA 1M 5M FREQUENCY Hz DS011135 30 Output Characteristics Current Sinking 10 E LM E o ae Sa 59 z 5 0 1 oc u cd 0 01 0 001 0 01 0 1 1 10 100 OUTPUT SINK CURRENT mA DS011135 25 CMRR vs Frequency 100 90 80 70 60 50 40 30 20 10 CMRR dB 100 1k 10k 100k 1M FREQUENCY Hz DS011135 28 Non Inverting Large Signal Pulse Response INPUT VOLTAGE V OUTPUT VOLTAGE V TIME us DS011135 31 www national com Typical Performance Characteristics Vg 7 5V T4 25 C unless otherwise specified Continued Stability vs Stability vs Capacitive Load Capacitive Load 100 000 100 000 hau Ay 10or 10 10 000 y 10 000 y p S CNN E a 1000 Q 10007 3 N UNSTABLE 4 S8 n E m E 100 Z 100 Pd o 10 OVERSHOOT S z 10 OVERSHOOT a 2 OVERSHOOT Ei 10 o 10 1 1 10 1 0 1 0 01 0 0010 0 00102. www national com 12 Notes LIFE SUPPORT POLICY SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor National Semiconductor Corporation Europe Americas Fax 49 0 1 80 530 85 86 Tel 1 800 272 9959 Email europe support nsc com Fax 1 800 737 7018 Deutsch Tel 49 0 1 80 530 85 85 Email support nsc com English Tel 49 0 1 80 532 78 32 Frangais Tel 49 0 1 80 532 93 58 www national com Italiano Tel 49 0 1 80 534 16 80 NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor National Semiconductor Asia Pacific Customer Japan Ltd Response Group Tel 81 3 5639 7560 Tel 65 2544466 Fax 81 3 5639 7507 Fax 65 2504466 Email sea support nsc com National does not assume any responsibi
3. 90 12 50 V R 6002 to 7 5V 12 00 min 0 79 1 45 V 1 75 max lo Output Current Vt 5V 22 13 mA Sourcing Vo OV 9 min Sinking Vo 5V 21 13 mA 9 min Vt 15V 40 23 mA Sourcing Vo OV 15 min Sinking Vo 13V Note 10 Supply Current Both Amplifiers Vo 1 5V 1 9 max www national com AC Electrical Characteristics Unless otherwise specified all limits guaranteed for T 25 C Boldface limits apply at the temperature extremes V 5V V GND OV Vom 1 5V Vout 2 5V and R gt 1M unless otherwise specified Symbol Parameter Conditions Typical LMC6032I Units Note 5 Limit Note 6 SR Slew Rate Note 8 1 1 0 8 V us 0 4 min GBW Gain Bandwidth Product 1 4 MHz Om Phase Margin 50 Deg Gu Gain Margin 17 dB Amp to Amp Isolation Note 9 130 dB en Input Referred Voltage Noise F 1 kHz 22 nV dHz in Input Referred Current Noise F 1 kHz 0 0002 pA Hz THD Total Harmonic Distortion F 10 kHz A 10 R 2 KQ Vo 8 Vpp 0 01 5V Supply guarantee TA 0JA Note 4 Note 10 Note 11 Note 12 d specifications apply only for the test conditions listed uman body model 100 pF discharged through a 1 5 kQ resistor H Note 5 Typical values represent the most likely parametric norm Do not connect output to V when V is greater than 13V or reliability may be adversely affected All numbers apply for packages
4. soldered directly into a PC board Note 6 All limits are guaranteed at room temperature standard type face or at operating temperature extremes bold type face Note 7 Vt 15V Vom 7 5V and R connected to 7 5V For Sourcing tests 7 5V lt Vo lt 11 5V For Sinking tests 2 5V lt Vo lt 7 5V Note 8 V 15V Connected as Voltage Follower with 10V step input Number specified is the slower of the positive and negative slew rates Note 9 Input referred V 15V and R 10 kQ connected to V 2 Each amp excited in turn with 1 kHz to produce Vo 13 Vpp For operating at elevated temperatures the device must be derated based on the thermal resistance 8j with Pp Ty TA 0jA Note 1 Absolute Maximum Ratings indicate limits beyond which damage to component may occur Operating Ratings indicate conditions for which the device is in tended to be functional but do not guarantee specific performance limits For guaranteed specifications and test conditions see the Electrical Characteristics The Note 2 Applies to both single supply and split supply operation Continuous short circuit operation at elevated ambient temperature and or multiple Op Amp shorts can result in exceeding the maximum allowed junction temperature of 150 C Output currents in excess of 30 mA over long term may adversely affect reliability Note 3 The maximum power dissipation is a function of Tymax 64 and TA The maximum allowable power dissipation at any a
5. 010 1 1 10 10 1 0 1 0 01 0 0010 0 0010 010 1 1 10 SINKING SOURCING SINKING SOURCING LOAD CURRENT mA LOAD CURRENT mA DS011135 32 DS011135 33 Note 13 Avoid resistive loads of less than 5000 as they may cause instability Application Hints AMPLIFIER TOPOLOGY COMPENSATING INPUT CAPACITANCE The topology chosen for the LMC6032 shown in Figure 1 is The high input resistance of the LMC6032 op amps allows unconventional compared to general purpose op amps in the use of large feedback and source resistor values without that the traditional unity gain buffer output stage is not used losing gain accuracy due to loading However the circuit will instead the output is taken directly from the output of the in be especially sensitive to its layout when these large value tegrator to allow a larger output swing Since the buffer tra resistors are used ditionally delivers the power to the load while maintaining Every amplifier has some capacitance between each input high op amp gain and stability and must withstand shorts to and AC ground and also some differential capacitance be either rail these tasks now fall to the integrator tween the inputs When the feedback network around an As a result of these demands the integrator is a compound amplifier is resistive this input capacitance along with any affair with an embedded gain stage that is doubly fed forward additional capacitance due to circuit board traces the via C and Cy by a dedicat
6. D LMC60327 0 LMC6032 General Description The LMC6032 is a CMOS dual operational amplifier which can operate from either a single supply or dual supplies Its performance features include an input common mode range that reaches ground low input bias current and high voltage gain into realistic loads such as 2 kQ and 6000 This chip is built with National s advanced Double Poly Silicon Gate CMOS process See the LMC6034 datasheet for a CMOS quad operational amplifier with these same features For higher performance characteristics refer to the LMC662 Features m Specified for 2 KQ and 6000 loads m High voltage gain 126 dB November 1994 National Semiconductor CMOS Dual Operational Amplifier m Low offset voltage drift 2 3 V C m Ultra low input bias current 40 fA m input common mode range includes V m Operating range from 5V to 15V supply m lss 400 uA amplifier independent of V m Low distortion 0 01 at 10 kHz m Slewrate 1 1 V us m improved performance over TLC272 Applications m High impedance buffer or preamplifier Current to voltage converter Long term integrator Sample and hold circuit n m Medical instrumentation Connection Diagram OUTPUT A INVERTING INPUT A NON INVERTING INPUT A 8 Pin DIP SO V OUTPUT B INVERTING INPUT B y NON INVERTING INPUT B DS011135 1 Top View Ordering Information Temperature Range Package NSC Drawing Transport M
7. DANCE WORK It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires special layout of the PC board When one wishes to take advantage of the ultra low bias current of the LMC6032 typically less www national com Application Hints Continued than 0 04 pA it is essential to have an excellent layout For tunately the techniques for obtaining low leakages are quite simple First the user must not ignore the surface leakage of the PC board even though it may sometimes appear accept ably low because under conditions of high humidity or dust or contamination the surface leakage will be appreciable To minimize the effect of any surface leakage lay out a ring of foil completely surrounding the LMC6032 s inputs and the terminals of capacitors diodes conductors resistors relay terminals etc connected to the op amp s inputs See Figure 5 To have a significant effect guard rings should be placed on both the top and bottom of the PC board This PC foil must then be connected to a voltage which is at the same voltage as the amplifier inputs since no leakage current can flow between two points at the same potential For example a PC board trace to pad resistance of 10 20 which is nor mally considered a very large resistance could leak 5 pA if the trace were a 5V bus adjacent to the pad of an input This would cause a 100 times degradation from the LMC6032 s actu
8. LDER CONNECTION DS011135 11 Input pins are lifted out of PC board and soldered directly to components All other pins connected to PC board FIGURE 7 Air Wiring BIAS CURRENT TESTING The test method of Figure 8 is appropriate for bench testing bias current with reasonable accuracy To understand its op eration first close switch S2 momentarily When S2 is opened then Nout C2 dt lp Typical Single Supply Applications v Additional single supply applications ideas can be found in the LM358 datasheet The LMC6032 is pin for pin compat ible with the LM358 and offers greater bandwidth and input resistance over the LM358 These features will improve the performance of many existing single supply applications Note however that the supply voltage range of the LMC6032 is smaller than that of the LM358 Instrumentation Amplifier Vin 91k 20k pot DS011135 14 Vout _ R2 2R1 R4 VIN R2 R3 if R1 R5 R3 R6 S2 push rod operated S1 push rod operated DS011135 12 FIGURE 8 Simple Input Bias Current Test Circuit A suitable capacitor for C2 would be a 5 pF or 10 pF silver mica NPO ceramic or air dielectric When determining the magnitude of I the leakage of the capacitor and socket must be taken into account Switch S2 should be left shorted most of the time or else the dielectric absorption of the ca pacitor C2 could cause errors Similarly if S1 is shorted momentarily while lea
9. al performance However if a guard ring is held within 5 mV of the inputs then even a resistance of 10 Q would cause only 0 05 pA of leakage current or perhaps a minor 2 1 degradation of the amplifier s performance See Figure 6a Figure 6b Figure 6c for typical connections of guard rings for standard op amp configurations If both inputs are active and at high impedance the guard can be tied to ground and still provide some protection see Figure 6d INB INB OUTB V O O O O Guard Ring DS011135 6 FIGURE 5 Example of Guard Ring in P C Board Layout OUTPUT DS011135 7 Guard Ring py OUTPUT INPUT bea DS011135 8 b Non Inverting Amplifier OUTPUT DS011135 9 DS011135 10 d Howland Current Pump FIGURE 6 Guard Ring Connections The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few circuits there is another technique which is even better than a guard ring on a PC board Dor t insert the amplifier s input pin into the board at all but bend it up in the air and use only air as an in sulator Air is an excellent insulator In this case you may have to forego some of the advantages of PC board con struction but the advantages are sometimes well worth the effort of using point to point up in the air wiring See Figure 7 www national com Application Hints Continued FEEDBACK CAPACITOR LLLL LPC Board P SO
10. ced to the level of the input offset voltage of the bottom amplifier typically 1 mV 11 www national com Physical Dimensions inches millimeters unless otherwise noted 0 189 0 197 4 800 5 004 0228 0 244 5 781 6 198 0 010 may 0 254 ww 1 2 3 4 d IDENT EM 9 150 0 157 3 810 3 988 0 010 0 020 455 X 0 053 0 069 1 346 1 753 0 254 0 508 E a MATE 0 004 0 010 ALL LEADS 0 102 0 254 es ee L Ah i ARA ew oam A i ki L J jon 10 102 i 0 008 0 010 0 050 0 014 0 020 t TYP TYP ALL LEADS ioo E OBA REV Hy Small Outline Dual In Line Package M Order Number LMC60321M NS Package Number M08A 0 373 0 400 9 474 10 16 0 090 04092 p14 ee 0 032 0 005 2 337 0 813 0 127 D 9 i 0 250 3 0 005 RAD PIN NO 1 cH e 6 35 0 127 PIN NO 1 n Fo OPTION 1 Y i 4 280 7 112 MIN 0 030 yay T OPTION 2 0 300 0 320 0 762 2 039 0 145 0 200 1 828 128 i 20 f 0 991 3 683 5 080 62 8 Y 0 130 0 005 y 3 302 0 127 opis A anne y 175 3555 hg 0 009 0 015 90 t4 0 508 0 229 0 381 TYP MIN 0 018 0 003 ig 0 457 0 076 0 100 0 010 a 2 540 0 254 ee a 143 40 0 060 ion 1 524 gt x 1 270 NOBE REV F Molded Dual In Line Package N Order Number LMC6032IN NS Package Number NO8E
11. e op amp This condition can also be stated in terms of the amplifiers low frequency noise gain To main tain stability a feedback capacitor will probably be needed if DS011135 3 FIGURE 1 LMC6032 Circuit Topology Each Amplifier The large signal voltage gain while sourcing is comparable to traditional bipolar op amps even with a 6000 load The gain while sinking is higher than most CMOS op amps due to the additional gain stage however under heavy load 6000 the gain will be reduced as indicated in the Electrical EE R Characteristics z 1 lt 46 X 27 X GBW X Rr X Cs IN www national com 6 Application Hints Continued where R E Rin is the amplifier s low frequency noise gain and GBW is the amplifiers gain bandwidth product An amplifiers low frequency noise gain is represented by the formula R Rin regardless of whether the amplifier is being used in an invert ing or non inverting mode Note that a feedback capacitor is more likely to be needed when the noise gain is low and or the feedback resistor is large If the above condition is met indicating a feedback capacitor will probably be needed and the noise gain is large enough that R 1 gt 2 GBW X Rf X Cg Rin the following value of feedback capacitor is recommended Cs e FE 1 Rin Re ay lt 2 GBW X Rp X Os IN the feedback capacitor should be Cs to E F VGBW x Re Note that these capac
12. ed unity gain compensation Socket etc and the feedback resistors create a pole in the driver In addition the output portion of the integrator is a feedback path In the following General Operational Amplifier push pull configuration for delivering heavy loads While Circuit Figure 2 the frequency of this pole is sinking current the whole amplifier path consists of three gain stages with one stage fed forward whereas while T 1 sourcing the path contains four gain stages with two fed fp 2aCgRp forward where Cs is the total capacitance at the inverting input in cluding amplifier input capacitance and any stray capaci tance from the IC socket if one is used circuit board traces etc and Rpis the parallel combination of Re and R This formula as well as all formulae derived below apply to in verting and non inverting op amp configurations When the feedback resistors are smaller than a few kQ the frequency of the feedback pole will be quite high since Cais generally less than 10 pF If the frequency of the feedback pole is much higher than the ideal closed loop bandwidth the nominal closed loop bandwidth in the absence of Cg the pole will have a negligible effect on stability as it will add only a small amount of phase shift However if the feedback pole is less than approximately 6 to 10 times the ideal 3 dB frequency a feedback capacitor Cp should be connected between the output and the invert ing input of th
13. edia Industrial 40 C lt Ty lt 85 C LMC6032IN 8 Pin NO8E Rail Molded DIP LMC60321M 8 Pin M08A Rail Small Outline Tape and Reel 1999 National Semiconductor Corporation DS011135 www national com Jeyiduy jeuonejedo jena SOND 2 099IN1 Absolute Maximum Ratings note 1 If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Differential Input Voltage Supply Voltage V V7 Output Short Circuit to V Output Short Circuit to V Lead Temperature Soldering 10 sec Storage Temperature Range Junction Temperature ESD Tolerance Note 4 Power Dissipation DC Electrical Characteristics Distributors for availability and specifications Supply Voltage Voltage at Output Input Pin V 0 3V V 0 3V Current at Output Pin 18 mA Current at Input Pin 5 mA Current at Power Supply Pin 35 mA Nub Operating Ratings note 1 Note 2 Temperature Range Supply Voltage Range 260 C Power Dissipation 65 C to 150 C Thermal Resistance Oja Note 12 150 C 8 Pin DIP 1000V 8 Pin SO Note 3 40 C lt T lt 85 C 4 75N to 15 5V Note 11 101 C W 165 C W Unless otherwise specified all limits guaranteed for T 25 C Boldface limits apply at the temperature extremes V 5V V GND OV Vom 1 5V Vour 2 5V and R gt 1M unless otherwise specified Symbo
14. haracteristics The load capacitance interacts with the op amp s output re sistance to create an additional pole If this pole frequency is sufficiently low it will degrade the op amp s phase margin so that the amplifier is no longer stable at low gains As shown in Figure 3 the addition of a small resistor 50O to 1000 in series with the op amp s output and a capacitor 5 pF to 10 pF from inverting input to output pins returns the phase margin to a safe value without interfering with lower frequency circuit operation Thus larger values of ca pacitance can be tolerated without oscillation Note that in all cases the output will ring heavily when the load capacitance is near the threshold for oscillation Cx 10 pF Rx 1000 T Cload DS011135 5 FIGURE 3 Rx Cx Improve Capacitive Load Tolerance Capacitive load driving capability is enhanced by using a pull up resistor to V Figure 4 Typically a pull up resistor con ducting 500 pA or more will significantly improve capacitive load responses The value of the pull up resistor must be de termined based on the current sinking capability of the ampli fier with respect to the desired output swing Open loop gain of the amplifier can also be affected by the pull up resistor see Electrical Characteristics M IN C I DS011135 22 FIGURE 4 Compensating for Large Capacitive Loads with a Pull Up Resistor PRINTED CIRCUIT BOARD LAYOUT FOR HIGH IMPE
15. itor values are usually significantly smaller than those given by the older more conservative for mula Cs Rin Cp SN Rr DS011135 4 Cs consists of the amplifier s input capacitance plus any stray capacitance from the circuit board and socket Cp compensates for the pole caused by Cs and the feedback resistor FIGURE 2 General Operational Amplifier Circuit Using the smaller capacitors will give much higher band width with little degradation of transient response It may be necessary in any of the above cases to use a somewhat larger feedback capacitor to allow for unexpected stray ca pacitance or to tolerate additional phase shifts in the loop or excessive capacitive load or to decrease the noise or band width or simply because the particular circuit implementa tion needs more feedback capacitance to be sufficiently stable For example a printed circuit board s stray capaci tance may be larger or smaller than the breadboard s so the actual optimum value for Ce may be different from the one estimated using the breadboard In most cases the value of Ce should be checked on the actual circuit starting with the computed value CAPACITIVE LOAD TOLERANCE Like many other op amps the LMC6032 may oscillate when its applied load appears capacitive The threshold of oscilla tion varies both with load and circuit gain The configuration most sensitive to oscillation is a unity gain follower See the Typical Performance C
16. l Parameter Conditions Typical LMC60321 Units Note 5 Limit Note 6 Vos Input Offset Voltage 1 9 mV 11 max AVos AT Input Offset Voltage 2 3 uV C Average Drift lg Input Bias Current 0 04 pA 200 max los Input Offset Current 0 01 pA 100 max Rin Input Resistance gt 1 TeraQ CMRR Common Mode OV Vom 12V 83 63 dB Rejection Ratio 15V 60 min PSRR Positive Power Supply 5V lt V lt 15V 83 63 dB Rejection Ratio Vo 2 5V 60 min PSRR Negative Power Supply OV lt V lt 10V 94 74 dB Rejection Ratio 70 min Vom Input Common Mode Vt 2 5V amp 15V 0 4 0 1 V Voltage Range For CMRR 2 50 dB 0 max V 1 9 V 2 3 V Vt 2 6 min Ay Large Signal R 2 KQ Note 7 2000 200 V mV Voltage Gain Sourcing 100 min Sinking 500 90 V mV 40 min Ri 6002 Note 7 1000 100 V mV Sourcing 75 min Sinking 250 50 V mV 20 min www national com 2 DC Electrical Characteristics continued Unless otherwise specified all limits guaranteed for T 25 C Boldface limits apply at the temperature extremes V 5V V GND OV Vem 1 5V Vout 2 5V and R gt 1M unless otherwise specified Symbol Parameter Conditions Typical LMC6032I Units Note 5 Limit Note 6 Vo Output Voltage Swing Vt 5V 4 87 4 20 V R 2 kQ to 2 5V 4 00 min 0 10 0 25 V 0 35 max Vt 5V 4 61 4 00 V R 6002 to 2 5V 3 80 min 0 30 0 63 V 0 75 max Vt 15V 14 63 13 50 V R 2 KQ to 7 5V 13 00 min 0 26 0 45 V 0 55 max Vt 15V 13
17. lity for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications Jeyiduy jeuonejedo jena SOND 2 092IN1
18. mbient temperature is Pp TJ max www national com 4 Typical Performance Characteristics Vg 7 5V T4 25 C unless otherwise specified Supply Current vs Supply Voltage 4 0 3 0 i Ty 125 C 20 4 3 Ty 25 C gt a Ty 559C 3 10 a 0 0 4 8 12 16 20 TOTAL SUPPLY VOLTAGE VDC DS011135 23 Output Characteristics Current Sourcing 10 W ER ag Sa aa ae A ae 5 g 0 01 0 001 0 01 0 1 1 10 100 OUTPUT SOURCE CURRENT mA DS011135 26 Open Loop Frequency Response 140 120 100 80 60 VOLTAGE GAIN dB 1 10 100 1k 10k 100k 1M 10M FREQUENCY Hz DS011135 29 Input Bias Current 10 E z 1 pa 5 3 n x m 0 1 5 2 z 0 01 0 25 50 75 100 125 150 TEMPERATURE C DS011135 24 Input Voltage Noise vs Frequency 120 100 80 60 40 VOLTAGE NOISE nV 4 Hz 20 10 100 1k 10k FREQUENCY Hz DS011135 27 Frequency Response vs Capacitive Load 27 UL TI 90 24 PHASE 80 GAIN dB PHASE DEGREES
19. ving S2 shorted bt our x C1 Cy where C is the stray capacitance at the input 5 0 Vbo and R4 R7 100 for circuit shown For good CMRR over temperature low drift resistors should be used Matching of R3 to R6 and R4 to R7 affects CMRR Gain may be adjusted through R2 CMRR may be adjusted through R7 Sine Wave Oscillator R2 C2 392k 200 pF C1 Vout 20k 20k 1N914 Cx 300 pF DS011135 15 Oscillator frequency is determined by R1 R2 C1 and C2 fosc 1 2nRC where R R1 R2 and C C1 C2 www national com Typical Single Supply Applications V 5 0 Vpc Continued 10 Hz Bandpass Filter C2 This circuit as shown oscillates at 2 0 kHz with a peak to peak output swing of 4 0V Low Leakage Sample and Hold Vour 560k 0 0068 uF OUTPUT 5V 0 1 uF POLYPROPYLENE OR POLYSTYRENE DS011135 18 DS011135 13 fo 10 Hz Q 24 Gain 8 8 1 Hz Square Wave Oscillator 1 Hz Low Pass Filter Maximally Flat Dual Supply Only 5V DS011135 16 R4 DS011135 19 10 Hz High Pass Filter 5V Q1 0 1 AF 2N3904 Vout DS011135 17 390k DS011135 20 fe 10 Hz d 0 895 Gain 1 2 dB passband ripple www national com 10 Typical Single Supply Applications v 5 0 Voc Continued High Gain Amplifier with Offset Voltage Reduction 22k 15k DS011135 21 Gain 46 8 Output offset voltage redu
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National Semiconductor LMC6032 CMOS Dual Operational Amplifier handbook