National Semiconductor LMC555 CMOS Timer handbook
Contents
1. 8 Pin SOIC MSOP 8 Bump micro SMD and MDIP Packages ve LMC555 8 i GROUND Ve DISCHARGE GROUND LMC555 R 100k R 100k2 TRIGGER DISCHARGE THRESHOLD TRIGGER OUTPUT THRESHOLD CONTROL VOLTAGE CONTROL _3 VOLTAGE RESET OUTPUT DS008669 1 Top View RESET DS008669 9 Top View bump side down LMCMOS is a trademark of National Semiconductor Corp 2000 National Semiconductor Corporation DS008669 www national com J WIL SOWO SSSOINT LMC555 Ordering Information Package Temperature Range Package Marking Industrial 40 C to 85 C 8 Lead Mini Small LMC555CMM ZC5 Transport Media 8 LeadSmall Outline LMC555CM LMC555CM SO LMC555CMX LMC555CM 2 5k Units Tape and Reel 1k Units Tape and Reel 3 5k Units Tape and Reel NSC Drawing MO8A Outline MSOP LMC555CMMX ZC5 8 Lead Molded Dip LMC555CN LMC555CN MDIP LMC555CBPX Metronome Circuit LMC555CBPEVAL micro SMD Marking Orientation Top View XT Date Code Ke 1 Corner Pin 1 is identified by lower left corner with respect to the text DS008669 23 Bumps are numbered counter clockwise www national com 2 Rails C 8 Bump micro SMD LMC555CBP 250 Units Tape and Reel 3k Units Tape and Reel N A MUAO8A NO8E BPAO8EFB Absolute Maximum Ratings Notes 2 3 Operating Ratings noies 2 3 If Military Aerospace specified devices are required Termperature Range 40 C to 85 C please contact the Nat2. millimeters unless otherwise noted Continued e 0 5 gt LAND PATTERN RECOMMENDATION TOP SIDE COATING NOTE 1 0 06 BUMP 1 CORNER 0 14 zy i h NOTE 4 SILICON 0 11 0 5 H 0 18 0 005 6f oho DIMENSIONS ARE IN MILLIMETERS BPA08XXX REV A NOTES UNLESS OTHERWISE SPECIFIED 1 EPOXY COATING 2 63Sn 37Pb EUTECTIC BUMP 3 RECOMMEND NON SOLDER MASK DEFINED LANDING PAD 4 PIN 1 IS ESTABLISHED BY LOWER LEFT CORNER WITH RESPECT TO TEXT ORIENTATION REMAINING PINS ARE NUMBERED COUNTERCLOCKWISE 5 XXX IN DRAWING NUMBER REPRESENTS PACKAGE SIZE VARIATION WHERE X1 IS PACKAGE WIDTH X2 IS PACK AGE LENGTH AND X3 IS PACKAGE HEIGHT 6 REFERENCE JEDEC REGISTRATION MO 211 VARIATION BC micro SMD Package NS Package Number BPAO8EFB X 1 387 X 1 412 X 0 850 11 www national com SSSOINT LMC555 CMOS Timer Notes LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which a are intended for surgical implant support device or system whose failure to perform into the body or b support or sustain life and can be reasonably expected to cause the failure of whose failu
3. 5 For device pinout please refer to table 1 Test Circuit Note 5 Maximum Frequency Test Circuit Note 5 TRIGGER 10ka OUTPUT OUTPUT Output Thresh LMC555 LMC555 Reset Control RESET Reset Control 1 1 Vs DS008669 3 DS008669 2 TABLE 1 Package Pinout Names vs Pin Function Package Pin numbers 8 Pin SO MSOP and MDIP 8 Bump micro SMD Output Reset www national com 4 Application Info MONOSTABLE OPERATION In this mode of operation the timer functions as a one shot Figure 1 The external capacitor is initially held discharged by internal circuitry Upon application of a negative trigger pulse of less than 1 3 Vs to the Trigger terminal the flip flop is set which both releases the short circuit across the capaci tor and drives the output high Thresh Je Output t lt EE LMC555 I sl Reset Control S DS008669 4 FIGURE 1 Monostable One Shot The voltage across the capacitor then increases exponen tially for a period of t4 1 1 RaC which is also the time that the output stays high at the end of which time the voltage equals 2 3 Vs The comparator then resets the flip flop which in turn discharges the capacitor and drives the output to its low state Figure 2 shows the waveforms generated in this mode of operation Since the charge and the threshold level of the comparator are both directly proportional to supply voltage the timing internal is indepe
4. 0 O LMC555CN amp nbs 0 O 0 February 2000 National Semiconductor LMC555 CMOS Timer General Description Features The LMC555 is a CMOS version of the industry standard Less than 1 mW typical power dissipation at 5V supply 555 series general purpose timers In addition to the stan 3 MHz astable frequency capability dard package SOIC MSOP and MDIP the LMC555 is also 1 5V supply operating voltage guaranteed available in a chip sized package 8 Bump micro SMD using Output fully compatible with TTL and CMOS logic at 5V National s micro SMD package technology The LMC555 of supply fers the same capability of generating accurate time delays and frequencies as the LM555 but with much lower power dissipation and supply current spikes When operated as a m Tested to 10 mA 50 mA output current levels E one shot the time delay is precisely controlled by a single a a a a Reduced supply current spikes during output transitions Extremely low reset trigger and threshold currents external resistor and capacitor In the stable mode the oscil Excellent temperature stability lation frequency and duty cycle are accurately set by two ex Pin for pin compatible with 555 series of timers ternal resistors and one capacitor The use of National Semi Available in 8 pin MSOP Package and 8 Bump micro conductor s LMCMOS process extends both the frequency SMD package range and low supply capability Block and Connection Diagrams
5. NG FREQUENCY Hz DS008669 13 FIGURE 6 Free Running Frequency FREQUENCY DIVIDER The monostable circuit of Figure 1 can be used as a fre quency divider by adjusting the length of the timing cycle Figure 7shows the waveforms generated in a divide by three circuit www national com DS008669 14 Voc 5V Top Trace Input 4V Div TIME 20 us Div Middle Trace Output 2V Div Ra 9 1 kQ Bottom Trace Capacitor 2V Div C 0 01pF FIGURE 7 Frequency Divider Waveforms PULSE WIDTH MODULATOR When the timer is connected in the monostable mode and triggered with a continuous pulse train the output pulse width can be modulated by a signal applied to the Control Voltage Terminal Figure 8 shows the circuit and in Figure 9 are some waveform examples Trigger Disch OUTPUT Output Thresh k LMC555 I RESET Reset Control Vs O Modulation Input DS008669 20 FIGURE 8 Pulse Width Modulator DS008669 15 Vcc 5V Top Trace Modulation 1V Div TIME 0 2 ms Div Bottom Trace Output Voltage 2V Div Ra 9 1 kQ C 0 01pF FIGURE 9 Pulse Width Modulator Waveforms PULSE POSITION MODULATOR This application uses the timer connected for astable opera tion as in Figure 10 with a modulating signal again applied to the control voltage terminal The pulse position varies with Application Info continued the modulating sign
6. al since the threshold voltage and hence the time delay is varied Figure 11 shows the waveforms generated for a triangle wave modulation signal Trigger Disch OUTPUT Output Thresh LMC555 RESET Reset Control O Modulation Input DS008669 21 FIGURE 10 Pulse Position Modulator Vcc 5V Top Trace Modulation Input 1V Div TIME 0 1 ms Div Bottom Trace Output Voltage 2V Div Ra 3 9 kQ Rg 3kQ C 0 01uF FIGURE 11 Pulse Position Modulator Waveforms 50 DUTY CYCLE OSCILLATOR The frequency of oscillation is f 1 1 4 RoC OUTPUT ALTERNATE Output Thresh OUTPUT LMC555 RESET o Reset Control Vs DS008669 6 FIGURE 12 50 Duty Cycle Oscillator www national com SSSOINT LMC555 Physical Dimensions inches millimeters unless otherwise noted 0 189 0 197 4 800 5 004 E 83 7 6 5 0 228 0 244 5 791 6 198 0 010 wax N 0 254 ee LEADNO 1 1 2 3 4 ai A DENT TYP 0 150 0 457 3 810 3 988 0 053 0 069 0 010 0 020 5 45 ye jg 0 053 0 068 2 010 0 020 1 346 1 753 0 254 0 508 Suan os am 102 0 254 ALL LEADS lt 4 4 Anh i i aa SEATING Fo 0 008 A 7 th dL ma 0 102 0 008 0 010 jozoa o254 MULMEAD TIPS 0 016 0 050 10 398 aa ad ae a 7 508 0356 0508 TYP ALL LEADS 0 406 1 270 ie 0 008 typ oa TYP ALL LEADS 0 203 MOBA REV H Molded Small Outlin
7. d Vs 1 5V 0 9 1 1 1 25 5V 1 0 1 1 1 20 Ys 12V 1 0 1 1 1 25 At AVs Timing Shift with Supply 5V 1V os Temperature ve ed lt lt 85 C tr tF Output Rise and ae Fred Test Circuit ns Fall Times 5V C 10 pF ms 3 www national com SSSOINT LMC555 Electrical Characteristics notes 1 2 Test Circuit T 25 C all switches open RESET to Vs unless otherwise noted Continued Symbol Parameter Conditions Typ Units Limits tpp Trigger Propagation Delay Vs 5V Measure Delay 100 ns from Trigger to Output Note 1 All voltages are measured with respect to the ground pin unless otherwise specified Note 2 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Operating Ratings indicate conditions for which the device is func tional but do not guarantee specific performance limits Electrical Characteristics state DC and AC electrical specifications under particular test conditions which guar antee specific performance limits This assumes that the device is within the Operating Ratings Specifications are not guaranteed for parameters where no limit is given however the typical value is a good indication of device performance Note 3 See AN 450 for other methods of soldering surface mount devices and also AN 1112 for micro SMD considerations Note 4 If the RESET pin is to be used at temperatures of 20 C and below Vs is required to be 2 0V or greater Note
8. d as shown in Figure 4 Trigger and Threshold terminals connected together it will trigger itself and free run as a multivibrator The external capacitor charges through Ra Rpg and discharges through Rg Thus the duty cycle may be precisely set by the ratio of these two resistors OUTPUT Output Thresh LMC555 RESET Reset Control Vs DS008669 5 FIGURE 4 Astable Variable Duty Cycle Oscillator In this mode of operation the capacitor charges and dis charges between 1 3 Vs and 2 3 Vs As in the triggered mode the charge and discharge times and therefore the fre quency are independent of the supply voltage Figure 5 shows the waveform generated in this mode of operation www national com SSSOINT LMC555 Application Info Continued DS008669 12 Vcc 5V Top Trace Output 5V Div TIME 20 us Div Bottom Trace Capacitor Voltage 1V Div Ra 3 9kQ Rp 9kQ C 0 01pF FIGURE 5 Astable Waveforms The charge time output high is given by t4 Ln2 Ra Rg C And the discharge time output low by to Ln2 Rg C Thus the total period is T t t Ln2 Ra Rg C The frequency of oscillation is 1 1 44 T Ra 2Rg C Figure 6 may be used for quick determination of these RC Values The duty cycle as a fraction of total period that the output is low is C CAPACITANCE uF 0 001 0 1 100 1k 10k 100k f FREE RUNNI
9. e SO Package M NS Package Number M08A www national com 8 Physical Dimensions inches millimeters unless otherwise noted Continued 0 118 0 004 340 1 0 19340 004 4 940 1 0 11840 004 340 1 0 043 1 09 0 002 0 05 A 0 002 0 006 0 06 0 15 P L 0 002 0 05 B cO 0 953 0 007 0 002 0 012 0 004 al Le 0 02140 005 a i TYP 0 5340 12 0 6 TYP 2005 0 034 _ 0 0375 SEATING PLANE 0 18 0 05 TYP MUAOBA REV B 8 Lead 0 118 Wide Molded Mini Small Outline Package NS Package Number MUA08A www national com SSSOINT LMC555 Physical Dimensions inches millimeters unless otherwise noted Continued 0 092 2 337 ne PIN NO 1 IDENT OPTION 1 0 280 95 5 0 009 0 015 0 229 0 381 0 045 0 015 Lan lt mg 0 030 ax 0 300 0 320 0 762 c gt 7 628 128 0 373 0 400 9 474 10 16 0 090 2 286 0 250 0 005 6 35 0 127 0 032 0 005 0 813 0 127 RAD OPTION 2 0 145 0 200 3 683 5 080 0 065 90 4 TYP 0 100 0 010 2 540 0 254 1 143 0 381 isa 0 050 IEN 1 270 www national com Molded Dual in line Package N NS Package Number NO8E ae BE 0 130 0 005 3 302 0 127 0 125 0 140 3 175 3 556 0 018 0 003 0 457 0 076 0 020 0 508 MIN NO8E REV F Physical Dimensions inches
10. ional Semiconductor Sales Office ante eaten ies Thermal Resistance Ja Note 2 Distributors for availability and specifications SO 8 lead Small Outline 169 C W Supply Voltage V 15V MSOP 8 lead Mini Small Input Voltages Vraic Vres Veta Outline 225 C W VTHRESH 0 3V to Vs 0 3V MDIP 8 lead Molded Dip 111 C W Output Voltages Vo Vpis 15V 8 Bump micro SMD 220 C W Output Current lo Ipis 100 mA Maximum Allowable Power Storage Temperature Range 65 C to 150 C Dissipation 25 C Soldering Information MDIP 8 1126mW MDIP Soldering 10 seconds 260 C SO 8 740mW SOIC MSOP Vapor Phase 60 MSOP 8 555mW sec 215 C 8 Bump micro SMD 568mW SOIC MSOP Infrared 15 sec 220 C Note See AN 450 Surface Mounting Methods and Their Effect on Product Reliability for other methods of soldering surface mount devices Electrical Characteristics notes 1 2 Test Circuit T 25 C all switches open RESET to Vs unless otherwise noted Units Limits Supply Current pA Control Voltage Vs 1 5V 5V V Vs 12V Discharge Saturation Vs 1 5V Ibis 1 MA mV Voltage Vs 5V Ibis 10 mA VoL Output Voltage Low Vs 1 5V lo 1 mA s 5V lo 8 mA V Vs 12V lo 50 mA Vou Output Voltage Vs 1 5V lo 0 25 mA High Vs 5V lo 2 mA V s 12V lo 10 mA Vtria Trigger Voltage 1 5V v imma Tigger Current C pA Vres Reset Voltage 1 5V Note 4 0 4 v 12V 0 4 t Timing Accuracy SW 2 4 Close
11. ndent of supply DS008669 10 Voc 5V Top Trace Input 5V Div TIME 0 1 ms Div Middle Trace Output 5V Div Ra 9 1kQ Bottom Trace Capacitor Voltage 2V Div C 0 01uF FIGURE 2 Monostable Waveforms Reset overrides Trigger which can override threshold Therefore the trigger pulse must be shorter than the desired ty The minimum pulse width for the Trigger is 20ns and it is 400ns for the Reset During the timing cycle when the output is high the further application of a trigger pulse will not effect the circuit so long as the trigger input is returned high at least 10us before the end of the timing interval However the cir cuit can be reset during this time by the application of a negative pulse to the reset terminal The output will then re main in the low state until a trigger pulse is again applied When the reset function is not use it is recommended that it be connected to V to avoid any possibility of false triggering Figure 3 is anomograph for easy determination of RC values for various time delays Note In monstable operation the trigger should be driven high before the end of timing cycle 100 gt Ne 10 aa Ww Ey Df Y ee XS SYS 1 eA S V E NAS O R a o N lt oO I 0 01 0 001 10 s100 us1ms10ms100ms is 10s 100s ta TIME DELAY DS008669 11 FIGURE 3 Time Delay ASTABLE OPERATION If the circuit is connecte
12. re to perform when properly used in the life support device or system or to affect its accordance with instructions for use provided in the safety or effectiveness labeling can be reasonably expected to result in a significant injury to the user National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Asia Pacific Customer Japan Ltd Americas Fax 49 0 180 530 85 86 Response Group Tel 81 3 5639 7560 Tel 1 800 272 9959 Email europe support nsc com Tel 65 2544466 Fax 81 3 5639 7507 Fax 1 800 737 7018 Deutsch Tel 49 0 69 9508 6208 Fax 65 2504466 Email support nsc com English Tel 44 0 870 24 0 2171 Email ap support nsc com www national com Frangais Tel 33 0 1 41 91 8790 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications
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National Semiconductor LMC555 CMOS Timer handbook