National LMH6582 handbook
Contents
1. 10 0 1 4 33 t 49 32 1240 2 10 0 1 a EXPOSED PAD wa a my l 64X 0 3 0 5 4 LAND PATTERN RECOMMENDATION PIN 1 ID alll 6 4X 0 089 BO b 60x 0 5 SEE DETAIL A 0 09 0 20 11 13 amp 0 25 GAGE PLANE 0 08 0 20 1 2 1410 0 SEATING PLANE 0 7 08 MIN 0 2 MIN DIMENSIONS ARE IN MILLIMETERS DETAIL A TYPICAL VXE64A Rev 64 Pin Exposed Pad QFP NS Package Number VXE64A 15 www national com C8S9HIN I LMH6582 16x8 550 MHz Analog Crosspoint Switch Gain of 1 Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION NATIONAL PRODUCTS NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE NO LICENSE WHETHER EXPRESS IMPLIED ARISING BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT NATIONAL S PRODUCT WARRANTY EXCEPT WHERE MANDATED BY GOVER2. National Semiconductor LMH6582 February 2007 16x8 550 MHz Analog Crosspoint Switch Gain of 1 Features General Description The LMH family of products is joined by the LMH6582 a high speed non blocking analog crosspoint switch The LMH6582 is designed for high speed DC coupled analog signals like high resolution video UXGA and higher The LMH6582 has 16 inputs and 8 outputs The non blocking ar chitecture allows an output to be connected to any input including an input that is already selected With fully buffered inputs the LMH6582 can be impedance matched to nearly any source impedance The buffered outputs of the LMH6582 can drive up to two back terminated video loads 75Q load The outputs and inputs also feature high impedance inactive states allowing high performance input and output expansion for array sizes such as 16 x 16 or 32 x 8 by combining two devices The LMH6582 is controlled with a 4 pin serial inter face Both single serial mode and addressed chain modes are available The LMH6582 comes in a 64 pin thermally enhanced TQFP package It also has diagonally symmetrical pin assignments to facilitate double sided board layouts and easy pin connec tions for expansion The package has an exposed thermal pad on the bottom of the package Connection Diagram O 20214402 LMH is a registere
3. OUTPUTS 0 01 0 1 FREQUENCY MHz 20214420 pi wi 100 20214422 Vour Vour OUTPUT SIGNAL dBc 2 Vpp Pulse Response 1 5 5 10 15 20 25 30 35 40 45 50 TIME ns 20214419 2 Vpp Pulse Response AB 0 5 10 15 20 25 30 35 40 45 50 TIME ns 20214421 Off Isolation 110 0 001 0 01 1 1 MHz 20214423 www national com C8S9HIN I LMH6582 DISTORTION dBc DISTORTION dBc 9 www national com 70 Vi vs Frequency V 5V Loure FREQUENCY MHz 20214427 HD2 vs Frequency A A vour 3Y ap 1 FREQUENCY MHz 20214429 Enabled Output Impedance a an 1 Hee HH Ht 0 1 1 10 100 1000 FREQUENCY MHz 20214413 DISTORTION dBc DISTORTION dBc Z 10000 HD2 vs Frequency 55 verse UI 60 FR 1000 T TI AAT I H Yours v 3927 2 N z NUE AA Yoro 1 10 100 FREQUENCY MHz 20214428 HD3 vs Frequency 1000 WK vorz oz ZO ANI 1 10 100 FREQUENCY MHz 20214430 Disabled Output Impedance 1000 0 1 1 10 100 1000 FREQUENCY MHz 20214414 Applica
4. COP TIN FREQUENCY MHz Small Signal Bandwidth FREQUENCY MHz Group Delay 100 200 300 FREQUENCY MHz PHASE 20214435 PHASE 20214434 20214424 www national com C8S9HIN I LMH6582 GROUP DELAY ns NORMALIZED GAIN dB Vout www national com Input Expansion Frequency Response CONNECTED RESTY NORMALIZED GAIN dB 710 100 FREQUENCY MHz 0 20214431 Group Delay Vout RL 1500 BROADCAST FREQUENCY MHz 20214425 DC Transfer Function Your V 20214416 Input Expansion Frequency Response OUTPUTS CONNECTED DIRECTLY _ a noexpansion 1 0 Your ee 710 100 1000 FREQUENCY MHz 20214432 DC Transfer Function 3 2 1 1 Vin 20214415 4 Pulse Response ed ae ee P EF tt yt _ see 2 5 0 5 10 15 20 25 30 35 40 45 50 TIME ns 20214417 Vout Your V CROSSTALK dBc 1 Vpp Pulse Response a LEE TE TIME ns 1 Vpp Pulse Response LTT T 0 75 0 5 10 15 20 25 30 35 40 45 50 20214418 5 0 5 10 15 20 25 30 35 40 45 50 TIME ns All Hostile INPUTS amp OUTPUTS AM A I ANNI i
5. Miscellaneous Performance Rin Input Resistance Non Inverting Input Capacitance Non Inverting Ro Output Resistance Enabled Closed Loop Enabled mQ Output Resistance Disabled Output Resistance Disabled Disabled Disabled kQ CMVR Input Common Mode Voltage V Range Digital Control 5V Electrical Characteristics 5 Unless otherwise specified typical conditions 25 C Ay 1 Vs 5V R 1000 Boldface limits apply at the temperature extremes Symbol Parameter Conditions Min Typ Max Units Note 8 Note 7 Note 8 Frequency Domain Performance SSBW 3 dB Bandwidth 0 5 Note 11 456 5 O 2V Step 10 to 90 di6 rms t Fall Time 1V Step 10 to 90 16 rs 1V Step 10 to 90 ns 05 Distortion And Noise Response npr etoned Nace Curent soL 1 005 Static DC Performance mV 3 www national com C8S9HIN I LMH6582 Typ Max Units Symbol Parameter Conditions Note 8 Note 7 Note 8 Output Offset Voltage Average Note 10 Drift 3 gt Miscellaneous Performance Rin Input Resistance Input Capacitance Ro Output Resistance Output Resistance CMVR Input Common Mode Voltage R
6. the Chip select function is provided by the presence or absence of the clock signal The programming format of the incoming serial data is se lected by the MODE pin When the mode pin is HIGH the crosspoint can be programmed one output at a time by en tering a string of data that contains the address of the output that is going to be changed Addressed Mode When the mode pin is LOW the crosspoint is in Serial Mode In this mode the crosspoint accepts a 40 bit array of data that pro grams all of the outputs In both modes the data fed into the chip does not change the chip operation until the Configure pin is pulsed high The configure and mode pins are inde pendent of the chip select pin www national com C8S9HIN I LMH6582 Uda Timing Diagram for Serial Mode Tp 20214409 Serial Mode Data Frame First 2 Words Input Address Input Address tss fot 1 68 8 fot 1 1 4 b 6 7 8 9 Off TRI STATE Bit 0 is first bit clocked into device Serial Mode Data Frame Continued uss fon Serial Mode Data Frame Continued uss 66 fon Serial Mode Data Frame Last 2 Words Output 6 Input Address Input Address uss wee iss jonas Bit 39 is last bit clocked into device www national com 12 Serial programming mode is the mode selected by bringi
7. this the termination resistors of both crosspoints should be adjusted to approximately 800 This will provide very good matching but the gain accuracy of the system will now be dependent on the process variations of the crosspoint resistors which have a variability of approxi mately 20 The LMH6582 has fully buffered inputs and outputs The in puts provide a low load high impedance input and ensure maximum performance from a variety of signal sources The fully buffered outputs will drive up to two back terminated video loads When disabled the outputs are in a high impedance state When making thermal calculations the out put loading conditions will be a key consideration Please see the section on thermal management 4x4 2 22 4 4 OUT OUT FIGURE 1 Output Expansion IN 4x4 IN 4x4 20214403 w 20214404 FIGURE 2 Input Expansion with Shared Termination Resistors www national com C8S9HIN I LMH6582 20214405 FIGURE 3 Input Expansion with Separate Termination Resistors OUTPUTS CONNECTED DIRECTLY 4 75Q RESISTOR ON EACH OUTPUT NORMALIZED GAIN dB FREQUENCY MHz 20214431 FIGURE 4 Input Expansion Frequency Response with Direct Connection and Isolation Resistors www national com NO EXPANSION NUTT NORMALIZED GAIN dB FREQUENCY MHz 20214432 FIGURE 5 Input Expa
8. NMENT REQUIREMENTS TESTING OF ALL PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED NATIONAL ASSUMES NO LIABILITY FOR APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND APPLICATIONS USING NATIONAL COMPONENTS PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE NATIONAL COMPONENTS BUYERS SHOULD PROVIDE ADEQUATE DESIGN TESTING AND OPERATING SAFEGUARDS EXCEPT AS PROVIDED IN NATIONAL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS NATIONAL ASSUMES NO LIABILITY WHATSOEVER AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE AND OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION As used herein Life support devices or systems are devices which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user A critical component is any component in a life support de
9. ange lo Output Current Sourcing Digital Control Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Operating Ratings indicate conditions for which the device is intended to be functional but specific performance is not guaranteed For guaranteed specifications see the Electrical Characteristics tables Note 2 Human Body Model applicable std MIL STD 883 Method 3015 7 Machine Model applicable std JESD22 A115 A ESD MM std of JEDEC Field Induced Charge Device Model applicable std JESD22 C101 C ESD FICDM std of Note 3 The maximum output current lour is determined by device power dissipation limitations 100 300 2 3 42 76 12 60 J O N O I lt Note 4 The maximum power dissipation is a function of T ymax The maximum allowable power dissipation at any ambient temperature is Pp Oja All numbers apply for packages soldered directly onto a PC Board Note 5 Electrical Table values apply only for factory testing conditions at the temperature indicated No guarantee of parametric performance is indicated in the electrical tables under conditions different than those tested Note 6 Slew Rate is the average of the rising and falling edges Note 7 Typical values represent the most likely parametric norm as determin
10. d having two connected inputs active is a valid state Crosspoint ex pansion as detailed above has the advantage that the signal path has only one crosspoint in it at a time Expansion meth ods that have cascaded stages will suffer bandwidth loss far greater than the small loading effect of parallel expansion Output expansion is very straight forward Connecting the in puts of two crosspoint switches has a very minor impact on performance Input expansion requires more planning As show in Figure 1 and Figure 2 there are two ways to connect the outputs of the crosspoint switches In Figure 2 the cross point switch outputs are connected directly together and share one termination resistor This is the easiest configura tion to implement and has only one drawback Because the disabled output of the unused crosspoint only one output can be active at a time has a small amount of capacitance the frequency response of the active crosspoint will show peak ing This is illustrated in Figure 4 and Figure 5 In most cases this small amount of peaking is not a problem As illustrated in Figure 1 each crosspoint output can be given its own termination resistor This results in a frequency re sponse nearly identical to the non expansion case There is one drawback for the gain of 2 crosspoint and that is gain error With a 75Q termination resistor the 12500 resistance of the disabled crosspoint output will cause a gain error In order to counter act
11. d trademark of National Semiconductor Corporation TRI STATE is a registered trademark of National Semiconductor Corporation 2007 National Semiconductor Corporation 202144 16 inputs and 8 outputs 64 pin exposed pad TQFP package 3 dB bandwidth 0 5 3 dB bandwidth Voy 2Vpp Fast slew rate Low crosstalk 10 MHz 100 MHz 70 50 dBc Easy to use serial programming 4 wire bus Two programming modes Serial amp addressed modes Symmetrical pinout facilitates expansion Output current Two gain options 500 MHz 400 MHz 3000 V us 60 mA Applications Studio monitoring production video systems Conference room multimedia video systems KVM keyboard video mouse systems Security surveillance systems Multi antenna diversity radio Video test equipment Medical imaging Wide band routers amp switches Block Diagram SWITCH MATRIX 16 INPUTS 000 8 OUTPUTS CONFIGURATION REGISTER LOAD REGISTER CFG BCST RST DATA IN CS CLK MODE DATA OUT 20214411 www national com JO JUIOdSSOD ZHIN OSS 8X9 Z8S9HNT LMH6582 Absolute Maximum Ratings Note 1 Storage Temperature Range 65 C to 150 C Soldering Information If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Infrared or onvgenon 20 sec 235 Distributors for availabili
12. ed at the time of characterization Actual typical values may vary over time and will also depend on the application and configuration The typical values are not tested and are not guaranteed on shipped production material Note 8 Room Temperature limits are 100 production tested at 25 C Factory testing conditions result in very limited self heating of the device such that Tj T Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control SQC methods Note 9 Negative input current implies current flowing out of the device Note 10 Drift determined by dividing the change in parameter at temperature extremes by the total temperature change Note 11 This parameter is guaranteed by design and or characterization and is not tested in production Ordering Information Package Package Marking Transport Media NSC Drawing 64 Pin QFP LMH6582YA LMH6582YA 160 Units Tray VXE64A www national com 4 GAIN dB GAIN dB NORMALIZED GAIN dB 1 Vpp Bandwidth PHASETTTN PHASE FREQUENCY MHz 20214436 Small Signal Bandwidth ST Tt PHASE FREQUENCY MHz 20214433 Frequency Response 1 kQ Load V PHASE FREQUENCY MHz 20214426 GAIN dB GAIN dB GROUP DELAY ns 1 00 0 50 0 00 0 50 1 Vpp Bandwidth LT
13. guration the device draws only 20 mA The reset pin can used as a shutdown function to reduce power consumption The other special control pin is the broadcast BCST pin The BCST pin is also active high and sets all the outputs to the on state connected to input This is sometimes referred to as broadcast mode where input 0 is broadcast to all 8 outputs www national com C8S9HIN I LMH6582 THERMAL MANAGEMENT The LMH6582 is packaged a thermally enhanced Quad Pack package Even so it is a high performance device that produces a significant amount of heat With a 5V supply the LMH6582 will dissipate approximately 1 1W of idling power with all outputs enabled Idling power is calculated based on the typical supply current of 110 mA 10V supply voltage This power dissipation will vary with the range of 800 mW to 1 4W due to process variations In addition each equivalent video load 1500 connected to the outputs should be bud geted 30 mW of power For a typical application with one video load for each output this would be a total power of 1 14 W With a of 27 C W this will result in the silicon being 31 C over the ambient temperature A more aggressive applica tion would be two video loads per output which would result in 1 38W of power dissipation This would result in a 37 C temperature rise For heavier loading the QFP package ther mal performance can be significantly enhanced with an ex ternal
14. heat sink and by providing for moving air ventilation Also be sure to calculate the increase in ambient temperature from all devices operating in the system case Because of the high power output of this device thermal management should be considered very early in the design process Generous www national com 14 passive venting and vertical board orientation may avoid the need for fan cooling or heat sinks Also the LMH6582 can be operated with a 3 3V power supply This will cut power dis sipation substantially while only reducing bandwidth by about 10 2 Vpp output The LMH6582 is fully characterized and factory tested at the 3 3V power supply condition for appli cations where reduced power is desired PRINTED CIRCUIT LAYOUT Generally a good high frequency layout will keep power sup ply and ground traces away from the input and output pins Parasitic capacitances on these nodes to ground will cause frequency response peaking and possible circuit oscillations see Application Note OA 15 for more information If digital control lines must cross analog signal lines particularly in puts it is best if they cross perpendicularly National Semi conductor suggests the following evaluation boards as a guide for high frequency layout and as an aid in device testing and characterization Device Package Evaluation Board Part Number LMH6582 64 Pin TQFP LMH730156 Physical DIMENSIONS inches millimeters unless otherwise noted
15. lexibility The first stage of the control logic is tied directly to the crosspoint switching matrix This logic consists of one register for each output that stores the on off state and the address of which input to connect to These registers are not directly accessible by the user The second level of logic is another bank of reg isters identical to the first but set up as shift registers These registers are accessed by the user via the serial input bus As described further below there are two modes for programing the LMH6582 Serial Mode and Addressed Mode The LMH6582 is programmed via a serial input bus with the support of 4 other digital control pins The Serial bus consists of a clock pin CLK a serial data in pin DIN and a serial data out pin Dour The serial bus is gated by a chip select pin CS The chip select pin is active low While the chip se lect pin is high all data on the serial input pin and clock pins is ignored When the chip select pin is brought low the internal logic is set to begin receiving data by the first positive transi tion O to 1 of the clock signal The chip select pin must be brought low at least 5 ns before the first rising edge of the clock signal The first data bit is clocked in on the next nega tive transition 1 to 0 All input data is read from the bus on the negative edge of the clock signal Once the last valid data has been clocked in the chip select pin must go high and then the clock
16. mming mode To use this feature serial data is clocked into the first chip DIN pin and the next chip DIN pin is connected to the Doyr pin of the first chip Both chips may share a chip select signal or the second chip can be enabled separately When the chip select pin goes low on both chips a double length word is clocked into the first chip As the first word is clocking into the first chip the second chip is receiving the data that was originally in the shift register of the first chip When a full 40 bits have been clocked into the first chip the next clock cycle begins moving the first frame of the new configuration data into the second chip With a full 80 clock cycles both chips have valid data and the chip select pin of both chips should be brought high to prevent the data from overshooting A configure pulse will activate the new config uration on both chips simultaneously or each chip can be configured separately The mode chip select configure and 13 clock pins of both chips can be tied together and driven from the same sources SPECIAL CONTROL PINS The LMH6582 has two special control pins that function in dependent of the serial control bus One of these pins is the reset RST pin The RST pin is active high meaning that a logic 1 level the chip is configured with all outputs disabled and in a high impedance state The RST pin programs all the registers with input address 0 and all the outputs are turned off In this confi
17. ng the MODE pin low In this mode a stream of 40 bits programs all 8 outputs of the crosspoint The data is fed to the chip as shown in the table above The table is arranged such that the first bit clocked into the crosspoint register is labeled bit num ber 0 The register labeled Load Register in the block diagram is a shift register If the chip select pin is left low after the valid data is shifted into the chip and if the clock signal keeps run ning then additional data will be shifted into the register and the desired data will be shifted out Timing Diagram Addressed programming mode makes it possible to change only one output register at a time To utilize this mode the mode pin must be High All other pins function the same as in serial programming mode except that the word clocked in is 8 bits and is directed only at the output specified In ad dressed mode the data format is shown below in the table titled Addressed Mode Word Format General Case Addressed Mode Timing Diagram 1 4 T5 16 7 Ty Tio CLK 0 CS_N 0 1 CFG 0 1 HIGH IMPEDANCE 20214410 Addressed Mode Word Format General Case Output Address Input Address TRI STATE 0 23 4 b Bit is first bit clocked into device DAISY CHAIN OPTION IN SERIAL MODE The LMH6582 supports daisy chaining of the serial data stream between multiple chips This feature is available only in the Serial progra
18. nsion Frequency Response DRIVING CAPACITIVE LOADS Capacitive output loading applications will benefit from the use of a series output resistor Capacitive loads of 5 pF to 120 pF are the most critical causing ringing frequency re sponse peaking and possible oscillation The chart Suggest ed Roy VS Load gives a recommended value for selecting a series output resistor for mitigating capacitive loads The values suggested in the charts are selected for 0 5 or less of peaking in the frequency response This gives good compromise between settling time and bandwidth For applications where maximum frequency response is needed and some peaking is tolerable the value of be duced slightly from the recommended values When driving transmission lines the 50Q 750 matching resistor makes the series output resistor unnecessary USING OUTPUT BUFFERING TO ENHANCE BANDWIDTH AND INCREASE RELIABILITY The LMH6582 crosspoint switch can offer enhanced band width and reliability with the use of external buffers on the outputs The bandwidth is increased by unloading the outputs and driving the high impedance of an external buffer See the Frequency Response 1 Load curve in the Typical Perfor mance section for an example of bandwidth achieved with less loading on the outputs For this technique to provide maximum benefit a very high speed amplifier such as the LMH6703 should be used As shown in Figu
19. re 6 there is an optional resistor Roy between the LMH6582 and the buffer input This resistor will isolate the amplifier input capacitance and board capacitance from the crosspoint switch output Any traces longer than 1 cm will most likely require some termi nation resistance as shown Besides offering enhanced bandwidth performance using an external buffer provides for greater system reliability The first advantage is to reduce thermal loading on the crosspoint switch This reduced die temperature which increases the life of the crosspoint The second advantage is enhanced ESD reliability It is impossible to build high speed devices that can withstand all possible ESD events With external buffers the crosspoint switch is isolated from ESD events on the external system connectors LMH6703 LMH6582 OUTPUT BUFFER 20214412 FIGURE 6 Buffered Output In this example is to improve settling time by isolating the LMH6703 input capacitance from the crosspoint output The resistor R is optional It may improve performance providing a small DC load for the LMH6582 output stage CROSSTALK When designing a large system such as a video router crosstalk can be a very serious problem Extensive testing in our lab has shown that most crosstalk is related to board lay out rather than occurring in the crosspoint switch There are many ways to reduce board related crosstalk Using con trolled impedance lines is an importan
20. signal must make at least one low to high transition Otherwise invalid data will be clocked into the chip The data clocked into the chip is not transferred to the crosspoint matrix until the CFG pin is pulsed high This is the case regardless of the state of the Mode pin The CFG pin is not dependent on the state of the Chip select pin If no new data is clocked into the chip subsequent pulses on the CFG pin will have no effect on device operation There are two ways to connect the serial data pins The first way is to control all 4 pins separately and the second option is to connect the CFG and the CS pins together for a 3 wire interface The benefit of the 4 wire interface is that the chip can be configured independently of the CS pin This would be an advantage in a system with multiple crosspoint chips where all of them could be programmed ahead of time and then configured simultaneously The 4 wire solution is also helpful in a system that has a free running clock on the CLK pin In this case the CS pin needs to be brought high after the last valid data bit to prevent invalid data from being clocked into the chip The three wire option provides the advantage of one less pin to control at the expense of having less flexibility with the configure pin One way around this loss of flexibility would be If the clock signal is generated by an FPGA or microcontroller where the clock signal can be stopped after the data is clocked in In this case
21. t step Using well de coupled power and ground planes will help as well When crosstalk does occur within the crosspoint switch it self it is often due to signals coupling into the power supply pins Using appropriate supply bypassing will help to reduce this mode of coupling Another suggestion is to place as much grounded copper as possible between input and output signal traces Care must be taken though not to influence the signal trace impedances by placing shielding copper too closely One oth er caveat to consider is that as shielding materials come closer to the signal trace the trace needs to be smaller to keep the impedance from falling too low Using thin signal traces will result in unacceptable losses due to resistive losses This effect becomes even more pronounced at higher frequencies due to the skin effect The skin effect reduces the effective thickness of the trace as frequency increases Resistive loss es make crosstalk worse because as the desired signal is attenuated with higher frequencies crosstalk increases at higher frequencies DIGITAL CONTROL Block Diagram SWITCH MATRIX 16 INPUTS 8 OUTPUTS CONFIGURATION REGISTER CFG BCST RST DATA IN LOAD DATA OUT CS REGISTER CLK MODE 20214411 FIGURE 7 11 The LMH6582 has internal control registers that store the programming states of the crosspoint switch The logic is two staged to allow for maximum programming f
22. tion Section INTRODUCTION The LMH6582 is a high speed fully buffered non blocking analog crosspoint switch Having fully buffered inputs allows the LMH6582 to accept signals from low or high impedance sources without the worry of loading the signal source The fully buffered outputs will drive 75 or 50Q back terminated transmission lines with no external components other than the termination resistor The LMH6582 can have any input con nected to any or all output s Conversely a given output can have only one associated input INPUT AND OUTPUT EXPANSION The LMH6582 has high impedance inactive states for both inputs and outputs allowing maximum flexibility for Crosspoint expansion In addition the LMH6582 employs diagonal sym metry in pin assignments The diagonal symmetry makes it easy to use direct pin to pin vias when the parts are mounted on opposite sides of a board As an example two LMH6582 chips can be combined on one board to form either an 16 x 16 crosspoint or a 32 x 8 crosspoint To make a 16 x 16 cross point all 16 input pins would be tied together Input on side 1 to input 15 on side 2 and so on while the 8 output pins on each chip would be left separate To make the 32 x 8 cross point the 8 outputs would be tied together while all 32 inputs would remain independent In the 32 x 8 configuration it is important not to have 2 connected outputs active at the same time With the 16 x 16 configuration on the other han
23. ty and specifications Wave Soldering 10 sec 260 C ESD Tolerance Note 2 Human Body Model Operating Ratings Note 1 Machine Model 200V Temperature Range Note 4 40 C to 85 C Vs 6 2V Supply Voltage Range 3V to 5 5V Input Pins 20 mA aur Note 3 Thermal Resistance Input Voltage Range V to V 64 Pin Exposed Pad TQFP 27 C W 0 82 C W Maximum Junction Temperature 150 C 3 3V Electrical Characteristics note 5 Unless otherwise specified typical conditions are 25 C Ay 1 3 1000 Boldface limits apply at the temperature extremes Note 8 Note 7 Note 8 Frequency Domain Performance veea SEW Varco _ DP Differential Phase 1 1500 358 44442 Time Domain Response 1V Step 10 to 90 i ns t i 1V Step 10 to 90 5 Distortion And Noise Response HD2 2nd Harmonic Distortion 2 Vpp 10 MHz eo dBe HD3 Harmonic Distortion 2 Vpp 10 MHZ Ee dBc SOL owe Static DC Performance Offset Voltage Offset Voltage mV Drift lb Input Bias Current Non Inverting Note 9 UA 0 Power Supply Rejection Rat re J Tri State Supply Current RST pin gt 2 0V onc ek ac ee mA www national com 2 Symbol Parameter Conditions Min Typ Max Units Note 8 Note 7 Note 8
24. vice or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation All other brand or product names may be trademarks or registered trademarks of their respective holders Copyright 2007 National Semiconductor Corporation For the most current product information visit us at www national com National Semiconductor National Semiconductor Europe National Semiconductor Asia National Semiconductor Japan Americas Customer Customer Support Center Pacific Customer Support Center Customer Support Center Support Center Fax 49 0 180 530 85 86 Email ap support nsc com Fax 81 3 5639 7507 Email Email europe support nsc com Email jon feedback nsc com new feedback nsc com Deutsch Tel 49 0 69 9508 6208 Tel 81 3 5639 7560 Tel 1 800 272 9959 English Tel 49 0 870 24 0 2171 Fran ais Tel 33 0 1 41 91 8790 www national com
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National LMH6582 handbook