mosaic PUMA 2E1000-70/90/12 handbook(1)
Contents
1. PUMA2E1000 70 O In HMP Ltd West Chirton North Shields Tyne amp Wear NE29 8SE England Tel 44 191 293 0500 Fax 44 191 259 0997 J2K x 32 EEPROM MODULE PUMA 2E1000 70 90 12 Issue 4 4 January 2001 Description The PUMA 2E1000 is a 1Mbit High Speed EEPROM module user configurable as 32Kx32 64Kx16 or 128Kx8 Available with access times of 70 90 amp 120ns the device has an industry standard ceramic 66 pin P G A footprint The device features byte and page write facility 10 000 Write Erase cycle capability and data retention time of 10 years The device may be screened in accordance with MIL STD 883 1 048 576 bit CMOS High Speed EEPROM Features Very Fast access times of 70 90 120 ns User Configurable 5 8 16 32 bit wide Upgradeable footprint Operating Power 1760 mW max Standby Power 1320 mW max Package Suitable for Thermal Ladder Applications Single byte and Page Write operation DATA Polling and Toggle Bit for End of Write Detection Hardware and Software Data Protection May be screened in accordance with MIL STD 883 Block Diagram Pin Definition y CD 29 566 g ERN EM Eon o 00 655 566 5 7 000 099 ES ae 7 Pin Functions N A0 14 Address Inputs D0 31 Data Inputs Outputs 051 4 Chip Select2. 240 mA Output Low Voltage oi j 6 0mA 0 45 V Output High Voltage Von loy 4 0mA 2 4 V Capacitance V 5V109 5 T 25 C Parameter Symbol Test Condition lyp max Unit Input Capacitance Ch Vn 0V 26 34 pF I O Capacitance i V o 0V 8 bit mode 42 58 pF AC Test Conditions Output Test Load Input pulse levels OV to 3 0V VO Pin 6450 Input rise and fall times 5ns 0 o Input and Output timing reference levels 1 5V 1 76V Output load 1 TTL gate 100pF 100pF Vac 9 V 10926 o PUMA 2E1000 70 90 12 ISSUE 4 4 January 2001 AC READ CHARACTERISTICS Read Cycle 70 90 12 Parameter Symbol min max min max min max Unit Read Cycle Time tac 70 90 120 ns Address to Output Delay Line 70 90 120 ns CS1 4 to Output Delay tss 70 90 120 ns OE to Output Delay tse 0 40 0 45 0 50 ns CS1 4 or OE to Output Float 9 UE 0 40 0 45 0 50 ns Output Hold from OE CS1 4 or Li 0 0 0 ns Address whichever occured first Notes 1 CS1 4 may be delayed up to th after the address transition without impact on t 2 OE may be delayed up to t tog after the falling edge of CS1 4 without impact on t or by t address change without impact on t 3 is specified from OE or CS1 4 whichever occurs first C 5pF 4 This parameter is only sampled and is not 100 tested Acc toe after an Parameter Symbol min lyp max Unit Address OE
3. 3 Write protect state will be disabled at end of WORD TO write period even if no other data is loaded LAST ADDRESS 4 1 to 64 bytes words of data can be loaded Note Load Data above represents 8 bit mode For 16 or 32 bit mode place the load data in the 2 bytes or all 4 bytes on the data lines respectively Eg 8 bit load data 55 16 bit load data 5555 HEX All software write commands must obey the Page Write timing specifications The process of disabling the Data Protection mode is very similar to that described for enable except 6 bytes words must be loaded to specific locations in the EEPROM as shown Note here the use of the word load to describe enabling and disabling the protection modes in preference to write Although it may seem that if the Write command sequence is performed to enable protection then the three bytes words at those addresses will be overwritten with AA 55 A0 this is not the case 10 PUMA 2E1000 70 90 12 ISSUE 4 4 January 2001 Package Details Dimensions in mm inches 27 69 1 090 Sq Max 4 83 0 190 2 54 0 100 typ 4 32 0 170 i EE 8 13 0 320 max k i s i k 0 53 0 021 0 38 0 015 1 40 0 055 11 14 0 045 EE ooeocococcoQQoO 1 27 0 050 0 64 0 025 1 52 0 060 1 02 0 040 Military Screening Procedure Module Screening Flow for high reliability product is in accordance wit
4. OE Output Enable WE1 4 Write Enable NC No Connect C Vece Power 5V GND Ground J ISSUE 4 4 January 2001 PUMA2E1000 70 90 12 DC OPERATING CONDITIONS Absolute Maximum Ratings Temperature Under Bias 55 to 125 C Storage Temperature 65 to 150 C All input voltages including N C pins with Respect to GND V 0 6 to 6 25 V All output voltages with respect to GND V 0 6 to V 0 6 V Voltage on OE and A9 with Respect to GND V 0 6 to 13 5 V Notes 1 Stresses above those listed may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated below is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Recommended Operating Conditions Parameter Symbol min typ max DC Power Supply Voltage Vee 4 5 5 0 5 5 V Input Low Voltage Vie 0 1 0 8 V Input High Voltage Vu 2 0 Voc 1 V Operating Temp Range Ti 0 70 C T 40 85 C 2E10001 T s 55 125 C 2E1000M MB DC Electrical Characteristics V 5 0V 10 6 T 55 to 125 C Parameter Symbol TestCondition min typ max Unit Input Leakage Current Address OE l OV lt VS Vogt1V 40 CS1 4 WE1 4 As above 10 uA Output Leakage Current T CS1 42V V j GND to VCC 40 uA Operating Supply Current loc f 5MHz I 0mA 320 mA Standby Supply Current B 2 0 lt 0651 4 lt 1
5. Our products are subject to a constant process of development Data may be changed at any time without notice Products are not authorised for use as critical components in life support devices without the express written approval of a company director 12
6. Read Cycle Timing Waveform 234 Address b Address Valid Ia tao CS1 4 i lcs log 9E N a n tacc ton 7 7 DATA OUT HIGH Z pns AC Write Waveform WE1 4 Controlled k luc DATA IN E l Data Valid tos i tou PUMA2E1000 70 90 12 ISSUE 4 4 January 2001 AC Write Waveform CS1 4 Controlled Address X X ths ig tan tes E Iy ten WE1 4 fe ty High Z DATA IN 2 1 Data Valid tos ton Page Mode Write Waveform 2 77 Byte 62 E Note 1 A6 through A14 must specify the page address during each high to low transition of WE1 4 or CS1 4 2 OE must be high only when WE1 4 and CS1 4 are both low ISSUE 4 4 January 2001 PUMA2E1000 70 90 12 DATA Polling Waveform WE1 4 m toEH SDN S SN D7 D15 no D23 D31 A0 A14 An An x An An Toggle Bit Waveform 23 tou D6 D14 EE HIGH Z HIGHZ D22 D30 Software Protected Write Waveform 2 OE ATA MUTA gr 7 4 ven V Y AS j A0 A5 3 X BYTE ADDRESS 05555 O2AAA 05555 fe A6 A14 X X PAGE ADDRESS 7 f f DS j DH p Data X AA 55 A0 X Byte 0 Byte 62 E Notes 1 A6 through A14 must specify the page address during each high t
7. 4 January 2001 PUMA2E1000 70 90 12 Software Data Protection Software controlled data protection once enabled by the user necessitates the use of a software algorithm before any Write can be performed To enable this feature a special sequence of 3 Writes to 3 specific addresses must be performed and must be reused for each subsequent Write cycle Once set the data protection remains operational until it is disabled by using a second algorithm power transitions will not reset this feature Note that the PUMA 2E1000 is supplied with the Software data Protection feature disabled The algorithms to enable and disable the protection are shown below SDP Enable SDP Disable LOAD DATA AA LOAD DATA AA TO TO ADDRESS 5555 ADDRESS 5555 LOAD DATA 55 LOAD DATA 55 TO TO ADDRESS 2AAA ADDRESS 2AAA LOAD DATA 40 LOAD DATA 80 TO ADDRESS 5555 ADDRESS 5555 WRITES ENABLED 2 LOAD DATA XX LOAD DATA AA TO ANY ADDRESS 4 ADDRESS 5555 LOAD LAST BYTE LOAD DATA 55 WORD TO TO LAST ADDRESS ENTER DATA ADDRESS2AAA PROTECT STATE LOAD DATA 20 TO ADDRESS 5555 Once initiated the enable sequence of write operations should not be interrupted EXIT DATA PROTECT STATE 3 LOAD DATA XX TO ANY ADDRESS 4 Notes 1 Data D7 DO hex Address A14 AO hex 2 Write Protect Mode will be activated at end of Write even if no other data is loaded LOAD LAST BYTE
8. Set up Time fiss lots 0 ns Address Hold Time t 50 ns Chip Select Set up Time las 0 g s ns Chip Select Hold Time T 0 ns Write Pulse Width WE1 4 or CS1 4 twp 100 ns Data Set up Time Tog 50 ns Data OE Hold Time tsu togn 0 ns Time to Data Valid t NR ns Note 1 NR No Restriction Page Mode Write Cycle Parameter Symbol min typ max Unit Write Cycle Time Luc 5 10 ms Address Set up Time Ls 0 ns Address Hold Time Los 50 ns Data Set up Time tis 50 s ns Data Hold Time lu 0 gt E ns Write Pulse Width Lip 100 2 B ns Byte Word Load Cycle Time Lis 150 us Write Pulse Width High m 50 ns See notes on page 6 Mode Write Waveform DATA Polling Characteristics Parameter Symbol min typ max Unit Data Hold Time LT 0 a ns OE Hold Time OEH 0 s ns OE to Output Delay Ice ns Write Recovery Time Lus 0 ns Note 1 See AC Read Characteristics ISSUE 4 4 January 2001 PUMA2E1000 70 90 12 Toggle Bit Characteristics 25 Parameter Symbol min lyp max Unit Data Hold Time tou 10 x ns OE Hold Time toen 10 a ns OE to Output Delay ie ns OE High Pulse D eeu 150 ns Write Recovery Time Lin 0 ns Note 1 See AC Read Characteristics 2 Toggling either OE or CS1 4 or both OE and CS1 4 will operate toggle bit 3 Beginning and ending state of D6 will vary 4 Any address location may be used but the address should not vary aS
9. ection circuitis enabled after the first write operation utilizing the software algorithm This circuit is nonvolatile and will remain set for the life of the device unless the reset command is issued Once the software protection is enabled the PUMA 2E1000 is also protected against inadvertent and accidental writes in that the software algorithm must be issued prior to writing additional data to the device Operating Modes The table below shows the logic inputs required to control the operation of the PUMA 2E1000 MODE cS OE VEHHOUTPUTS Head Data Out Write Data in Standby Write inhibit High Z Write Inhibit Output Disable 1 Chip Erase o 1 0 High Z O V 1 V X V orv IH IH IL Notes 1 OE must be 12 0V 0 5V Device Indentification An extra 64 bytes of EEPROM memory are avaliable to the user for device identification accessed by placing 12V 0 5V on A9 and using locations 7FCO to 7FFF These locations can be used during the initial programming of each EEPROM to record data such as issue number and release date and subsequent reprogramming can change these locations to record the alterations performed All of the memory locations on the PUMA 2E1000 can be erased in 10 ms by placing 12 0V 0 5V onto OE and controlling WE1 4 and CS1 4 to follow the Chip Erase timing characteristics This function will operate even if the module is in Software Data Protection Mode as explained later ISSUE 4
10. h MIL STD 883 method 5004 Level B and is detailed below MB MODULE SCREENING FLOW SCHEEN TEST METHOD LEVEL Visual and Mechanical External visual Temperature cycle Burn In Pre Burn in Electrical Burn In Final Electrical Tests Static dc Functional Switching ac 2017 Condition B or manufacturers equivalent 1010 Condition C 10 Cycles 65 C to 150 C Per Applicable device Specifications at T 25 C optional Method 1015 Condition D T 125 C Per applicable Device Specification T 25 C and power supply extremes temperature and power supply extremes a b a T 25 C and power supply extremes b temperature and power supply extremes a b T 2425 C and power supply extremes temperature and power supply extremes Calculated at Post Burn in at T 25 C Per applicable Device Specification 2009 Per HMP or customer specification 11 ISSUE 4 4 January 2001 PUMA2E1000 70 90 12 Ordering Information PUMA 2E1000MB 70 Speed Temp range screening Memory Type 70 70ns 90 90 ns 12 120ns Blank Commercial Temp Industrial Temp M Military Temp MB Screened in accordance with MIL STD 883 E1000 EEPROM Configurable as 32Kx32 64Kx16 or 128Kx8 Although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantability or fitness for a particular purpose
11. o low transition of WE1 4 or CS1 4 2 OE must be high only when WE1 4 and CS1 4 are both low PUMA2E1000 70 90 12 ISSUE 4 4 January 2001 Chip Erase Waveform 5us min t 10ms min V lt 12V 0 5V ISSUE 4 4 January 2001 PUMA2E1000 70 90 12 Device Operation Where references are made to byte word operations the user will control the memory configuration of 8 16 or 32 bits wide using CS1 4 Read The PUMA 2E1000 read operations are initiated by both Output Enable and Chip Select s LOW while Write Enable s is HIGH The read operation is terminated by either Chip Select s or Output Enable returning HIGH This dual line control architecture eliminates bus contention in a system environment The data bus will be in a high impendence state when either Output Enable or Chip Select is HIGH Write Write operations are initiated when both Chip Select s and Write Enable s are LOW and Output Enable is HIGH The PUMA 2E1000 supports both a Chip Select s and Write Enable s controlled write cycle Thatis the address is latched by the falling edge of either Chip Select s or Write Enable s whichever occurs last Similarly the data is latched internally by the rising edge of either Chip Select s or Write Enable s whichever occurs first A byte word write operation once initiated will automatically continue to completion within 10 ms max Page Mode Write The page write featu
12. re of the PUMA 2E1000 allows the entire memory to be written in typically 5 12 seconds Page Write allows 1 to 64 bytes words of data to be written into the device during a single programming cycle The host can fetch data from another location within the system during a page write operation change the source address butthe page address A6 through A14 for each subsequent valid write cycle to the part during this operation must be the same as the initial page address The page write mode can be initiated during any write operation Following the initial byte word write cycle the hostcan write up to 63 bytes words in the same manner as the first byte word written Each successive byte word load cycle started by the Write Enable s HIGH to LOW transition must begin within 150 us of the falling edge of the preceding Write Enable s If a subsequent Write Enable s HIGH to LOW transition is not detected within 150 us the internal automatic programming cycle will commence The AO to A5 inputs are used to specify which bytes words within the page are to be written The bytes words may be loaded in any order and altered within the same load period Only bytes words which are specified for writing will be written unnecessary cycling of other bytes words within the page does not occur DATA Polling The PUMA 2E1000 features DATA Polling to indicate if the write cycle is completed During the internal programming cycle any attempt to read the last by
13. te word written will produce the complement of that data on D7 Once the programming is complete D7 will refect the true data Note If the the PUMA 2E1000 is in a protected state and an illegal write operation is attempted DATA Polling will not operate DATA Polling may begin at any time during the write cycle TOGGLE bit In addition to DATA polling another method is provided to determine the end of a Write Cycle During a write operation successive attempts to read data will result in D6 toggling between 1 and 0 Once a write is complete this toggling will stop and valid data will be read Reading the toggle bit may begin at any time during the write cycle PUMA 2E1000 70 90 12 ISSUE 4 4 January 2001 Hardware Data Protection The PUMA 2E1000 provides hardware features to protect non volatile data from inadvertent writes Vg Sense If V is below 3 8V typical the write function is inhibited Vg Power on Delay Once V has reached 3 8V the device will automatically time out 5ms typical before allowing a write Write Inhibit Holding any one of OE Low CS High WE High inhibits write cycles Noise Filter Pulses of less than 15ns typical on the WE or 65 inputs will not initiate a write cycle Software Data Protection The PUMA 2E1000 can be automatically protected during power up and power down without the need for external circuits by employing the software data protect feature The internal software data prot
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mosaic PUMA 2E1000 70/90/12 handbook(1)