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mosaic PUMA 2E1000-70/90/12/X405 handbook

1. 0 38 0 015 1000 oo 0o00 eo ooo oo ooo oo 1 40 0 055 path a 2 2 54 0 100 typ 1 14 0 045 00O oo 1 27 0 050 0 64 0 025 1 52 0 060 1 02 0 040 8 13 0 320 max Military Screening Procedure Module Screening Flow for high reliability product is in accordance with MIL STD 883 method 5004 Level B and is detailed below B MODULE SCREENING FLOW TEST METHOD Visual and Mechanical External visual 2017 Condition B or manufacturers equivalent Temperature cycle 1010 Condition C 10 Cycles 65 C to 150 C Burn in Pre Burn in Electrical Per Applicable device Specifications at T 25 C optional Burn in Method 1015 Condition D T 125 C Final Electrical Tests Static dc Per applicable Device Specification T 25 C and power supply extremes temperature and power supply extremes Functional T 25 C and power supply extremes a b a b temperature and power supply extremes a b Switching ac T 25 C and power supply extremes temperature and power supply extremes Percent Defective Allowable PDA Calculated at Post Burn in at T 25 C Quality Conformance Per applicable Device Specification External Visual 2009 Per HMP or customer specification dl a Mosaic Semiconductor Inc 7420 Carroll Rd Suite 300 San Diega CA 92121 Tel 619 271 4565 Fax 619 271 6058 E 6353379 0002729 T14 EE
2. Powered by ICminer com Electronic Library Service CopyRight 2003 ISSUE 4 0 JUNE 1997 Ordering Information PUMA 2 1000 70 80 12 X405 PUMA 2E1000LMB 70 X405 l JIL J EJ Speed Temp range screening Power Consumption Memory Type NOTES 1 X405 indicates customer specific part X405 is designed for Fast Page Write applications twe 3ms Max If not specified when ordered only a t of 10ms Max can be guaranteed Mosaic Semiconductor Inc 7420 Carroll Rd Suite 300 San Diego CA 92121 EE 6353379 0002730 736 mm 12 Powered by ICminer com 70 70ns 90 90 ns 12 120 ns Blank Commercial Temp Industrial Temp M Military Temp MB Screened in accordance with MIL STD 883 Blank Standard Part L Low Power Part 90 12 Only E1000 EEPROM Configurable as 32Kx32 64Kx16 or 128Kx8 Tel 619 271 4565 Fax 619 271 6058 Electronic Library Service CopyRight 2003
3. 2 Byte a Byte 62 Note 1 A6 through A14 must specify the page address during each high to low transition of WE1 4 or CS1 4 2 OE must be high only when WE1 4 and CS1 4 are both low Mosaic Semiconductor Inc 7420 Carroll Rd Suite 300 San Diego CA 92121 Tel 619 271 4565 Fax 619 271 6058 MB 6353379 0002723 STL EE Powered by ICminer com Electronic Library Service CopyRight 2003 ISSUE 4 0 JUNE 1997 PUMA 2E1000 70 90 12 x405 DATA Polling Waveform Software Protected Write Waveform 2 OE ae Aw Oe Ae aw Ae ee Notes 1 A6 through A14 must specify the page address during each high to low transition of WE1 4 or CS1 4 2 OE must be high only when WE1 4 and CS1 4 are both low e ee ee BO Mosaic Semiconductor Inc 7420 Carroll Rd Suite 300 San Diego CA 92121 Tel 619 271 4565 Fax 619 271 6058 MB 6353379 0002724 432 W 6 Powered by ICminer com Electronic Library Service CopyRight 2003 PUMA 2E1000 70 90 12 X405 ISSUE 4 0 JUNE 1997 Chip Erase Waveform 4 5ps min ty 10ms min V 12V 0 5V Se a ee Mosaic Semiconductor Inc 7420 Carroll Rd Suite 300 San Diego CA 92121 Tel 619 271 4565 Fax 619 271 6058 WS 6353379 0002725 379 EE Powered by ICminer com Electronic Library Service CopyRight 2003 ISSUE 4 0 JUNE 1997 PUMA 2E1000 70 90 12 X405 Device Operation eee Where references are made to byte word oper
4. to Output Delay te O 40 O 45 Oo 50 ns CS1 4 or OE to Output Float amp tor 0 40 Q 45 0 50 ns Output Hold from OE CS1 4 or ty 0 3 0 0 ns Address whichever occured first Notes 1 CS1 4 may be delayed up to ticc t s after the address transition without impact on theo 2 OE may be delayed up to tss tos after the falling edge of CS1 4 without impact on t or by taco gt toe after an address change without impact on tioc 3 t is specified from OE or CS1 4 whichever occurs first C 5pF 4 This parameter is only sampled and is not 100 tested Write Cycle Parameter Symbol min typ max Unit Address OE Set up Time Tet bce 0 ns Address Hold Time tay 50 gt 5 ns Chip Select Set up Time tes 0 ns Chip Select Hold Time toy 0 a ns Write Pulse Width WE1 4 or CS1 4 twp 100 ns Data Set up Time tie 50 ns Data OE Hold Time toa toti 0 ns Time to Data Valid tay NR ns Note 1 NR No Restriction Page Mode Write Cycle T o Parameter Symbol min typ max Unit Write Cycle Time two 2 3 ms Address Set up Time tis 0 ns Address Hold Time tig 50 ns Data Set up Time tos 50 3 ns Data Hold Time ts 0 ns Write Pulse Width tio 100 ns Byte Word Load Cycle Time taic 150 Us Write Pulse Width High lige 50 a ns See notes on page 6 Mode Write Waveform DATA Polling Characteristics Parameter Symbol min typ max Unit Data Hold Time tis 0 ns OE Hold
5. 27 141 EE Powered by ICminer com Electronic Library Service CopyRight 2003 ISSUE 4 0 JUNE 1997 PUMA 2E1000 70 90 12 X405 Software Data Protection Software controlled data protection once enabled by the user necessitates the use of a software algorithm before any Write can be performed To enable this feature a special sequence of 3 Writes to 3 specific addresses must be performed and must be reused for each subsequent Write cycle Once set the data protection remains operational until it is disabled by using a second algorithm power transitions will not reset this feature Note that the PUMA 2E1000 is supplied with the Software data Protection feature disabled The algorithms to enable and disable the protection are shown below SDP Enable SDP Disable LOAD DATA AA TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 LOAD DATA 55 TO ADDRESS 2AAA ADDRESS 2AAA LOAD DATA A0 LOAD DATA 80 T ADDRESS 5555 ADDRESS 5555 WRITES ENABLED 2 LOAD DATA XX LOAD DATA AA TO TO ANY ADDRESS 4 ADDRESS 5555 LOAD LAST BYTE LOAD DATA 55 WORD TO TO LAST ADDRESS ENTER DATA ADDRESS2AAA PROTECT STATE LOAD DATA 20 TO Once initiated the enable sequence of ADDRESS 5555 EXIT DATA write operations should not be interrupted PROTECT STATE 3 LOAD DATA XX TO Notes 1 Data D7 DO hex Address A14 AO hex ANY ADDRESS 4 2 Write Protect Mode will be activated at end of Write even if no other data is l
6. 3 G v 9 2 K 9 8 3 3 gt kad 2x 3 Oz Q z O z O p E 0 0 10 O O 0 Gi 03530 0 0 o br z Zz z 2 03070 z0 10 z qq oS a Q Q nm 9 a Q t3 0 Data Inputs Outputs Output Enable No Connect Ground E 6353379 0002719 075 EE ICminer com Electronic Library Service CopyRight 2003 ISSUE 4 0 JUNE 1997 PUMA 2E1000 70 90 12 X405 DC OPERATING CONDITIONS Absolute Maximum Rating Temperature Under Bias Taas 55 to 125 C Storage Temperature Tsg 65 to 150 C All input voltages including N C pins with Respect to GND Vi 0 6 to 6 25 V All output voltages with respect to GND Vour 0 6 to Voc 0 6 V Voltage on OE and A9 with Respect to GND Voea 0 6 to 13 5 V Notes 1 Stresses above those listed may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated below is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Recommended Operating Conditions Parameter Symbol min typ max DC Power Supply Voltage Voc 4 5 5 0 5 5 V Input Low Voltage Vi 0 1 5 0 8 V input High Voltage Vin 2 0 Voott V Operating Temp Range Ty 0 70 C Ty 40 85 C 2E10001 Tai 55 125 C 2E1000M MB DC Electrica
7. Powered by 0 O0 PUMA2E1000 10 0 O larn MOSAIC Description The PUMA 2E1000 X405 is a 1Mbit CMOS High Speed EEPROM organised as 32K x 32 This is available in a 66 pin PGA package which is suitable for thermal ladder applications Access times are 70ns 90ns or 120ns It has a user configurable output width There is facility for both Byte and Page write operation with the X405 having a Page Write Cycle time of 3ms Max Included is both hardware and software data protection and a data retention time of 10 years It may be screened in accordance with MIL STD 883 Block Diagram 32K x 8 EEPROM 32K x 8 EEPROM 32K x 8 EEPROM oi I cs2 cs3 cs4 DOo 7 D8 15 D16 23 D24 31 Pin Functions AQ 14 CSs1 4 WE1 4 Address Inputs Chip Select Write Enable ce Power 5V 32K x 32 EEPROM MODULE PUMA 2E1000 70 90 12 X405 Issue 4 0 June 1997 1 048 576 bit CMOS High Speed EEPROM Features Very Fast access times of 70 90 120 ns User Configurableas 8 16 32 bit wide Operating Power 1760 mW max Standby Power 1320 mW max Package Suitable for Thermal Ladder Applications Single byte and Page Write operation DATA Polling and Toggle Bit for End of Write Detection Hardware and Software Data Protection Endurance 10 Cycles and Data retention 10 years May be screened in accordance with MIL STD 883 Pin Definition lt 3 z
8. Time tage 0 ns OE to Output Delay te ns Write Recovery Time twa 0 gt z ns Note 1 See AC Read Characteristics i U a Mosaic Semiconductor Inc 7420 Carroll Rd Suite 300 San Diego CA 92121 Tel 619 271 4565 Fax 619 271 6058 EE 6353379 0002721 723 EE Powered by ICminer com Electronic Library Service CopyRight 2003 ISSUE 4 0 JUNE 1997 PUMA 2E1000 70 90 12 X405 Toggle Bit Characteristics 0234 Parameter Symbol min typ max Unit Data Hold Time tou 10 ns OE Hold Time toen 10 ns OE to Output Delay tor ns OE High Pulse beg 150 ns Write Recovery Time twi 0 ns Note 1 See AC Read Characteristics es 2 Toggling either OE or CS1 4 or both OE and CS1 4 will operate toggle bit 3 Beginning and ending state of D6 will vary 4 Any address location may be used but the address should not vary Read Cycle Timing Waveform 2 34 Address Address Valid CS1 4 OE mm 4 YZ DATA OUT HIGH Z Uf Output GY WE1 4 DATAIN eee IM alL Mosaic Semiconductor Ine 7420 Carroll Rd Suite 300 San Diego CA 92121 Tel 619 271 4565 Fax 619 271 6058 EE 6353379 0002722 bbT EE 4 Powered by ICminer com Electronic Library Service CopyRight 2003 PUMA 2E1000 70 90 12 X405 ISSUE 4 0 JUNE 1997 Address WE1 4 Page Mode Write Waveform 7 Data XK X X Byte 0 Byte 1 Byte
9. ach subsequent valid write cycle to the part during this operation must be the same as the initial page address The page write mode can be initiated during any write operation Following the initial byte word write cycle the host can write up to 63 bytes words in the same manner as the first byte word written Each successive byte word load cycle started by the Write Enable s HIGH to LOW transition must begin within 150 us of the falling edge of the preceding Write Enable s If a subsequent Write Enable s HIGH to LOW transition is not detected within 150 us the internal automatic programming cycle will commence The AO to A5 inputs are used to specify which bytes words within the page are to be written The bytes words may be loaded in any order and altered within the same load period Only bytes words which are specified for writing will be written unnecessary cycling of other bytes words within the page does not occur DATA Polling The PUMA 2E1000 features DATA Polling to indicate if the write cycle is completed During the internal programming cycle any attempt to read the last byte word written will produce the complement of that data on D7 Once the programming is complete D7 will refect the true data Note If the the PUMA 2E1000 is ina protected State and an illegal write operation is attempted DATA Polling will not operate DATA Polling may begin at any time during the write cycle In addition to DATA polling anothe
10. ations the user will control the memory configuration of 8 16 or 32 bits wide using CS1 4 Read The PUMA 2E1000 read operations are initiated by both Output Enable and Chip Select s LOW while Write Enable s is HIGH The read operation is terminated by either Chip Select s or Output Enable returning HIGH This dual line control architecture eliminates bus contention in a system environment The data bus willbe ina high impendence state when either Output Enable or Chip Select is HIGH Write operations are initiated when both Chip Select s and Write Enable s are LOW and Output Enable is HIGH The PUMA 2E1000 supports both a Chip Select s and Write Enable s controlled write cycle Thatis the address is latched by the falling edge of either Chip Select s or Write Enable s whichever occurs last Similarly the data is latched internally by the rising edge of either Chip Select s or Write Enable s whichever occurs first A byte word write operation once initiated will automatically continue to completion within 10 ms max Page Mode Write A See Pi The page write feature of the PUMA 2E1000 allows the entire memory to be written in typically 2 05 seconds Page Write allows 1 to 64 bytes words of data to be written into the device during a single programming cycle The host can fetch data from another location within the system during a page write operation change the source address but the page address A6 through A14 for e
11. l Characteristics V Parameter Symbol Test Condition min typ max Unit Input Leakage Current Address OE OVE VS Voot V 40 pA CS1 4 WE1 4 I As above 10 HA Output Leakage Current lio CS1 4 V V o GND to VCC i 40 LA Operating Supply Current leca f 5MHz OmA 320 mA Standby Supply Current lssi 2 0VSCS1 4 lt V_o 1V 240 mA L Version CMOS 90 12 3 0VSCS1 45V 4 1V z 1 2 m Output Low Voltage Vo lo 6 0MA 0 45 V Output High Voltage Von lon 4 0MA 2 4 gt V Capacitance V 5V 10 T 25 C Parameter Symbol Test Condition typ max Unit Input Capacitance Cw Vin OV 26 34 pF VO Capacitance Cis Vo 0V 8 bit mode 42 58 pF ac Test Conditions Output Test Load Input pulse levels OV to 3 0V f A 1 0 Pin 6450 Input rise and fall times 5ns o o Input and Output timing reference levels 1 5V ails 1 76V Output load 1 TTL gate 100pF gt 100pF Voc 5V 10 ME Mosaic Semiconductor Inc 7420 Carroll Rd Suite 300 San Diego CA 92121 Tel 619 271 4565 Fax 619 271 6058 EE 6353379 0002720 897 EE 2 Powered by ICminer com Electronic Library Service CopyRight 2003 PUMA 2E1000 70 90 12 X405 ISSUE 4 0 JUNE 1997 AC READ CHARACTERISTICS Read Cycle ae 70 90 12 Parameter Symbol min max min max min max Unit Read Cycle Time ee 70 90 120 ns Address to Output Delay biog 70 90 120 ns CS1 4 to Output Delay tes 70 90 120 ns OE
12. lgorithm This circuit is nonvolatile and will remain set for the life of the device unless the reset command is issued Once the software protection is enabled the PUMA 2E1000 is also protected against inadvertent and accidental writes in that the software algorithm must be issued prior to writing additional data to the device Operating Modes The table below shows the logic inputs required to control the operation of the PUMA 2E1000 i Standby Write inhibit 1 x x High z_ Output Disable Chip Erase o O V 1 V o High z no X Va rV Notes 1 OE must be 12 0V 0 5V Device Indentification p An extra 64 bytes of EEPROM memory are avaliable to the user for device identification accessed by placing 12V 0 5V on A9 and using locations 7FCO to 7FFF These locations can be used during the initial programming of each EEPROM to record data such as issue number and release date and subsequent reprogramming can change these locations to record the alterations performed All of the memory locations on the PUMA 2E1000 can be erased in 10 ms by placing 12 0V 0 5V onto OE and controlling WE1 4 and CS1 4 to follow the Chip Erase timing characteristics This function will operate even if the module is in Software Data Protection Mode as explained later i E S E Mosaic Semiconductor Inc 7420 Carroll Rd Suite 300 San Diego CA 92121 Tel 619 271 4565 Fax 619 271 6058 EE 6353379 00027
13. oaded LOAD LAST BYTE 3 Write protect state will be disabled at end of WORD TO write period even if no other data is loaded LAST ADDRESS 4 1 to 64 bytes words of data can be loaded Note Load Data above represents 8 bit mode For 16 or 32 bit mode place the load data in the 2 bytes or all 4 bytes on the data lines respectively Eq 8 bit load data 55 16 bit load data 5555 ex All software write commands must obey the Page Write timing specifications The process of disabling the Data Protection mode is very similar to that described for enable except 6 bytes words must be loaded to specific locations in the EEPROM as shown Note here the use of the word load to describe enabling and disabling the protection modes in preference to write Although it may seem that if the Write command sequence is performed to enable protection then the three bytes words at those addresses will be overwritten with AA 55 A0 this is not the case St Sa pe Mosaic Semiconductor Inc 7420 Carroll Rd Suite 300 San Diego CA 92121 Tel 619 271 4565 Fax 619 271 6058 EE 6353379 0002728 088 me 10 Powered by ICminer com Electronic Library Service CopyRight 2003 PUMA 2E 1000 70 90 12 xX405 ISSUE 4 0 JUNE 1997 Package Details Dimensions in mm inches 2 54 0 100 typ 15 24 0 60 27 69 1 090 Sq Max 4 83 0 190 4 32 0 170 l I A of ooo 60 ooo oo 0 53 0 021 00 E
14. r method is provided to determine the end of a Write Cycle During a write operation successive attempts to read data will result in D6 toggling between 1 and 0 Once a write is complete this toggling will stop and valid data will be read Reading the toggle bit may begin at any time during the write cycle aLL ye an Gn lt lt Mosaic Semiconductor Inc 7420 Carroll Rd Suite 300 San Diego CA 92121 Tel 619 271 4565 Fax 619 271 6058 E 6 3533979 OCOe ck 205 EE 8 Powered by ICminer com Electronic Library Service CopyRight 2003 PUMA 2E 1000 70 90 12 X405 ISSUE 4 0 JUNE 1997 Hardware Data Protection The PUMA 2E1000 provides hardware features to protect non volatile data from inadvertent writes Voc Sense If V is below 3 8V typical the write function is inhibited Voc Power on Delay Once V has reached 3 8V the device will automatically time out 5ms typical before allowing a write e Write Inhibit Holding any one of OE Low CS High WE High inhibits write cycles Noise Filter Pulses of less than 15ns typical on the WE or CS inputs will not initiate a write cycle Software Data Protection The PUMA 2E 1000 can be automatically protected during power up and power down without the need for external circuits by employing the software data protect feature The internal software data protection circuit is enabled after the first write operation utilizing the software a

mosaic PUMA 2E1000-70/90/12/X405 handbook

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