PHILIPS SAA3323 Drive processor for DCC systems handbook
Contents
1. tscL Vin SBMCLK V tscH e IE td5 Y OUT3 ll VoL MGB407 Fig 40 Timing for AC characteristics May 1994 49 Philips Semiconductors Drive processor for DCC systems ADC CHARA CTERISTICS Preliminary specification SAA3323 Vop 2 7 to 3 6 V Tamb 40 to 85 C C 10 pF on TCLOCK output see Fig 41 unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN TYP negative reference voltage 0 CN Vret p 10 Vret n input impedance input capacitance RDMUX Vref p to Vret n 2 0 700 AC RDMUX ADC resolution E A o et AV ret Vref n to Vss THD N signal to total harmonic distortion plus noise ratio 20 dB FS 100 to 500 kHz 24 Ci l input current S S Timing Toy cycle time of CLK24 ta TCLOCK delay time from rising edge of CLK24 tsu RDMUX set up time to falling Zsource lt 150 Q 60 ns edge of CLK24 th RDMUX hold time from falling 40 ns edge of CLK24 CLK24 TCLOCK CLK ADC May 1994 th tsu e Fig 41 ADC timing 50 romux AAA sate AG TESTBUS DATA SAMPLE 1 3 N DATA SAMPLE 1 2 LH IL MGB408 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 DAC CHARACTERISTICS Vop 2 7 to 3 6 V Tamb 40 to 85 C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT DIGEYE2. t ii AUX 1 AENV 1 internal H LAB 7 MGB401 ta3 pal toa o Fig 27 AENV to LAB delays May 1994 32 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 daa ell Ie 7 lT internal MGB402 a td5 lt tae Fig 28 AENV to VIR delays Table 25 Digital equalizer STATUS1 a ae EA E EE A ESA Meaning AENV 2 LABS Notes 1 VIR gives the state of the VIRGIN signal 2 AENV represents the state of the AENV signal 3 LAB gives the state of the LAB signal AUX envelope count AECNT register This 16 bit register is used for loading the AUX envelope counter and for reading the state of that counter it is therefore readable and writable as 2 bytes Least Significant Byte first Table 26 AECNT register AECNT LEAST SIGNIFICANT BYTE MOST SIGNIFICANT BYTE Search speed SSPD register 51 2 Search speed 258 512 SV x normal speed Table 27 Search speed register Oo B 7 6 SVF s Meaning y4 2 5 a sa 2 ae o sv3 sv22 svi svo sR1 sro Notes 1 SVF speed validation flag if HIGH then the search speed measurement is invalid 2 SV4 to SVO search speed value 3 SR1 and SRO search speed range May 1994 33 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 ANAEYE register Table 28 ANAEYE register analog eye pat
3. data SRAM 1 O 4 mA data SRAM 1 O 4 mA PERU AN pened pea Be E Rae Rae Rae hae data SRAM 1 O 4 mA data SRAM data DRAM 1 0 4 mA D D D D D D D data SRAM data DRAM UO 4 mA data SRAM data DRAM I O 4 mA Vpp7 digital supply voltage for RAM S Vss7 digital ground for RAM S data SRAM data DRAM I O 4 mA D A A 4 EN 2 RAS 2 2 2 7 2 6 2 5 2 4 2 3 2 2 3 1 3 3 3 0 3 0 3 1 3 0 1 1 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 0 2 1 2 2 3 3 3 4 3 5 3 6 3 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 address SRAM address DRAM address SRAM address DRAM 37 35 address SRAM address DRAM May 1994 38 36 address SRAM address DRAM Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 SYMBOL PIN QFP80 DESCRIPTION TYPE TQFP80 39 37 address SRAM address DRAM 38 digital ground A12 PINO5 A14 PINO1 A16 PINO3 4 address SRAM Port expander output 5 4 address SRAM Port expander output 1 A15 PINO4 WEN A13 PINO2 3 4 45 address SRAM Port expander output 3 47 write enable for RAM 48 address SRAM Port expander output 2 address SRAM address DRAM digital supply voltage digital ground O 1 mA SPEED 56 Pulse Width Modulation PWM capstan control output for deck PINO2 57 Port expander output 2 52 address SRAM CA
4. 2 1 block of 128 bytes being transferred in time segment 1 In mode DRAR SYSINFO must be transferred as 4 blocks of 32 bytes one block in each segment Figures 31 to 34 show the offsets between the SYSINFO and AUX and the time segment counter for the various modes of operation of the SAA3323 MODE 1 AUX block in each time segment DESCRIPTION SYSBLK SNUM 3 MOD4 or read all 4 SYSINFO blocks when SNUM logic 0 if AUX and main were recorded simultaneously then AUXBLK SNUM 1 MOD4 else read and interpret SYSBLK SNUM AUXBLK SNUM 1 MOD4 SYSBLK SNUM 3 MOD4 or read all 4 SYSINFO blocks when SNUM logic 0 May 1994 ion t SAA3323 Iminary specitica Prel BIZZLE OILLO K kx RA eer KKK KKK RRRS RCRA ESE RE RK LY QI IS IIS ROLL L L G xh 99 99 KO E d e E RIIIE 2 JE 4 Jo 2ja o 1j2 3 o 1 2 3 o 1 2 oro E S SNUM AUX BLK Drive processor for DCC systems Philips Semiconductors SYS BLK SYS BLK Itaneously recorded MLB414 Imu d AUX separately recorded d AUX s 10 an 10 an aud U o 1 2 3 0 1 3 aud 3 U Kal SYS BLK EJ 112 sls 112 SYS BLK 39 DEPENDS ON P
5. INTEGRATED CIRCUITS DATA SHEET COMPACT CASSETTE SAA3323 Drive processor for DCC systems Preliminary specification May 1994 File under Integrated Circuits IC01 Philips Semiconductors PHILIPS Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 FEATURES Operating supply voltage 2 7 to 3 6 V Low power dissipation 84 mW typ Single chip digital equalizer tape formatting and error correction 8 bit flash analog to digital converter ADC for low symbol error rate Two switchable Infinite Impulse Response IIR filter sections 10 tap Finite Impulse Response FIR filter per main data channel with 8 bit coefficients identical for all main channels 10 tap FIR filter for the AUX channel Analog and digital eye outputs Interrupt line triggered by internal auxiliary envelope processing e g label counter and others Robust programmable digital PLL clock extraction unit Low power SLEEP mode Slew rate limited Electromagnetic Compatibility EMC friendly output Digital Compact Cassette DCC optimized error correction Programmable symbol synchronization strategy for tape input data Microcontroller control of capstan servo possible during DIGITAL EC COMPACT CASSETTE Frequency and phase regulation of capstan servo during playback Choice of Dynamic Random Access Memory DRAM and Static Random Access Memory SRAM types for system Random
6. MODE DRAR NEW MODE DRAR a 222ms gt T MEA707 2 AUXILIARY MAIN TAPE OUT Fig 35 Mode change to DRAR Preliminary specification SAA3323 SNUM 1 2 JODE a o 1 2 MODE DPAP DPAR NEW MODE DPAR 85 3 ms ane AUXILIARY TAPE OUT A MEA708 2 Fig 36 Mode change to DPAR SNUM 1 213 0 00 11 2 3 011 MODE DRAR DPAP NEW MODE DPAP URDA 213 3 ms MEA709 1 Fig 37 Mode change from DRAR SNUM 1 2 s o 1 2 3Jo 1 2 MODE DPAR DPAP NEW MODE DPAP AUXILIARY l TAPE OUT 128 ms lt gt AUXILIARY TO MICROCONTROLLER 170 66 ms la S MEA710 2 Fig 38 Mode change from DPAR May 1994 43 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 LIMITING VALUES In accordance with the Absolute Maximum Rating System IEC 134 SYMBOL PARAMETER CONDITIONS MIN MAX UNIT supply voltage input voltage note 1 input current output voltage output current supply current Tstg storage temperature Vest electrostatic handling note 2 2000 2000 V Ves2 electrostatic handling note 3 200 200 V Notes 1 The input voltage must not exceed maximum supply voltage unless otherwise specified 2 Equivalent to discharging a 100 pF capacitor through a 1 5 kQ series resistor
7. status byte 1 it can be read by the microcontroller and may be used for any CMOS level compatible input signals These are the supply ground pins all of which must be connected Duration of the one tape block li 5 3 ms g AZCHK 8 periods MCLK 1 3 us MEA705 This is a measure of the azimuth error Nominal Inter Frame Gap IFG lasts 660 us Fig 25 AZCHK timing May 1994 30 Philips Semiconductors Drive processor for DCC systems Vpp7 This is the supply pin for the output buffers to the data lines of the system RAM It should always be connected externally Decouple this pin with a 22 nF capacitor to the Vss7 pin Vss7 This is the ground supply pin for the output buffers of the data lines of the system RAM This pin is connected Table 22 Interrupt mask register Preliminary specification SAA3323 internally to all the supply ground pins Vss to Vsse however it should always be connected externally Auxiliary envelope detection INTMASK INTMASK is a interrupt mask register This register sets the mode of operation for the interrupt interface and is writable only BIT Meaning Default 0 0 0 0 0 0 0 0 Notes 1 Vup rising edge of VIRGIN interrupt 2 AEup rising edge of AUX envelope interrupt 3 AEdn falling edge of AUX envelope interrupt 4 Lup rising edge of LABEL interrupt 5 Ldn falling edge of LABEL interrupt 6 ECZ AU
8. A12 PINO5 A7 A6 A5 VDD3 MLB763 May 1994 766 BIN speed control CAPSTAN DRIVE analog DAC output TDA1305 R sae SFC3 Ss WRAMP baseband 4 SAA2003 TDA1381 12s STEREO WRITE AMP FILTER CODEC O L FIXED tape analog ADC SAA3323 HEAD input SAA7366 DRIVE R 2 PROCESSOR O fitered 2S SB SE TDA1380 ADAS3 READ AMP SAA2013 ADAPTIVE ALLOCATION DIGITAL IEC958 AUDIO VO MECHANICS TDA1315 DRIVERS search data analog CC L output Jelec analog CC 7 mie R output AUDIO IN OUT PASC PROCESSOR TAPE DRIVE PROCESSING SYSTEM MICROCONTROLLER SYSTEM CONTROL Fig 4 DCC system block diagram MBD620 NOILdIHOS3Ad TVWNOILONNA suwals s 90 104 JOSS39010 SAL ECEEVVS SJOJONPUODIWAS sdi lyd uonyeonosds Meuiwlald Philips Semiconductors Drive processor for DCC systems A simplified block diagram of the SAA3323 is shown in Fig 1 DCC drive processing The SAA3323 provides the following functions for the DCC drive processing PLAYBACK MODES e Analog to digital conversion e Tape channel equalization e Tape channel data and clock recovery e 10 to 8 demodulation e Data placement in system RAM e C1 and C2 error correction decoding Interfacing to sub band serial PASC interface Interfacing to microcontroller for SYSINFO and AUX data e Capstan control for tape deck RECORD MODES Interfacing to sub band serial PASC interf
9. DRAM the address pins AO to A8 should be connected to the address input pins of the DRAM When SAA3323 is used with SRAM these are the lower address pins and should be connected directly to the SRAM address pins A11 This output pin is the an address pin for the SRAM and when SRAM is used they should be connected directly to the address pins of the SRAM When DRAM is used this pin should not be connected A10 AND A12 TO A16 These output pins are the upper address pins for the SRAM and when SRAM is used they should be connected directly to the address pins of the SRAM When DRAM is used or when the small SRAM is used all or some of these pins become available as Port expander outputs Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 Table 15 Port expander outputs PIN PORT EXPANDER TQFP80 OUTPUT A14 PINO1 RType 00 A13 PINO2 RType 00 A16 PINO3 RType 00 or RType 01 A15 PINO4 RType 00 or RType 01 A12 PINO5 RType 00 PIN NAME CONDITIONS DO To D3 When SAA3323 is used with SRAM these I O pins form the lower nibble of the data bus connection to the RAM and should be connected to the corresponding data I O pins of the SRAM When SAA3323 is used with DRAM these input output pins are the data lines for the RAM they should be connected directly to the DRAM data I O pins D4 To D7 These input output pins are the upper nibble of the data bus for use wi
10. SOT318 2 QFP80 May 1994 53 Philips Semiconductors Drive processor for DCC systems SOLDERING Plastic quad flatpacks BY WAVE During placement and before soldering the component must be fixed with a droplet of adhesive After curing the adhesive the component can be soldered The adhesive can be applied by screen printing pin transfer or syringe dispensing Maximum permissible solder temperature is 260 C and maximum duration of package immersion in solder bath is 10 s if allowed to cool to less than 150 C within 6 s Typical dwell time is 4 s at 250 C A modified wave soldering technique is recommended using two solder waves dual wave in which a turbulent wave with high upward pressure is followed by a smooth laminar wave Using a mildly activated flux eliminates the need for removal of corrosive residues in most applications BY SOLDER PASTE REFLOW Reflow soldering requires the solder paste a suspension of fine solder particles flux and binding agent to be May 1994 54 Preliminary specification SAA3323 applied to the substrate by screen printing stencilling or pressure syringe dispensing before device placement Several techniques exist for reflowing for example thermal conduction by heated belt infrared and vapour phase reflow Dwell times vary between 50 and 300 s according to method Typical reflow temperatures range from 215 to 250 C Preheating is necessary to dry the past
11. 3 Equivalent to discharging a 200 pF capacitor through a 0 Q series resistor DC CHARACTERISTICS Vop 2 7 to 3 6 V Tamb 40 to 85 C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT Supply supply voltage supply current digital plus analog see Fig 39 inputs with internal pull down to Vss all other inputs to Vss or Vpp Inputs CLK24 L3CLK L3MODE PINI SLEEP and SBMCLK LOW level input voltage HIGH level input voltage input current Vi 0 V to Vpop Tamb 25 C Inputs TESTO TEST1 and TEST2 LOW level input voltage HIGH level input voltage l input current Vi Vpp Tamb 25 C 25 400 uA May 1994 44 Philips Sem iconductors Drive processor for DCC systems SYMBOL PARAMETER CONDITIONS Preliminary specification SAA3323 Input RESET ViLH ViHL positive going threshold negative going threshold Vhys Outputs AZCHK CHTST1 CHTST2 ERCOSTAT L3INT L3REF MCLK PINO3 RDSYNC SBDIR SBE hysteresis Vi y to Vint TCLOCK and WDATA HIGH level output voltage lo 1 mA F URDA VoH VoL LOW level output voltage lo 1 mA HIGH level output voltage Vpop 0 5 V e 0 4 V Outputs AO to A8 A9 CAS A10 RAS OEN and WEN V VoH VoL LOW level output voltage Outputs SPEED and PINO2 lo 2 mA Nnn 0 5 lo 2 mA lo 1 mA 0 4 VoH HIGH level output v
12. L3 interface timing and typical transfers 2 SWAISAS 90 104 10ss 901d SAL ECEEVVS SJOJONPUOCDIWAS sdilyd uoneonosds Meulwljald Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 SAA3323 test pins PINO1 TESTO To TEST3 This output pin is connected directly to the PINO1 bit of the TFE settings O register The microcontroller can set or These input pins are for test only do not connect reset this pin AZCHK This output pin indicates the occurrence of a tape channel sync symbol on tape channels TCHO and TCH7 the distance between the pulses for the TCHO and TCH7 channels gives a measure of the azimuth error between the tape and head alignment Figure 25 shows the typical timing for this signal PINO2 TO PINO5 Depending upon the type and the size of system RAM used some or all of these Port expander output pins may be available please see Section RAM connections A10 and A12 to A16 on interfacing to the RAM pins Supply pins ERCOSTAT Vpp1 TO Vppe This output pin can be connected to a symbol error rate These are the supply pins all of these pins must be measurement system connected We recommend that each power supply pin l pair i e Vpp1 to Vss1 Vpp2 to Vss2 etc be decoupled Port expansion pins using a 22 nF capacitor as close as is physically possible PINI to the pins of the SAA3323 This input pin is connected directly to the PINI bit in the Vss1 TO Vege
13. Vssa L3REF 11 50 VDD4 RESET 12 49 A8 SLEEP 13 48 A13 PINO2 CLK24 14 47 WEN AZCHK 15 46 A15 PINO4 MCLK 16 45 A16 PINO3 TEST3 17 44 A14 PINO1 ERCOSTAT 18 43 A12 PINOS OEN 19 42 A7 A10 RAS 20 41 A6 SI TN 8 al 8 8 a 8 Sy ISI lal fe e 31 3 18 fa 8 8 2 a E G Z Os aoe 9 a 2 B S Z z Z 2 Z B 2 2 TIE gt gt gt gt gt gt Fig 2 Pin configuration SOT315 1 TQFP80 May 1994 6 Philips Semiconductors Drive processor for DCC systems SBWS SBCL SBDA SBDIR SBMCLK URDA L3MODE L3CLK L3DATA LSINT Vpp1 Vss1 L3REF RESET SLEEP CLK24 AZCHK MCLK TESTS ERCOSTAT OEN A10 RAS Vop2 Vss2 TIRE SPE SOS ee eee 2 R 2 s fel 5 la el T 5 3 lo le gt o lel fee leo gt e S 9 Oo wo E E Dn o gt UU lt lt n S Or p a UU E E Yn n a n Y a 9 Z Z 00 K FE Ga AF GHz SHS 3 0 K K EE O OF gt E gt gt HR GD FS o o foe LD to t m N Kad o o foe co LO 00 N N N N N N N N N Pe co co co co co Baja jajajjaja jajajajajaj 56464686868 8 6 6 FB Z lt gt 92 Z F Q GS Yn gt gt gt Fig 3 Pin configuration SOT318 2 QFP80 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 Preliminary specification SAA3323 TCLOCK WDATA PINO2 SPEED A11 A9 CAS Vss4 Vpp4 A8 A13 PINO2 WEN A15 PINO4 A16 PINO3 A14 PINO1
14. 21 WDATA and TCLOCK timing Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 Tape deck capstan control connections SPEED This pin outputs a pulse width modulated signal that may be used for controlling the tape capstan of the deck Operation of the SPEED control signal Table 19 gives the sources that determine the duty factor of the SPEED signal Note that the 3 state SPEED output may be put into high impedance state by programming the TFE setting by bit HiZSpd Table 19 SPEED signal duty factor SOURCE FOR MODE uCSPD SPEED DUTY FACTOR Notes 1 Tape means that the duty factor has been calculated from the played back main data tape signal When tape is the source for the duty factor of the SPEED signal the type of regulation can be chosen with the TFE settings bits EnFReg and SelNBand 2 uC means that the microcontroller programs the duty factor via the SPDDTY register 3 50 means that the duty factor is fixed at 50 May 1994 25 Philips Semiconductors Drive processor for DCC systems Preliminary specification SAA3323 MEA717 100 91 af ae Lee factor speed 50 9 0 ge 1 65 blocks 8 8 ms 2 blocks 10 6 ms If EnFReg is programmed LOW then there is phase regulation of the capstan speed The period of the pulse width modulated SPEED signal is 41 66
15. 23 lt lt twp lt lt twp WEN OEN OS LC R RE GA AD tO A16 A ADDRESS DO to D7 MGB391 WRITE READ MODIFY WRITE Fig 15 Fast SRAM write cycle timing RTim 01 a tyyp typ gt WEN OEN tens L A O AO to A16 XKL ADDRESS OA ADDRESS A RE SS See tpow2 1DH2 MGB392 het AA tWOA WRITE READ MODIFY WRITE Fig 16 Fast SRAM write cycle timing RTim 10 May 1994 21 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 WEN OEN SSN SONNY A A SSOP O to A16 288282 MGB393 WRITE READ MODIFY WRITE Fig 17 Fast SRAM write cycle timing RTim 11 WEN OEN aotoaie BERR LEDER ADDRESS Reon ESOS DO to D7 RY SK tan ton MGB394 Fig 18 Slow SRAM read cycle timing May 1994 22 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 Fig 19 Slow SRAM Table 16 Timing values for Figs 10 to 12 SYMBOL VALUE ns gt 110 DH WRITE write cycle timing Table 17 Timing values for Figs 13 to 17 SYMBOL VALUE ns me 2510 gt 140 gt 180 23 May 1994 Table 18 Timing values for Figs 18 and 19 SYMBOL VALUE ns twp 2225 Philips Semiconductors Drive processor for DCC systems Read write connection
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17. A SBCL SBWS SPEED URDA CONTROL RESET ERROR RAM INTERFACE SLEEP CORRECTOR INTERFACE Sere L3REF L3DATA MLB761 AO to A10 A11 to A16 L3MODE L3CLK 1 FIR Finite Impulse Response 2 IIR Infinite Impulse Response Fig 1 Block diagram May 1994 3 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 PINNING PIN SYMBOL DESCRIPTION TYPE SBWS 1 79 word select for sub band PASC interface I O 1 mA SBCL 80 SBDA bit clock for sub band PASC interface I O 1 mA data line for sub band PASC interface UO 1 mA direction line for sub band PASC interface O 1 mA master clock for sub band PASC interface L3CLK unreliable data O 1 mA mode line for L3 interface L3DATA i bit clock line for L3 interface serial data line for L3 interface I O 2 mA 8 9 L3 interrupt output O 1 mA digital supply voltage S digital ground S L3 bus timing reference SLEEP reset SAA3323 CLK24 AZCHK sleep mode selection of SAA3323 24 576 MHz clock input MCLK TEST3 channel 0 and channel 7 azimuth monitor 6 144 MHz clock output ERCOSTAT O 2 13 14 15 16 17 18 TEST3 output do not connect ERCO status for symbol error rate measurements A10 RAS output enable for RAM address SRAM RAS DRAM OIO Vpp2 Vss2 digital supply voltage digital ground data SRAM UO 4 mA ll
18. ANAEYE resolution ANAEYE output voltage ZL gt 1MQ May 1994 51 Philips Semiconductors Drive processor for DCC systems PACKAGE OUTLINES Preliminary specification SAA3323 A seating plane Doa TS A e a E E DQM AT ATATATATATATATATATATATATATATATATATATIO T Li 0 15 B oo n w 0 Nw MBB947 Dimensions in mm HIST LL pe detail X Fig 42 Plastic thin quad flatpack 80 leads body 12 x 12 x 1 4 mm SOT315 1 TQFP80 May 1994 52 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 pin 1 index DN _e ie Ls 0 20 M A E La 12 4x 08 0 8 x 14 1 E 13 9 A j 14 ae 1 2 f 3 2 2 65 0 25 4 0 25 27 0 05 0 14 i Me Fy a ae 4 4 1 el HO a n an 0 6 o detail X MSA394 1 Dimensions in mm Fig 43 Plastic quad flatpack 80 leads lead length 1 95 mm body 14 x 20 x 2 7 mm high stand off height
19. Access Memory RAM Scratch pad RAM for microcontroller in system RAM Integrated interface for Precision Adaptive Sub band Coding PASC data bus Three wire microcontroller L3 interface Protection against invalid auxiliary data Seamless joins between recordings GENERAL DESCRIPTION The SAA3323 performs the drive processor function in the DCC system This function is built up of digital equalizer error correction and tape formatting functions The digital equalizer is intended for use with DCC read amplifiers TDA1318 or TDA1380 The tape formatting and error correction circuit is intended for use with PASC ICs SAA2003 and SAA2013 and write amplifiers TDA1319 or TDA1381 playback and recording ORDERING INFORMATION PACKAGE TYPE NUMBER PINS PIN POSITION MATERIAL CODE SAA3323H TQFP80 SAA3323GP Note 1 QFP80 1 plastic SOT315 1 plastic SOT318 2 When using reflow soldering it is recommended that the Dry Packing instructions in the Quality Reference Pocketbook are followed The pocketbook can be ordered using the code 9398 510 34011 May 1994 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 BLOCK DIAGRAM SAA3323 DIGITAL TO ANALOG CONVERTER ANAEYE RDSYNC ANALOG RDMUX TO DIGITAL BIAS CONVERTER Vret p Vref n AUXILIARY ENVELOPE DETECTION EQUALIZER MODULE SBDIR SBMCLK SBEF SUB BAND TCLOCK 12s SBDA INTERFACE WDAT
20. GB404 BR i l a a T 28 frequency loop range limitation bit rate deviation LAY A W A 22 frequency loop range limitation 3 20 nase p K N K Arch a L 16 frequency loop range limitation 2 1 bee oleae Ac HTN yb 8 frequency loop range limitation 10 1 Gain 4 0 S A L 10 10 f Hz 10 2 Gain 3 3 Gain 2 Fig 30 Clock extraction PLL lock characteristic May 1994 37 Philips Semiconductors Drive processor for DCC systems RD1 and RDO return delay This is the delay before returning to normal mode after being in extended range mode i e the number of consecutive channel clock bit periods where the bit clock frequency falls within the normal range before the clock extraction returns to normal frequency mode Table 42 RD1 and RDO return delay RD DELAY IN BITS TO RETURN TO NORMAL MODE SYSINFO and AUX data offsets in the SAA3323 AUX data consists of 4 blocks of 36 bytes one block being transferred in each n time segment Table 43 Block offsets with respect to time segment Preliminary specification SAA3323 The 128 bytes in each tape frame contain SYSINFO The SYSINFO bytes can for convenience be considered as being grouped into 4 SYSINFO blocks with SYSBLKO gt SIO to SI31 SYSBLK1 gt SI31 to S163 etc In modes DPAP and DRAR SYSINFO transfers may occur in two ways 1 4 blocks of 36 bytes one block being transferred to the SAA3323 in each time segment
21. H when used for bypassing So if it is not in bypass mode and at least one of the interrupts has occurred it will go LOW and stays LOW until DEQ status byte 0 has been read Extra interrupts that occur after the first interrupt and before the DEQ status byte 0 is read are seen in the status register Extra interrupts that occur after the status byte Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 has been read will generate a new interrupt Interrupts that are already noted in the digital equalizer Status 0 are cleared by reading it Table 24 Digital equalizer STATUSO BIT 7 6 5 4 3 2 1 0 Meaning BKSW TEST Vup Y AEup S AEdn Lup 5 Ldn ECZO Notes 1 BKSW filter bank switched indicates that the last main data coefficients sent to the digital equalizer have been activated Vup indicates whether an interrupt caused by the rising edge of VIRGIN has occurred AEup indicates whether an interrupt caused by the rising edge of AUX envelope has occurred AEdn indicates whether an interrupt caused by the falling edge of AUX envelope has occurred Lup indicates whether an interrupt caused by the rising edge of LABEL has occurred Ldn indicates whether an interrupt caused by the falling edge of LABEL has occurred N OAR WD ECZ indicates that the AUX envelope counter has reached zero j taux gt RDMUX AENV MGB400 Fig 26 AUX channel envelope to AENV delays
22. HASE OF AUX WRT MAIN DATA CHANNELS Jo 2 a o 2 3 o 1 213 o 1 2 IS T AUX MAIN DATA INPUT FROM TAPE AUX BLK AUX MAIN DATA INPUT FROM TAPE SNUM Fig 32 SYSINFO and AUX block delays in DPAP mode Fig 31 SYSINFO and AUX block delays in DPAP mode May 1994 Preliminary specification Philips Semiconductors SAA3323 Drive processor for DCC systems Q S 8 LOSI L DN N o o N o 99 G S o 09 N o o 52 e r Saa T Er gt a 25 x 72w par x ZO a a ans gt x n SC Z 5 gt 3x0 Rd E Rel zar orn oO Sos eos POSO SLI POR POR RRE _ Jol 2 3 o 1 2 3 o0 1 2 3 0 1 2 Fig 33 SYSINFO and AUX block delays in DRAR mode AUX BLK SYS BLK Bio UBI sls 1 2 10055 aE SNUM SYS BLK A T ROOK PRK KY RRRS Fig 34 SYSINFO and AUX block delays in DPAR mode FROM TAPE AUX OUTPUT TO TAPE MAIN DATA INPUT 40 May 1994 Philips Semiconductors Drive processor for DCC systems Scratch pad RAM The SAA3323 provides the microcontroller with a scratch pad RAM that the microcontroller can use for whatever it likes The size of the scratch pad depends upon the size and type
23. NDITION TIME tw lt 140 ns tsu lt 72 ns Write pulse duration Data set up to rising WEN Write cycle time Tey lt 200 ns Read access time tacc lt 240 ns Note 1 The SAA3323 should work in RType 01 RTim 00 mode A9 CAS When SAA3323 is used with SRAM this output pin is Address line 9 and should be connected directly to the corresponding address pin on the SRAM When SAA3323 is used with DRAM this output pin is the column address strobe active LOW it connects directly to the column address strobe pin of the DRAM A10 RAS When SAA3323 is used with SRAM this output pin is Address line 10 and should be connected to the corresponding address pin of the SRAM When SAA3323 is used with DRAM this output pin is the row address strobe active LOW it connects directly to the row address strobe pin of the DRAM May 1994 Preliminary specification SAA3323 OEN This output pin is the output enable active LOW for the RAM it connects directly to the output enable pin of the RAM WEN This output pin is the write enable active LOW for the RAM it connects directly to the write enable pin of the RAM AO To A8 When SAA3323 is used with DRAM these output pins are the multiplexed column and row address lines When the 64K x 4 bit DRAM is used pins AO to A7 should be connected to the DRAM address input pins and pin A8 should be left unconnected When using the 256K x 4 bit
24. RITE FIR coefficients from active bank DIGITAL EQUALIZER COMMANDS These are the commands that need to be sent to the digital equalizer in order to access the indirectly accessible registers and the data streams COMMAND BYTE NAME Gl WRCOEF EXPLANATION write FIR coefficients to the digital equalizer buffer bank o ojojo O RDCOEF LDCOEFCNT LDFCTRL ojo o read FIR coefficients from the digital equalizer active bank 1 OE 1 load FIR coefficient counter load filter control register LDT1SEL LDT2SEL o ojojo load CHTST1 pin selection register LDTAEYE LDAEC 1 load CHTST2 pin selection register O load ANAEYE channel selection register load AEC counter RDAEC RDSSPD read AEC counter read SEARCH speed register ojojo ojojojo xzloO o LDINTMSK LDDEQ3SET ojojo o lG l i Ol Ol Oll k load interrupt mask register load digital equalizer settings register ojo ojo o ao LDCLKSET Table 10 Filter control register load PLL clock extraction settings register BIT 7 6 5 Meaning Reserved Default Note 1 1 CS is a microcontroller controlled coefficient bank switch This causes the filter coefficients to be activated at a time that is safe for the digital equalizer i e at the end of the FIR program and that the complete value of coefficient number 9 has been r
25. S for DRAM E 54 i 5 O O O 1 1 mA 5 6 serial output to write amplifier 1 mA 7 5 O 5 3 072 MHz clock output for tape I O O 1 mA 58 digital ground S 59 digital supply voltage S 60 TEST mode select do not connect lnd 61 analog multiplexed input from read amplifier la 62 ADC positive reference voltage BIAS Vssa VDDA 65 bias current for ADC la 66 analog ground S ANAEYE 6 analog supply voltage S 6 analog eye pattern output Oa Vss6 73 digital ground CHTST1 7 8 RDSYNC 71 69 71 2 74 7 channel test pin 1 channel test pin 2 TEST mode select do not connect May 1994 TEST mode select do not connect lnd Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 PIN SYMBOL DESCRIPTION TYPE QFP80 TQFP80 PINI 78 76 Port expander input 7 OUMA SBEF 80 78 sub band PASC error flag line O 1 mA Note 1 I input la analog input lpa input with pull down resistance I O bidirectional O output Oa analog output O 3 state output S supply a u 5 Er E L 5 o z lt lt x E zas5 SI IR IRI INI IRI RR RA RIEL RS Jej JS fs le IS 8 JS lo SBDA 1 60 TEST2 SBDIR 2 59 VDD5 SBMCLK 3 58 Vss5 URDA 4 57 TCLOCK L3MODE 5 56 WDATA L3CLK 6 55 PINO2 L3DATA 7 54 SPEED L3INT 8 53 A11 Vpp1 9 52 A9 CAS Vgg1 10 51
26. Spain Balmes 22 08007 BARCELONA Tel 03 301 6312 Fax 03 301 42 43 Sweden Kottbygatan 7 Akalla S 164 85 STOCKHOLM Tel 0 8 632 2000 Fax 0 8 632 2745 Switzerland Allmendstrasse 140 CH 8027 ZURICH Tel 01 488 2211 Fax 01 481 77 30 Taiwan PHILIPS TAIWAN Ltd 23 30F 66 Chung Hsiao West Road Sec 1 Taipeh Taiwan ROC P O Box 22978 TAIPEI 100 Tel 02 388 7666 Fax 02 382 4382 Thailand PHILIPS ELECTRONICS THAILAND Ltd 209 2 Sanpavuth Bangna Road Prakanong Bangkok 10260 THAILAND Tel 662 398 0141 Fax 662 398 3319 Turkey Talatpasa Cad No 5 80640 GULTEPE ISTANBUL Tel 0212 279 2770 Fax 0212 269 3094 United Kingdom Philips Semiconductors Limited P O Box 65 Philips House Torrington Place LONDON WC1E 7HD Tel 071 436 41 44 Fax 071 323 03 42 United States INTEGRATED CIRCUITS 811 East Arques Avenue SUNNYVALE CA 94088 3409 Tel 800 234 7381 Fax 708 296 8556 DISCRETE SEMICONDUCTORS 2001 West Blue Heron Blvd P O Box 10330 RIVIERA BEACH FLORIDA 33404 Tel 800 447 3762 and 407 881 3200 Fax 407 881 3300 Uruguay Coronel Mora 433 MONTEVIDEO Tel 02 70 4044 Fax 02 92 0601 For all other countries apply to Philips Semiconductors International Marketing and Sales Building BAF 1 P O Box 218 5600 MD EINDHOVEN The Netherlands Telex 35000 phtcnl Fax 31 40 724825 SCD31 O Philips Electronics N V 1994 All rights are reserved Reproduction in whole o
27. X envelope counter has just reached zero interrupt BP1 AND BPO BYPASS If any of the bypass bits are HIGH then the interrupts are not passed on to the microcontroller instead the level of the corresponding signal is available an the interrupt pin Table 23 BP1 and BPO EFFECT OF BYPASS 1 LAB on L3INT pin note 1 0 AENV on L3INT pin note 2 VIR on L3INT pin note 3 Notes 1 LAB LABEL HIGH if a LABEL condition is detected in the envelope of the AUX channel 2 AENV envelope of the AUX channel 1 bit binary 3 VIR VIRGIN indicated by the total continuous absence of signal on the AUX channel May 1994 The AUX envelope information is only valid when the digital equalizer is in search mode and when the tape speed is between the values of 3 to 48 x nominal tape speed The timing relationships between the AUX channel input signal AENV LAB and VIR are shown in Figs 26 to 28 The delays tg and ta2 are between 0 25 and 0 5tayx AUX envelope periods The delays tas tas tas and tag are between 2 and 6tayx AUX envelope periods When using the digital equalizer in search mode first program the digital equalizer to search mode then program the INTMASK register MASK If the BP1 and BPO bits are LOW then the mask bits take effect Any combination of the mask bits may be HIGH enabling the corresponding interrupts The interrupt pin L3INT is active LOW when used for interrupts and active HIG
28. a eae T ES Meaning T2F2 T2F1 T2F0 T2C3 T2C2 T2C1 T2C0 Default 0 0 0 0 0 0 0 Table 34 T2C3 to T2C0 CHTST2 pin channel selections Table 35 T2F2 to T2FO CHTST2 pin function selections CHANNEL ON CHTST2 FUNCTION OF CHTST2 PIN 2 0 0 0 off logic 0 1 digital eye pattern O sliced data 1 bit clock clock extraction frequency ojojo GIGI Kl Ol Ol e e a U S S C3 l o May 1994 35 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 rosync OS MGB403 Fig 29 CHTST1 and CHTST2 output timing Table 36 DEQSET a equalizer settings Note 1 ACup is the AUX envelope counter direction is up This setting caused the AUX envelope counter increment or to decrement by 1 every rising edge of the AUX envelope signal AENV DM1 and DMO Table 37 DM1 and DMO digital equalizer mode of operation MODE OF OPERATION OF DIGITAL EQUALIZER normall 0 1 search 2 1 0 off 3 1 1 off s Notes 1 In normal mode the main data channels and the AUX channel are processed equalized the AUX channel envelope information is not processed 2 In search mode only the AUX channel is processed by the digital equalizer 3 Off means that the digital equalizer is put to sleep low power this can be used for example in portable recording equipment RDSYNC is HIGH if off mode Also note that the oth
29. ace e C1 and C2 error correction encoding Formatting for tape transfer e 8 to 10 modulation Interfacing to microcontroller for SYSINFO and AUX data e Capstan control for tape deck programmable by microcontroller SEARCH MODE e Detection and interpretation of AUX envelope information e AUX envelope counting e Search speed estimation Tape Formatting and Error TFE correction module The TFE module has 3 basic modes of operation as shown in Table 1 May 1994 Preliminary specification SAA3323 Table 1 Basic modes of TFE module EXPLANATION audio and SYSINFO main data play AUX play audio and SYSINFO main data play AUX record audio and SYSINFO main data record AUX record MODE TFE REGISTERS The TFE module has 8 writable and 5 readable registers that are accessible via the L3 interface one write register CMD and four read registers STATUSO to STATUS3 which are directly addressable the other registers are indirectly addressable via commands sent to the CMD register The registers are named as shown in Table 2 Table 2 TFE register names REGISTER NAME READ WRITE CMD W STATUSO STATUS1 STATUS2 STATUS3 SET2 SET3 1 SPDDTY BYTCNT RACCNT SPEED SETO SET1 Y Note 1 The 4 LSBs of register SET3 set RAM type RType and RAM timing RTim See Table 3 For normal operation the 4 MSBs of register SET3 should be logic 0 P
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31. au b L3MODE o gt tho L3CLK ta tn LSDATA pa f c j E j microcontroler ZAA 0 KR KIA KER KERA KEAS KA KER KE teui C L3MODE LH tho lt L3CLK ta S va el w L3DATA p p C p C C C C SE NSN ST gt td MGB398 tag uta a Halt mode b Addressing mode c Data mode transfer from microcontroller to SAA3323 d Data mode transfer from SAA3323 to microcontroller Fig 23 L3 interface timing and typical transfers 1 May 1994 28 EGG L AeW DC EMODE Na MAR ON MN Ve IR AN L3CLK SLL L3DATA gt 3 gt gt gt GD GD GD a TFE3 WCMD LDSETO TFE3 WDAT SETO DATA TFE3WCMD LDSET1 TFE3 WDAT SET1 DATA a L3MODE N NY V V ss L3CLK J UU J l l l IU L3DATA TTT TFE3 RSTAT STATUSO STATUS1 STATUS2 STATUS3 DATA DATA DATA DATA b LME XO A O O O O O A I _ FRO L3CLK UIT WW L3DATA XD OD OD OT eee O TFE3 WCMD LDBYCYNT TFE3 WDAT D8HEX TFE3 WCMD RDSYS TFE3 RDAT SYSINFO 8 SYSINFO 9 TFE3 WCMD LDBYCYNT TFE3 WDAT D8HEX TFE3 WCMD RDSYS TFE3 RSTAT STATUSO TFE3 RDAT SYSINFO 8 DATA MGB399 IMODE NM IN IT ON L3CLK MMU UUU UU UU L3DATA A LCS TFE3 RSTAT STATUSO TFE3 RDAT SYSINFO 9 d DATA y a Write settings bytes 0 and 1 to TFE3 part of SAA3323 b Read all 4 status bytes from TFE part of SAA3323 c Read 2 SYSINFO bytes starting at byte 8 in high speed transfer part of program d Read 2 SYSINFO bytes starting at byte 8 in low speed transfer part of program Fig 24
32. cs sections of the specification is not implied Exposure to limiting values for extended periods may affect device reliability Application information Where application information is given it is advisory and does not form part of the specification LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale DIGITAL cc C The Digital Compact Cassette logo is a registered trade mark of Philips Electronics N V COMPACT CASSETTE May 1994 55 Philips Semiconductors a worldwide company Argentina IEROD Av Juramento 1992 14 b 1428 BUENOS AIRES Tel 541 786 7633 Fax 541 786 9367 Australia 34 Waterloo Road NORTH RYDE NSW 2113 Tel 02 805 4455 Fax 02 805 4466 Austria Triester Str 64 A 1101 WIEN P O Box 213 Tel 01 60 101 1236 Fax 01 60 101 1211 Belgium Postbus 90050 5600 PB EINDHOVEN The Netherlands Tel 31 40 783 749 Fax 31 40 788 399 Brazil Rua do Rocio 220 5 floor Suite 51 CEP 04552 903 SAO PAULO SP Brazil P O Box 7383 01064 970 Tel 011 821 2327 Fax 011 829 1849 Canada INTEGRATED CIRCUITS Tel 800 234 7381 Fax 708 296 855
33. d BYTCNT registers is shown in Table 45 Philips Semiconductors Drive processor for DCC systems Preliminary specification SAA3323 Table 45 Mapping of scratch pad RAM address for RAM quarter YZ 00 REGISTER RACCNT BYTCNT Value P2 P1 PO C2 C1 CO For The other three quarters of the RAM the mapping of the scratch pad RAM address onto the RACCNT and BYTCNT registers is shown in Table 46 Table 46 Mapping of scratch pad RAM address for RAM quarter YZ 01 10 and 11 REGISTER RACCNT BYTCNT Mode changes The possible mode changes for the TFE are shown in Table 47 Table 47 Mode changes CURRENT NEW MODE MODE DPAP TIMING FOR SAA3323 MODE CHANGES Mode change DPAP to DRAR This mode change occurs at the end of the time segment in which the TFE module receives the new settings Writing of the first Main and AUX data to tape starts at the start of the time segment 1 which occurs 2 end of time segment 3 s after the mode change The delay to writing to tape is approximately 222 ms as shown in Fig 35 If seamless appending is required the new settings should be sent to the TFE module during time segment 2 Mode change DPAP to DPAR This mode change occurs at the first end of time segment 2 after the TFE module receives the new settings Output of AUX to tape begins at the start of the following time segment 1 i e approximately 85 3 ms after the mod
34. d master clock input for the sub band serial PASC interface The frequency of this signal is nominally 6 144 MHz When the SAA3323 is used with SAA2003 this pin is tied to ground and the TFE settings bit DRPMAS set to logic 1 SBDIR This output pin is the sub band serial PASC bus direction signal it indicates the direction of transfer on the sub band serial PASC bus This pin connects directly to the SBDIR pin on the SAA2003 The transfer directions are shown in Table 13 Table 13 PASC bus transfer directions SBDIR DIRECTION 1 SAA3323 to SAA2003 transfer audio play 0 SAA2003 to SAA3323 transfer audio record May 1994 This input output pin is the bit clock line for the sub band serial PASC interface to the SAA2003 When used with SAA2003 this pin is input only It has a nominal frequency of 768 kHz SBWS This input output pin is the word select line for the sub band serial PASC interface to the SAA2003 When used with SAA2003 this pin is input only It has a nominal frequency of 12 kHz SBDA This input output pin is the serial data line for the sub band serial PASC interface to the SAA2003 SBEF This active HIGH output pin is the error per byte line for the sub band serial PASC interface to the SAA2003 Philips Semiconductors Drive processor for DCC systems URDA This active HIGH output pin indicates that the main data audio the SYSINFO and the AUXILIARY data are NOT usable regardles
35. e and evaporate the binding agent Preheating duration 45 min at 45 C REPAIRING SOLDERED JOINTS BY HAND HELD SOLDERING IRON OR PULSE HEATED SOLDER TOOL Fix the component by first soldering two diagonally opposite end pins Apply the heating tool to the flat part of the pin only Contact time must be limited to 10 s at up to 300 C When using proper tools all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 C Pulse heated soldering is not recommended for SO packages For pulse heated solder tool resistance soldering of VSO packages solder is applied to the substrate by dipping or by an extra thick tin lead plating before package placement Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development Preliminary specification This data sheet contains preliminary data supplementary data may be published later Product specification This data sheet contains final product specifications Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System IEC 134 Stress above one or more of the limiting values may cause permanent damage to the device These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristi
36. e change as shown in Fig 36 May 1994 Mode change DRAR to DPAP This mode change occurs at the first end of time segment 0 after the TFE module receives the new setting Writing of Main and AUX data stops immediately after the mode change The time segment jumps back to logic 0 URDA goes HIGH and stays HIGH for 5 time segments i e approximately 213 3 ms after which it goes LOW as shown in Fig 37 Mode change DPAR to DPAP This mode change occurs at the first end of time segment 0 after the TFE module receives the new setting The writing of AUX data to tape stops immediately after the mode change The first AUX read from tape can be expected during the following time segment 0 or 1 i e approximately 128 to 170 67 ms after the mode change as shown in Fig 38 Mode change DPAP to search This mode change occurs almost instantaneously program the digital equalizer module in SAA3323 to go to search mode then program the interrupt mask register to select the required type of interrupt Mode change search to DPAP This mode change occurs almost instantaneously program the interrupt mask register to disable interrupts program the digital equalizer module of SAA3323 to go to normal mode A re synchronization will most likely occur when as result of the data being read from tape thus causing URDA to go HIGH Philips Semiconductors Drive processor for DCC systems snum o 1 2 sfo 1 2 sfo 1 2
37. eceived May 1994 11 Philips Semiconductors Drive processor for DCC systems Table 11 SH1 and SH2 FIR output scaling EFFECT ON FIR OUTPUT FIR mod 256 FIR 5 mod 256 FIR mod 256 Transfer of FIR coefficients For the main data channels tracks 0 to 7 there are 10 coefficients taps each of 8 bits where all of the data channels make use of the same coefficients The addresses for the main data coefficients 0 to 9 are 0 to 9dec respectively There are ten coefficients taps each of 8 bits for the aux channel CHAUX The addresses for the auxiliary coefficients O to 9 are 16 to 25gec respectively Table 12 Coefficient address counter BIT Preliminary specification SAA3323 There are 2 banks of coefficients for both the aux and the main data channels namely the buffer and the active banks The microcontroller writes only to the buffer banks and reads only from the active banks The microcontroller can poll the digital equalizer status bit BKSW to see when the switch occurs BKSW starts life LOW goes HIGH as a result of the bank switching and goes LOW as result of the complete value of a main data coefficient being received by the digital equalizer The microcontroller sets uCS HIGH before sending the new set of aux or main data coefficients the digital equalizer resets it once the bank switch occurs The actual FIR coefficients that are used are a fu
38. ed SYMBOL PARAMETER CONDITIONS MIN Clock inputs CLK24 foLkos clock frequency tos pulse width LOW toaH pulse width HIGH SBMCLK fsemcik clock frequency tscL pulse width LOW tscu pulse width HIGH 30 ns May 1994 46 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 SYMBOL PARAMETER CONDITIONS Clock output MCLK CL load capacitance tg delay time from SLEEP HIGH to SLEEP active ucLk clock frequency tmcL MCLK pulse width LOW 50 ns tucH MCLK pulse width HIGH 50 ns tod propagation delay time from rising ns edge of CLK24 Ci input capacitance L3CLK L3MODE AND RESET set up time to rising edge of MCLK hold time from rising edge of MCLK PINI set up time to rising edge of MCLK hold time from rising edge of MCLK load capacitance AO TO A8 tod propagation delay time from falling 50 edge of CLK24 A9 CAS A10 RAS AND OEN tod propagation delay time from falling edge of CLK24 delay time from SLEEP HIGH to SLEEP active propagation delay time from falling edge of CLK24 from falling edge of WEN to rising long write pulse edge of CLK24 mode delay time from SLEEP HIGH to SLEEP active propagation delay time from rising edge of MCLK tod propagation delay time from rising 55 ns edge of MCLK May 1994 47 Philips Semiconductors Preliminary specification Dri
39. er digital equalizer registers are not addressable while the digital equalizer is in off mode May 1994 36 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 CLKSET Table 38 CLKSET clock extraction settings BIT 7 6 5 4 3 2 1 0 Meaning Default Note 1 LEAE leakage enable this setting enables a leakage function in the PLL clock extraction loop filter This gives a slightly improved performance with high SER tapes at the cost of a slight decrease in dynamic performance For home static applications program this bit to logic 1 and for portable applications to logic 0 Table 39 FR1 and FRO clock extraction frequency range Table 40 GNOR gain in normal frequency range mode of control clock extraction FR EFFECT ON PLL FREQUENCY EFFECT ON GAIN IN NORMAL RANGE LOOP gain 2 for portable mobile applications range 8 gain 1 for home static applications range 16 3 Table 41 GE1 and GEO gain in extended frequency range 22 range 28 range mode of clock extraction GE EFFECT ON PLL GAIN IN EXTENDED Note that in the FR 0 range the clock extraction stays RANGE in its normal range only hence it does not enter the 0 0 extended range 0 1 Figure 30 shows the lock characteristic of the clock 1 0 extraction PLL 1 1 gain 5 do not use M
40. high speed at all times except the second half of time segment 0 that is when the status bit SLOWTFR is HIGH When SLOWTEFR is HIGH the microcontroller must poll the status bit RFBT to investigate when a transfer can occur Two addressing modes are available for the scratch pad namely random access and auto increment For random access mode the address of each location is sent by the microcontroller to the SAA3323 before each location transfer For auto increment mode the address of the first location is sent by the microcontroller before the first location transfer auto incrementing of the row occurs then for all transfers until the end of the column May 1994 The 8 bit transfers are initiated by the WRDRAC and RDDRAC commands these transfers are each 1 byte per memory location therefore the byte counter will increment after each byte transfer The 12 bit transfers are initiated by the WRDRAC and RDDRAC commands these transfers are each 2 bytes per memory location The first byte contains the 4 Most Significant Bits MSBs of the memory location in its 4 Least Significant Bits LSBs positions The other bit positions being don t care The second byte contains the 8 LSBs of the memory location The byte counter is incremented after the transfer of the second byte The RACCNT and BYTCNT registers are used for addressing the scratch pad For RAM quarter YZ 00 the mapping of the scratch pad RAM address onto the RACCNT an
41. hilips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 Table 3 RAM settings by register SET3 Table 4 TFE data streams RAM REGISTER SET3 DATA STREAM NAME READ WRITE RTYPE 0 SYSINFO RTYPE 1 RTim 0 AUXINFO Scratch pad RAM R W RTim 1 TFE DATA STREAMS The TFE module has three read write data streams that are accessible via the L3 interface and they are shown in Table 4 Table 5 TFE commands TFE COMMANDS These are the commands that need to be sent to the TFE in order to access the indirectly accessible registers and the data streams see Table 5 COMMAND BYTE NAME Gl EXPLANATION read SPEED register RDSPEED LDSETO LDSET1 o ojojoj o ojo load new TFE settings register O load new TFE settings register 1 load new TFE settings register 2 0 LDSET2 LDSET3 o load new TFE settings register 3 load SPDDTY register ojojojo LDSPDDTY LDBYTCNT ojojo load BYTCNT register load RACCNT register O a T ay lo o LDRACCNT RDAUX read AUXILIARY information read SYSINFO Njojojo z O lt o RDSYS RDDRAC read RAM data bytes 8 bits from quarter YZ read RAM data words 12 bits from quarter YZ Jal O N Ol RDWDRAC WRAUX write AUXILIARY information write SYSINFO k kc lk l O write RAM data bytes 8 bits to quarter YZ ojo
42. miconductors Preliminary specification Drive processor for DCC systems SAA3323 May 1994 SBWS in l SBDA in sect HPPP n Pnn nnn Ann SBWS in SBDA in bit number SBCL in VIH OH V SBWS in a OH SBDA in In OH gt gt 2XtucLk 40ns gt 40ns MGB381 Fig 5 Sub band serial PASC interface timing DRAR mode 13 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 SBCL out SBDA out SBEF out SBCL out SBDA out SBEF out JUUUU UU U U U U U U U U U U U U U U U U U U U U U U U U U U SBWS out SBMCLK in Prof TV v SBCL out gt 60 ns f3 EY A SBDA out aye OL a lt 7 ns V SBDA out X X ZNR OL l lt 7 ns MGB382 Fig 6 Sub band serial PASC interface timing in play modes DRPMAS logic 1 May 1994 14 Philips Semiconductors Drive processor for DCC systems SBDA out SBDA out Preliminary specification SAA3323 sect PULL ULL SBWS in oli 213 4 5 6 7 8 9 10171 12413 14 15 SBEF out l sect PUPIL ALL SBWS in 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SBEF out l bit number SBCL in S SBWS in aye gt 2xtMcLK 40ns gt 40 ns SBDA out S gt tmcLk 40 85 ns SBDA out S gt tMCLK 40 40 ns MGB383 Fig 7 Sub band serial PASC interface timing in play modes DRPMAS logic 0 SBMCLK SBCL This is the sub ban
43. nction of the tape head read amplifier and type of tape i e pre recorded or own recorded used such information is outside of the scope of this data sheet Coefficient address counter COEFCNT This 5 bit counter is used to point to the FIR coefficient to be transferred to or from the digital equalizer Meaning Default Pin explanations and interfacing to other hardware RESET This is an active HIGH input which resets the SAA3323 and brings it into its default mode DPAP This reset does not affect the contents of the FIR filter coefficients in the digital equalizer This should be connected to the system reset which can be driven by the microcontroller The duration of the reset pulse should be at least 15 us SLEEP This pin is an active HIGH input which puts the SAA3323 in a low power consumption SLEEP mode This pin should be connected to the DCC SLEEP signal which can be driven by the microcontroller The CLK24 clock may be stopped and the VREFP and VREFN inputs brought to ground while the SAA3323 is in sleep mode to further reduce power consumption When recovering from sleep May 1994 12 mode the SLEEP pin should be taken LOW and the SAA3323 reset CLK24 This is the 24 576 MHz clock input and should be connected directly to the SAA2003 pin CLK24 Sub band serial PASC interface connections The timing for the sub band serial PASC interface is given in Figs 5 to 7 Philips Se
44. of RAM used with the SAA3323 The locations in Preliminary specification SAA3323 the scratch pad RAM may be written and read in 8 bit or 12 bit units The RAM may be viewed as having up to 4 quarters the availability of these quarters for the scratch pad RAM is given in Table 44 Table 44 Availability of RAM quarters for the scratch pad RAM RTYPE TYPE OF RAM USED AVAILABLE RAM QUARTERS YZ DRAM 64K x 4 00 DRAM 256K x 4 00 01 10 and 11 SRAM 32K x 8 fast 00 SRAM 128K x 8 fast 00 01 10 and 11 SRAM 2x 32K x 8 slow 00 SRAM 128K x 8 slow 00 and 10 Note 1 In RAM quarter YZ 00 the scratch pad is arranged as 6 pages where each page consists of 7 columns x 64 rows The pages are numbered 0 to 5 the columns 1 to 7 and the rows 0 to 63 This gives a total of 6 x 7 x 64 2688 locations In each of the RAM quarters YZ 01 10 and 11 the scratch pad is arranged as 6 pages where each page consists of 8 columns x 448 rows The pages are numbered 0 to 5 the columns 0 to 7 and the rows 0 to 447 This gives then a total of 6 x 8 x 448 21504 locations per RAM quarter YZ During communication with the scratch pad RAM the RAM quarter YZ is chosen when sending the RDDRAC RDWDRAC WRDRAC or WRWDRAC commands to the TFE module Use of the scratch pad RAM outside the specified ranges is not allowed and it may upset the operation of the SAA3323 As with SYSINFO and AUX transfers can occur at
45. oj ojojo ojojo o oO O JO OJO O lt lt ojo lt NIN oO ojjojo k l Ol k Digital equalizer module The digital equalizer module has 2 basic modes of operation as shown in Table 6 Table 6 Basic modes of equalizer module Play main data and AUX channels are equalized Search only AUX channel is processed AUX envelope information is processed May 1994 write RAM data words 12 bits to quarter YZ DIGITAL EQUALIZER REGISTERS The digital equalizer module has 9 write only 3 read only and 1 read write register s that are accessible via the L3 interface one write register CMD and 2 read registers STATUSO and STATUS1 which are directly addressable the other registers are indirectly addressable via commands sent to the CMD register The registers are named as shown in Table 7 10 Philips Semiconductors Drive processor for DCC systems Table 7 Digital equalizer register names REGISTER NAME READ WRITE CMD STATUSO STATUS1 COEFCNT FCTRL CHT1SEL CHT2SEL ANAEYE AEC SSPD INTMASK DEQ2SET CLKSET 01 Z IEEE Table 9 Digital equalizer commands Preliminary specification SAA3323 DATA STREAMS The digital equalizer module has one write only and one read only data stream that are accessible via the L3 interface and they are shown in Table 8 Table 8 Digital equalizer data streams DATA STREAM NAME FIR coefficients to buffer bank READ W
46. oltage VoL LOW level output voltage loz 3 state leakage current lo 1 mA VI 0 V to Vpp Tamb 25 C 10 Inputs out puts SBCL SBDA and SBWS HIGH level output voltage lo 1 mA LOW level output voltage LOW level input voltage lo 1 mA outputs in 3 state HIGH level input voltage outputs in 3 state 3 state leakage current Vi lt 0 V to Vpp Tamb 25 C puts A11 to A16 and L3DATA HIGH level output voltage LOW level output voltage lo 2mA LOW level input voltage HIGH level input voltage lo 2mA outputs in 3 state outputs in 3 state Inputs out 3 state leakage current puts DO to D7 V 0 V to Vpp Tamb 25 C VoH HIGH level output voltage lo 4 mA VoL LOW level output voltage lo 4 mA IL IH loz 3 state leakage current V LOW level input voltage 0 V HIGH level input voltage 0 Vi lt V to Vpp Tamb 25 C utputs in 3 state utputs in 3 state 2 10 May 1994 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 Average current consumption MLB778 60 IDD mA max 40 typ 20 2 0 2 5 3 0 3 5 4 0 Vop V Fig 39 Average current consumption AC CHARACTERISTICS Vop 2 7 to 3 6 V Tamb 40 to 85 C C1 10 pF on all outputs see Fig 40 unless otherwise specifi
47. ondition continues If the deviation is between the POT and the FOT then the frequency information is gated with the Phase information for 50 of the time The deviation thresholds POT and FOT are programmable via the TFE settings bit SelNBand POT FOT SPIN Band DEVIATION FROM NOMINAL DEVIATION FROM NOMINAL 0 16 19 May 1994 Philips Semiconductors Drive processor for DCC systems If SLEEP is HIGH then the state of the SPEED signal will be the state that it was in just before the SAA3323 went into sleep Thus if SPEED was HIGH just before sleep it will stay HIGH during sleep The same applies if it was LOW or if it was in high Z state Note that a reset of the SAA3323 will take the SPEED signals out of high Z state Microcontroller connections L3REF This active LOW output pin indicates the start of a time segment it goes LOW for 5 2 us once every 42 66 ms approximately and can be used for generating interrups for the microcontroller If a re synchronization occurs then the time between the occurrences van vary This pin can be connected directly to the interrupt input of the microcontroller L3CLK This input pin is the clock line for the microcontroller interface L3DATA This input output pin is the serial data line for the microcontroller interface L3MODE This input determines the type of transfer that is occurring between the microcontroller and the SAA3323 IfL3MODE is LOW then a de
48. r in part is prohibited without the prior written consent of the copyright owner The information presented in this document does not form part of any quotation or contract is believed to be accurate and reliable and may be changed without notice No liability will be accepted by the publisher for any consequence of its use Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights Printed in The Netherlands 513061 1500 01 pp56 Document order number Date of release May 1994 9397 732 30011 Philips Semiconductors PHILIPS PHILIPS
49. s TCLOCK This output pin is the 3 072 MHz clock output for the read and write amplifiers it should be connected directly to the WCLOCK pin of the write amplifier and to the RDCLK pin of the read amplifier RDMUX This input pin carries the time multiplexed analog tape channel signals from the read amplifier Vret n AND Vret p These are the lower and upper voltage reference inputs for the ADC in the digital equalizer part of SAA3323 BIAS This pin defines a bias current for the ADC It should be connected to the analog supply voltage Vppa via a 47 KQ resistor Fig 20 RDMUX RDSYNC and TCLOCK timing Preliminary specification SAA3323 RDSYNC This output line provides synchronization information for the read Amplifier data transfers The relationship between TCLOCK RDSYNC and the channel information carried by the RDMUX line is given in Fig 20 This pin should be connected directly to the RDSYNC pin of the read amplifier When the digital equalizer in SAA3323 is in search mode this pin will be HIGH ensuring that only the AUX channel is processed by the SAA3323 WDATA This output pin is the multiplexed data and control line for the write amplifier Figure 21 shows the manner in which this information is multiplexed onto WDATA The WDATA pin should be connected directly to the WDATA pin of the write amplifier WDATA SYNC ZA a o lt T Q H May 1994 TERAUX TCHO TCH1 MGB397 Fig
50. s of the state of the corresponding reliability flags The state of this pin is reflected in the URDA bit of STATUS byte 0 which can be read by the microcontroller This pin should be connected directly to SNUM 0 SBWS L3REF FIRST BYTE SBDA Fig 8 Position of first sub band serial PASC bytes in a tape frame in DPAP DPAR mode Preliminary specification SAA3323 the URDA pin of the SAA2003 URDA goes active as a result of a reset a mode change from mode DRAR to DPAP or if the SAA3323 has had to re synchronize with the incoming data from tape The position of the first sub band serial PASC bytes in a tape frame is shown in Figs 8 and 9 MGB384 byte 0 byte1 byte 2 SNUM 3 SBWS L3REF SBDA MGB385 byte 0 byte1 byte 2 Fig 9 Position of first sub band serial PASC bytes in a tape frame in DRAR mode May 1994 16 Philips Semiconductors Drive processor for DCC systems RAM connections The SAA3323 has been designed to operate with DRAMs and SRAMs Suitable DRAMs are 64K x 4 bit or 256K x 4 bit configurations operating in page mode with an access time of 80 to 100 ns The timing for read write and refresh cycles for DRAMs is shown in Figs 10 to 12 The timing for SRAMs is shown in Figs 13 to 19 For fast SRAMs these values are subject to verification during characterization in The conditions most critical at the required Vpp are shown in Table 14 Table 14 Fast SRAM conditions CO
51. tern selection register BIT 7 6 5 4 3 2 1 0 Meaning AEN ACHN3 3 ACHN2 3 ACHN1 2 ACHNO Default 0 0 0 0 0 Notes 1 AEN analog eye pattern output enable If this bit is LOW the Digital to Analog Converter DAC is switched off and the output is HIGH 2 ACHN3 to ACHNO select channel for analog eye output Table 29 ACHN3 to ACHNO channel selections for analog eye output CHANNEL ON ANAEYE O _ O O O O O JO O O 0O AUX T1sel register Table 30 T1SEL register CHTST1 pin selection register BIT 7 6 5 4 3 2 1 0 Meaning T1F2 T1F1 T1FO T1C3 T1C2 T1C1 T1CO CHANNEL ON CHTST1 k l Ol Ol O O O O 4 o o AUX 4 o o May 1994 34 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 Table 32 T1F2 to T1FO CHTST1 pin function selections FUNCTION OF CHTST1 PIN sliced data bit clock clock extraction frequency The digital eye pattern is in 8 bits two s complement notation the sliced data and the bit clock give the current binary state of the corresponding signals and the clock extraction frequency output is in 8 bits offset binary format The timing diagrams for the digital eye pattern output and the clock extraction frequency output are shown in Fig 29 T2sel register Table 33 T2SEL register CHTST2 pin selection register Se
52. th SRAM and when SRAM is being used they should be connected directly to the corresponding SRAM lO pins WEN OEN j tRAS A10 RAS AQ CAS tRaH lt AD to AS XI ROW ADDRESS N V COLUMN ADDRESS ICAC G j LEXY DO to DS ESV NIBBLE 0 DATA ES ANIBBLE 1 DATA La tRAC MGB386 Fig 10 DRAM read cycle timing May 1994 18 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 WEN OEN A10 RAS A9 CAS AO to A8 A 60MIN ADDRESS DO to D3 CABLE 2 DATA MGB387 tps Fig 11 DRAM write cycle timing WEN OEN A10 RAS A9 CAS Y A0to AS KERON ADDRESS DO to D3 MGB388 Fig 12 DRAM refresh cycle timing May 1994 19 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 WEN OEN ARAN L p BORRAR RRA OOOO AD t0 A16 A ADDRESS ADDRESS AR OS toHz PEOR Y ALLL IANA MAMPARAS ESA DO to D7 SSA SES gt H toLz MGB389 READ READ Fig 13 Fast SRAM read cycle timing La twp La twp WEN OEN TH 7 NSS SS A0 to A16 ORL RIESS SEREREK DO to D7 a a tay gt MGB390 tDH1 tOHz tDH2 WRITE READ MODIFY WRITE Fig 14 Fast SRAM write cycle timing RTim 00 May 1994 20 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA33
53. us The SAA3323 performs a new calculation to determine the duty factor of SPEED once every 21 33 ms giving a sampling rate of approximately 46 9 Hz This calculation is basically a phase comparison between the incoming Main Data tape frame and an internally generated reference The SPEED duty factor as a function of phase characteristic is shown in Fig 22 As shown the duty factor increases monotonously from approximately 9 when the incoming Main Data tape frame is 1 65 tape blocks 8 8 ms too early up to 91 when it is 1 65 tape blocks 8 8 ms too late Outside of a 2 tape blocks range the pulse width characteristic overflows and repeats itself forming a sawtooth pattern The SAA3323 has an internal buffer of 8 8 ms outside of which the phase information is invalid Table 20 POT and FOT deviation thresholds Fig 22 SPEED regulation duty factor as a function of phase characteristic 2 blocks 10 6 ms 0 1 65 blocks 8 8 ms If EnFReg is programmed HIGH then the above description is over ridden with frequency information If the incoming main data bit rate deviation from the nominal 96000 bits s rate is less than the Phase Only Threshold POT then the control is as described above in the phase control description If the deviation is more than the Frequency Only Threshold FOT then the SPEED information is gated with the phase information resulting in the SPEED signal being continuously HIGH or LOW while the c
54. ve processor for DCC systems SAA3323 SYMBOL PARAMETER CONDITIONS MIN Inputs outputs input capacitance load capacitance delay time from SLEEP HIGH to SLEEP active propagation delay time from falling edge of CLK24 delay time from SLEEP HIGH to SLEEP active set up time to falling edge of CLK24 hold time from falling edge of CLK24 propagation delay time from falling edge of CLK24 from rising edge of CLK24 delay time from SLEEP HIGH to SLEEP active set up time to falling edge of CLK24 hold time from falling edge of CLK24 propagation delay time from falling edge of CLK24 from rising edge of CLK24 delay time from SLEEP HIGH to SLEEP active set up time to rising edge of MCLK hold time from rising edge of MCLK propagation delay time from rising edge of MCLK from L83MODE SBWS delay time from SLEEP HIGH to SLEEP active set up time to rising edge of MCLK hold time from rising edge of MCLK toa propagation delay time from rising edge of SBMCLK 60 ns from rising edge of MCLK 55 ns 3 state control May 1994 48 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 SYMBOL PARAMETER CONDITIONS SBDA delay time from SLEEP HIGH to SLEEP active set up time to rising edge of MCLK hold time from rising edge of MCLK toa propagation delay time from rising 55 ns edge of MCLK
55. vice address can be sent by the microcontroller If L3MODE is HIGH then a data transfer may be occurring L3INT This pin carries interrupts from the digital equalizer module It can also be programmed to reflect the state of the AENV LABEL and VIRGIN signals May 1994 27 Preliminary specification SAA3323 Table 21 Timing values for Fig 23 SYMBOL TIME tw T tsu L3MODE th L3MODE tw1 gt 200 ns tat T tsu L3MODE th L3CLK tas 2 200 ns the T tsu L3CLK th L3MODE the 2 200 ns T tsu L3CLk ta L3DATA taz lt 250 ns 0 lt tas lt 50 ns T Lau T Lau T Lau T tsu L3CLK th L3CLK ten gt 200 ns L3CLK th L3cLk ten gt 200 ns L3DATA th L3CLK tsu1 200 ns L3CLK th L3DATA thi lt 35 ns 2 x T tsu L3MODE td L3DATA tag lt 250 ns T th ack td L3DATA th3 gt 50 ns 2 x T tsu L3CLK td L3DATA tag lt 410 ns 3 x T tsu L3CLK la L3DATA tag lt 575 ns Notes 1 2 T is the period of the master clock on the chip tua is the delay time between the last bit of a byte and first bit of the next byte if no halt is used Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA3323 L3MODE L3CLK La L3DATA DRP to microcontroller a L3MODE t t cL cH tno lt lt L3CLK tar thi j GH XK C NX NZ C XXNZ XX AD XL l
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