philips SAA2520 Stereo filter codec for MPEG layer 1 audio applications handbook
Contents
1. FS256 frequency is changed 12 288 11 2896 8 192 MHz FDIR is switching bit rate is changing system reset is active August 1993 11 MPEG CODED INTERFACE The interface that carries the MPEG coded signal uses the following signals The MPEG IPS interface SBWS bi directional word selection SBCL bi directional bit clock SBDA bi directional sub band coded data SBEF input error signal Operation is further controlled by SBDIR input direction of data flow URDA input unreliable encoded data signal The SBMCLK signal is the main frequency from which other clock signals are derived In encode mode this division is performed internally In decode mode the external source should provide SBWS and SBCL The frequency of the signal is equal to 1 32nd of the bit rate The frequency of the bit clock SBCL is twice that of the bit rate Some examples of the frequencies are given in Table 2 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 l aes SAA2520 audio applications Table 1 SAA2521 input output control FRESET output request a general reset of SAA2521 FDIR 1 for decoding and 0 for encoding mode common to S SYNCDAI pulse for synchronization of digital input output TDA1315 Table 2 Frequency examples BIT RATE SBWS FREQUENCY SBCL FREQUENCY k BITS s kHz kHz ENCODE MODE The following modes are supported Stereo or 2 channel mono2. SBCL SBWS SBDA Fig 15 Sub band S interface timing master mode SBCL SBWS and SBDA are output Notes to Fig 15 MEA645 2 T SBMCLK cycle time 120 to 205 ns 163 ns nominal tmH SBMCLK HIGH time gt 35 ns tmL SBMCLK LOW time gt 75 ns Te SBCL cycle time 384 kB s 8T ns nominal SBCL cycle time 256 kB s 12T ns nominal SBCL cycle time 192 kB s 16T ns nominal SBCL cycle time 128 kB s 24T ns nominal tou SBCL HIGH time 384 kB s gt 4T 20 ns SBCL HIGH time 256 kB s 2 gt 6T 20 ns SBCL HIGH time 192 kB s gt 8T 20 ns SBCL HIGH time 128 kB s gt 12T 20 ns teL SBCL LOW time 384 kB s gt 4T 20 ns SBCL LOW time 256 k Bs gt 6T 20 ns SBCL LOW time 192 kB s gt 8T 20 ns SBCL LOW time 128 kB s gt 12T 20 ns tp1 SBWS SBDA hold to SBCL LOW lt 20 ns tp2 SBCL LOW to SBWS SBDA valid lt 20 ns August 1993 18 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 l ae SAA2520 audio applications SBWS X a 9000009090000 AEK Tsc teL a teH 4 at SBCL tsut t thi p gt SBWS SBDA th SBEF MEA648 2 e tsu2 Fig 16 Sub band I S interface timing slave mode SBCL SBWS and SBDA are input Notes to Fig 16 Te SBCL cycle time see note 1 6 86T to 96T ns 8T ns nominal tcH SBCL HIGH time gt T 30ns to SBCL LOW time gt T 30ns ts1 SBWS SBDA input set up before SBCL HIGH gt
3. Fig 5 All essential information synchronization system information scale factors and encoded sub band samples are conveyed by incoming data Decoding is repeated for every frame August 1993 Preliminary specification SAA2520 After sync and coding information allocation data and the scale factors are used to correctly fill the scale factor array This is followed by a process of multiplication to provide de quantization and de scaling of the samples The decoded sub band samples which are represented in 24 bit two s complement notation are processed by the sub band filters and reconstituted into a single digital audio signal RESET Reset must be active under the following conditions 1 From system power up until CLK24 has executed more than 24 clock cycles 2 From the falling edge of PWRDWN for a period equivalent to 24 cycles of CLK24 oscillator start up time This is typically gt 1 ms however this value is crystal dependent PWRDWN A HIGH input applied to this pin will halt all internally generated clock signals As a result chip activity will halt completely with outputs frozen in the state which was current at the time of PWRDWN activation The bi directional outputs LTDATA FDAC FDAF SDA SBWS SBCL and SBDA will be 3 stated Crystal Oscillators A 24 576 MHz crystal together with some external components form the 24 576 MHz oscillator pins 42 and 43 Similarly a 22 5792 MHz oscillator
4. In the case of stereo encoding the channels are indicated by L left and R right This changes to and Il in the case of 2 channel mono encoding Be ieee BO R or Il channel sub band Lor 0 31 0 31 August 1993 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 l aes SAA2520 audio applications INTERNAL SETTINGS LTCNT1 LOGIC 1 LTNCT 0 LOGIC 0 The operation of the codec is controlled by the bits transferred in this mode Table 8 Internal Settings LTCNT1 logic 1 LTNCT 0 logic 0 name function valid in 15 12 bit rate index bit rate indication encode sample frequency 44 1 48 or 32 kHz indication encode decode 1 decode 0 encode encode decode EXT 256FS 1 external encode decode 0 internal 256FS 1 2 CH mono 0 stereo 2 channel mono encode MUTE 1 mute 0 no mute encode decode not used TrO to Tr1 transpare bits encode a Table 9 Internal Settings LTCNT1 logic 1 LTCNTO logic 0 bit rate 1 0 0 384 kbits s default value 0 0 0 256 kbits s 0 1 1 192 kbits s 0 0 128 kbits s The bit rate index indicates the bit rate of the encoded signal and is only effective in the encode mode The decode bit determines the operation mode of the SAA2520 The default value is logic 1 decoding mode EXT 256FS in the encoding mode determines whether or not the SAA2520 is
5. a 0 Q series resistor DC CHARACTERISTICS Tamb 40 to 85 C Vpp 3 8 to 5 5 V unless otherwise specified SYMBOL PARAMETER conpitions mm TYP MAX UNIT Supply Vpp supply voltage range 3 8 operating current Vpp 5 V note 1 Inputs URDA SBDIR SBEF LTCLK LTCNTO LTNCT1 X22IN X24IN operating current HIGH level input voltage 5 0 5 5 V 82 110 mA 58 80 mA LOW level input voltage input current V 0 3Vpp V 10 uA input current Inputs PWRDWN LTENA HIGH level input voltage LOW level input voltage input current August 1993 29 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 SAA2590 audio applications SYMBOL PARAMETER CONDITIONS Input RESET negative going threshold 0 a hystersis Vith Vini l input current Vi Vpp Tamb 25 C HIGH level output ise ace 2mA Vpp 0 5 aa gt for HIGH level output voltage lo 8 mA Vpp 0 5 e SeSS psu SBDA SBCL SBWS FDAF FDAC SCL SWS SDA LTDATA LOW evelinputvotage EO i ooo ee SBMCLK input current Input output FS256 Vou HIGH level output voltage lo 12 mA VoL LOW level output voltage lo 12 mA Output FS256 in 3 state HIGH level input voltage LOW level input voltage l input current Vi Vpp 40 Note 1 For load impedances representative of the application August 1
6. appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale August 1993 36
7. first soldering two diagonally opposite end leads Use only a low voltage soldering iron less than 24 V applied to the flat part of the lead Contact time must be limited to 10 seconds at up to 300 C When using a dedicated tool all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 eee SAA2520 audio applications DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development Preliminary specification This data sheet contains preliminary data supplementary data may be published later Product specification This data sheet contains final product specifications Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System IEC 134 Stress above one or more of the limiting values may cause permanent damage to the device These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied Exposure to limiting values for extended periods may affect device reliability Application information Where application information is given it is advisory and does not form part of the specification LIFE SUPPORT APPLICATIONS These products are not designed for use in life support
8. master or slave of the Filtered I S interface default is logic 0 master mode 2CH MONO is used in the encoding mode to determine whether the sub band signal is generated as a stereo or 2 channel mono signal Default value is logic 0 MUTE is used in both the encoding and decoding modes to mute the information to or from the Filtered I2S interface the default value is logic 0 August 1993 CH1 is utilized in the decoding mode to select one of the 2 channel mono signals to be decoded default is channel 1 A value of 0 results in channel 2 being decoded The transparent bits are copied in the sub band signal default is 00 The information from S15 to S10 S7 and S3 to SO will be copied into the sub band signal Philips Semiconductors Stereo filter and codec for MPEG layer 1 audio applications Table 10 Sample frequency indication Preliminary specification SAA2520 msb Isb sample frequency default value 0 44 1 kHz 1 48 kHz Before sending internal settings the microcontroller should check whether or not the SAA2520 is ready to receive However this does not apply for the transfer of internal settings to end a transfer of allocation information STATUS LTCNT LOGIC 1 LTNCTO LOGIC 1 Table 12 Status information 16 bit units function T12 bit rate index bit rate indication T10 sample frequency 44 1 48 or 32 kHz indication ready to receive 1 ready 0 not read
9. with allowable bit rates of 384 256 192 and 128 kbits s audio sampling frequencies of 48 44 1 and 32 kHz DECODE MODE The following modes are supported Stereo and joint stereo 2 channel mono and 1 channel mono with allowable bit rates in the range 448 to 32 k bits s audio sampling frequencies of 48 44 1 and 32 kHz August 1993 12 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 l ae SAA2520 audio applications FS256 SCL the SWS SDA FDAF FDAC FSYNC output a tqo gt tsu thi e SDA FDAF FDAC input MEA642 3 Fig 11 Filtered I S interface timing master mode FS256 SCL and SWS are input Notes to Fig 11 T FS256 cycle time fs 48 kHz 81 4 ns nominal FS256 cycle time fs 44 1 kHz 88 6 ns nominal FS256 cycle time fs 32 kHz 122 1 ns nominal Te SCL cycle time 4T ns nominal tH FS256 HIGH time fs 48 kHz gt 35ns FS256 HIGH time fs 44 1 kHz gt 38 ns FS256 HIGH time fs 32 kHz gt 35ns tie FS256 LOW time fs 48 kHz gt 35ns FS256 LOW time f 44 1 kHz gt 38 ns FS256 LOW time fs 32 kHz gt 75ns tsH SCL HIGH time gt 2T 20 ns ts SCL LOW time gt 2T 20 ns ts SDA FDAF FDAC input set up before FS256 HIGH gt 20 ns tu SDA FDAF FDAC input hold after FS256 HIGH gt 30 ns tHe SDA FDAF FDAC output hold after FS256 HIGH lt Ons tD1 2 FS256 HIGH to SCL SWS SDA FDAF FDAC output valid
10. 0 0 SAA25200 O INTEGRATED CIRCUITS DATA SHEET SAA2520 Stereo filter and codec for MPEG layer 1 audio applications Preliminary specification August 1993 File under Integrated Circuits IC01 Philips PHILIPS Semiconductors DH LI p Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications FEATURES Stereo filtering and codec functions in a single chip MPEG coded interface Filtered data interface Baseband audio data interface LT interface to microcontroller Clock generator Low operating voltage capability ORDERING INFORMATION SAA2520 GENERAL DESCRIPTION The SAA2520 performs the sub band filtering and audio frame codec functions to provide efficient audio compression decompression for MPEG 11172 3 Layer applications It is capable of functioning as a stand alone decoder but requires the addition of an adaptive masking threshold processor SAA2521 in order to function as a highly efficient encoder EXTENDED TYPE PACKAGE NUMBER PIN POSITION MATERIAL CODE SAA2520GP 44 QFP plastic SOT205AG Note 1 SOT205 1 1996 August 26 CLK24 X220UT X240UT CLK22 X22IN X24IN VDD Ge Gael gt SBDA FS256 CLOCK GENERATOR SAA2520 SUB BAND gt SBCL SERIAL INTERFACE gt SBWS SBDIR SBEF gt SBMCLK STEREO SUB BAND MUTEDAC FILTER PROCESSOR DEEMDAC ATTDAC SWS Bai FILTERED MICROPROCESSOR INTERFACE
11. 993 30 Philips Semiconductors Stereo filter and codec for MPEG layer 1 audio applications AC CHARACTERISTICS Tamb 40 to 85 C Vpp 3 8 to 5 5 V unless otherwise specified Preliminary specification SAA2520 SYMBOL PARAMETER UNIT input capacitance X24IN and X22IN crystal frequency at X22OUT CLK22 crystal frequency at X240UT CLK24 mutual conductance small signal gain feedback capacitance 5 pF output capacitance pF pF Co output capacitance Inputs URDA RESET LTDATA LTCLK LTENA LTCNTO LTCNT1 tub hold time to X241IN ns Outputs LTDATA MUTEDAC DEEMDAC ATTDAC SYNCDAI FDIR FRESET tg propagation delay from X24IN Inputs FDAF FDAC SDA SCL SWS setup time to FS256 hold time to FS256 FDAF FDAC SDA SCL SWS FSYNC propagation delay from FS256 neas SBDA SBCL SBWS URDA SBDIR SBEF setup time to SBMCLK hold time to SBMCLK 25 ns cup SBDA SBCL SBWS propagation delay from SBMCLK FS256 cycle time FS256 cycle time FS256 cycle time 32 kHz z SCL cycle time August 1993 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SYMBOL PARAMETER CONDITIONS SAA2520 FS256 master mode FS256 SCL and SWS are output FS256 HIGH time fs 48 kHz tH i tH FS256 HIGH time fs 44 1 kHz tiL FS256 LOW time fs 48 kH
12. INTERFACE amp CONTROL SDA Vss FDAF FRESET SYNCDAI LTCNTO LTCLK PWRDWN URDA FDAC FSYNC FDIR LTCNT1 LTENA LTDATA RESET Fig 1 Block diagram August 1993 Philips Semiconductors Stereo filter and codec for MPEG layer 1 audio applications X240UT X24IN X220UT X22IN CLK24 CLK22 Vss LTCNTI LTCNTO LTENA Q Q gt FS256 MUTEDAC DEEMDAC ATTDAC Vss URDA SBDIR SBDA SBCL SBWS SBEF 12 13 15 SBMCLK SYNCDAI FDIR FRESET FSYNC FDAF FDAC SCL SWS 20 SDA 21 PWRDWN 22 Fig 2 Pin configuration MLB126 Preliminary specification SAA2520 LTCLK LTDATA TO AUDIO AMPLIFIER p digital audio interface DAC control SAA2520 system micro interface power down MICROCONTROLLER reset MPEG interface Fig 3 MPEG decoder system data flow diagram MPEG source MLB127 August 1993 3 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 l aes SAA2520 audio applications PINNING SYMBOL PIN DESCRIPTION TYPE FS256 Filtered I2S clock 256 x sample frequency 12 mA 3 state output CMOS input with pull down MUTEDAC DAC control output expander DEEMDAC DAC control output expander DAC control output expander Vss supply ground 0 V unreliable drive processing data CMOS level SBDIR sub band IS direction SWBS SBCL SBDA CMOS level sub band I2S data 4 mA 3 state output CMO
13. MEA9PS E Fig 9 Transfer of FDAF and FDAC filtered data August 1993 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications channel L R L R L R L R L R L R L R SWS i FSYNC sub band r MBC148 1 Fig 10 SWS related to phase of FSYNC SAA2520 Baseband Interface Signals The interface between the SAA2520 and the baseband input output circuitry consists of the following signals SWS bi directional word channel select FS SCL bi directional bit clock 64FS SDA bi directional baseband data FDIR output decoding mode direction control The SWS signal indicates the channel of the sample signal either LEFT or RIGHT and is equal to the sampling frequency FS Operating at a frequency of 64 times that is used for sampling the bit clock dictates that each SWS period contains 64 SDA data bits Of these a maximum of 36 are used to transfer data samples may have a length up to 18 bits Samples are transferred most significant bit first Both SWS and SDA change state at the negative edge of SCL This baseband data is transferred between the SAA2520 and the input output using either Standard I S default or the alternative format shown in Fig 8 August 1993 10 Philips Semiconductors Stereo filter and codec for MPEG layer 1 audio applications Preliminary specification SAA2520 Interface between SAA2520 and SAA2521 cons
14. S input with pull down SBCL sub band I S bit clock 4 mA 3 state output CMOS input with pull down SBWS sub band 12S word select 4 mA 3 state output CMOS input with pull down SBEF SBMCLK w po OJO O oO ojlN 4 sub band IS byte error flag CMOS level sub band IS clock 6 144 MHz locked to FS256 8 mA 3 state output CMOS input with pull down ou hp FRESET reset signal for SAA2521 FSYNC Filtered I2S sync signal for SAA2521 FDAF Filtered I2S sub band filter data 4 mA 3 state output CMOS input with pull down FDAC Filtered I2S sub band codec data 4 mA 3 state output CMOS input with pull down SCL 12S bit clock 4 mA 3 state output CMOS input with pull down SWS I2S word select 4 mA 3 state output CMOS input with pull down SDA 21 12S baseband data filter 4 mA 3 state output CMOS input with pull down PWRDWN 22 power down mode CMOS level DSC4 23 test pin DSC3 24 test pin DSC2 2 test pin 5 DSC1 26 test pin Vpp 28 positive supply voltage 5 V 29 system reset CMOS level with pull down and hysteresis T1 30 test pin do not connect 31 test pin do not connect LTDATA LT interface data 4 mA 3 state output CMOS input with pull down LT interface bit clock CMOS level August 1993 4 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 l ae SAA2520 audio appl
15. T 30ns tH4 SBWS SBDA input hold after SBCL HIGH gt 30ns tse SBCL HIGH to SBEF valid lt T 30ns tue SBEF hold after SBCL HIGH gt 2T 30 ns Note 1 Minimum at bit rate 448 kB s Nominal at bit rate 384 kB s Maximum at bit rate 32 kB s August 1993 19 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 aes SAA2520 audio applications SBDIR tat ma t g2 HIGH Z HIGH Z SBCL fee Seles SBWS SBDA MEA647 1 Fig 17 Sub band I2S mode switch timing Notes to Fig 17 tp1 SBDIR HIGH to SBCL SBWS SBDA high impedance lt 50 ns tp2 SBCL SBWS SBDA after SBDIR LOW high impedance gt 240 ns August 1993 20 Philips Semiconductors Stereo filter and codec for MPEG layer 1 audio applications Microcontroller interface Preliminary specification SAA2520 The SAA2520 has an interface connection to the serial interface of a microcontroller The following signals are used LTCLK input bit clock LTDATA bi directional serial data LTCNTO input control line 0 LTCNT1 input control line 1 LTENA input enable The SAA2520 microcontroller interface is enabled only if LTENA pin 34 is logic 1 Information to or from the SAA2520 is conveyed in serial 8 or 16 bit units whilst the type of information is controlled by LTCNTO pin 35 and LTCNT1 pin 36 A transfer commences when the microcontroller sets the control lines to the correct combination for the required action LTENA is set t
16. ace LTENA 16 bits allocation scale factor information 16 bits allocation scale factor information LTCLKC T l l IT TT T ITT MLB132 Fig 19 The LTENA line must return to logic 0 between information transfers August 1993 26 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications LTENA ne LTCNTO 1 i Sa Pet thas A a A g kb yet gh toe yok YUU UU LTDATA ESR EE ese a bit 14 0 6 MLB133 9 11 13 15 1 3 5 7 Fig 20 Order of settings and status bits on the SAA2520 microcontroller interface SAA2520 LTENA LTENA must remain HIGH C ERA TE A ders ne cay ect ee Soe he ate ata amet wok ea A a asta LTCLK IL IL IL IL LTDATA OUTPUT 8 9 10 11 12 13 14 15 0123 4 5 6 7 MLB134 tpg delay LTCLK HIGH to LTDATA valid output for bit 0 in 16 bit transfers Fig 21 16 bit transfers August 1993 27 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 we t D5 lt t CL t CH lt tH4a LTCLK toa lt LTCDATA input LTCDATA output hiZ MLB135 Fig 22 Microcontroller interface timing Notes to Fig 22 teL LTENA LOW time gt 190 ns tcH LTCLK HIGH time gt 190 ns teL LTCLK LOW time 2190 ns tp1 LTENA HIGH to LTCLK HIGH 2 190 ns tp2 LTENA HIGH to LTDATA output low impedance 20ns tp3 LTENA HIGH to LTDATA ou
17. eheating duration 45 minutes at 45 C Wave soldering Wave soldering is not recommended for QFP packages This is because of the likelihood of solder bridging due to closely spaced leads and the possibility of incomplete solder penetration in multi lead devices August 1993 Preliminary specification SAA2520 If wave soldering cannot be avoided the following conditions must be observed e A double wave a turbulent wave with high upward pressure followed by a smooth laminar wave soldering technique should be used e The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners Even with these conditions do not consider wave soldering the following packages QFP52 SOT379 1 QFP100 SOT317 1 QFP100 SOT317 2 QFP100 SOT382 1 or QFP160 SOT322 1 During placement and before soldering the package must be fixed with a droplet of adhesive The adhesive can be applied by screen printing pin transfer or syringe dispensing The package can be soldered after the adhesive is cured Maximum permissible solder temperature is 260 C and maximum duration of package immersion in solder is 10 seconds if cooled to less than 150 C within 6 seconds Typical dwell time is 4 seconds at 250 C A mildly activated flux will eliminate the need for removal of corrosive residues in most applications Repairing soldered joints Fix the component by
18. ications SYMBOL DESCRIPTION TYPE LTENA LT interface enable CMOS level LTCNTO LT interface control CMOS level supply ground 0 V 22 5792 MHz buffered output CLK24 24 576 MHz buffered cup 22 5792 MHz crystal output 24 576 MHZ crystal input 24 576 MHz crystal output Vpp 44 positive supply voltage 5 V August 1993 5 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 SAA2520 audio applications ALLOCATION amp allocation information SCALE FACTOR and scale factor indices INFORMATION TABLE from SAA2521 SYNC AND CODING FORMATTER INFORMATION sub band MPE base band__ SUB BAND Samples SCALING amp APOT samples FILTER QUANTIZATION quantized samples DATA MLB128 Fig 4 Encoding mode sync coding CONTROL allocation SCALE FACTOR scale factor ARRAY MPEG amp ALLOCATION input DE data FORMATTER sub band samples quantized OUTPUT SUB BAND base band samples DEQUANTIZATION MULTIPLY CONTROL FILTER samples MLB129 Fig 5 Decoding mode August 1993 6 Philips Semiconductors Stereo filter and codec for MPEG layer 1 audio applications FUNCTIONAL DESCRIPTION Coding System MPEG coding achieves highly efficient digital encoding of audio signals by using an algorithm based on the characteristics of the human auditory system The broad band audio signal is split
19. ime after SBCL 2T 30 ns HIGH Notes 1 deviation from nominal frequency must be the same for X24 X22 and FS256 inputs to within 0 2 2 Minimum value for bit rate 448 kB s Typical value for bit rate 384 kB s Maximum value for bit rate 32 kB s August 1993 33 Philips Semiconductors Stereo filter and codec for MPEG layer 1 audio applications PACKAGE OUTLINE Preliminary specification QFP44 plastic quad flat package 44 leads lead length 2 35 mm body 14 x 14 x 2 2 mm SAA2520 SOT205 1 DIMENSIONS mm are the original dimensions detail X A UNIT max A1 A2 A3 bp 23 0 25 mm 2 60 21 Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES VERSION IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE SOT205 1 133E01A SEK 95 02 04 97 08 01 August 1993 34 Philips Semiconductors Stereo filter and codec for MPEG layer 1 audio applications SOLDERING Introduction There is no soldering method that is ideal for all IC packages Wave soldering is often preferred when through hole and surface mounted componen
20. into 32 sub band signals during encoding For each of the sub band signals the masking threshold is calculated The samples of the sub bands are incorporated in the signal with an accuracy that is determined by the signal to masking threshold ratio for that sub band During decoding the sub band signals are reconstructed and combined into a broadband audio signal The integrated filter processor performs the splitting encoding and joining decoding including the corresponding formatting functions For encoding a SAA2521 is necessary to calculate the masking threshold and required accuracy of the sub band samples Encoding See Fig 4 An encoding algorithm table is used during the coding process but due to the Adaptive Allocation functions of the SAA2521 this may change with every frame The table is therefore calculated for each frame by the SAA2521 and then transferred to the SAA2520 A frame contains 2 x 384 samples of Left and Right audio data This results in 12 samples per sub band 32 sub bands The samples of the greatest amplitude are used to determine the scale factor for a given sub band All samples are then scaled to represent a fraction of the greatest amplitude Once scaled the samples are quantized to reduce the number of bits to correspond with the allocation table as calculated by the SAA2521 Synchronization and coding information data is then added to result in a fully encoded MPEG signal Decoding See
21. is will occur in the following situations e with the loss of synchronisation e when in correct allocation information is received for two or more subsequent frames SBEF was HIGH e when the URDA input pin is HIGH In these situations the SAA2520 data output will be muted The SYNC bit will return to logic 1 as soon as the decoder is resynchronized to the incoming sub band data CLKOK indicates whether the 256FS clock corresponds to specified sample frequency The CLKOK bit is set to logic 1 after a change in sample frequency operation mode or EXT256FS setting It drops to logic 0 as soon as the 256FS clock deviates from the nominal frequency by more than approximately 0 2 Return to logic 1 will only occur automatically when the extended setting CLKOK hold mode is logic 0 The transparent bits are copied from the MPEG coded signal The EMPHASIS indication is as defined in the internal settings It can be used to apply the correct de emphasis Note the two bytes of the status are sampled at different moments so the information may not result from the same sub band frame August 1993 25 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 LTENA i ENN oie ee et ere gre ep ie eae i LTCLK if _ S LTDATA eS ie mccc 0 1 2 3 4 5 6 7 MLB131 Isb msb Fig 18 Transfer of data on SAA2520 microcontroller interf
22. ists of the following signals FILTERED I2S INTERFACE SWS bi directional word select common to 12S FS SCL bi directional bit clock common to 12S 64FS FDAC bi directional codec data FDAF bi directional filter data FSYNC output synchronization FS 32 Filtered data is transferred between SAA2520 filter codec functions and the SAA2521 using the format shown in Fig 9 The frequency of the SWS signal is equal to the sample frequency FS and the bit clock SCL is 64 times the sample frequency Each period of SWS contains 64 data bits 48 of which are used to transfer data The half period in which SWS is LOW is used to transfer the information of the LEFT channel while the following half period during which SWS is HIGH carries the data of the RIGHT channel The 24 bit samples are transferred most significant bit first This bit is transferred in the bit clock period with a 1 bit delay following the change in SWS Both SWS and FDAF FDAC change state at the negative edge of SCL The SAA2521 may be synchronized to the sub band codec using the FSYNC signal which defines the SWS period in which the samples of sub band 0 containing the lowest frequency components are transferred see Fig 10 SAA2521 AND INPUT OUTPUT MODE CONTROL The operation of SAA2521 and the input output circuitry is controlled by three signals shown in Table 1 FRESET and SYNCDAI are given whenever FS256 SCL and SWS outputs switch between high and low impedance
23. lt 50 ns August 1993 13 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 SAA2520 audio applications T tLe tH FS256 Lal tsL SCL a tht SDA FDAF FDAC FSYNC output tsu e the gt SWS SDA FDAF FDAC input MEA644 3 Fig 12 Filtered I S interface timing slave mode FS256 SCL and SWS are input Notes to Fig 12 try FS256 HIGH time gt 35ns tiL FS256 LOW time gt 35ns tsH SCL HIGH time gt T 35ns tsL SCL LOW time gt T 35ns tH4 SDA FDAF FDAC output hold after SCL HIGH gt 2T 15ns tp SCL HIGH to SDA FDAF FDAC output valid lt 3T 60 ns ts SDA FDAF FDAC input valid after SCL HIGH gt 20 ns tH2 SDA FDAF FDAC input hold after SCL HIGH gt T 20ns August 1993 14 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications FRESET f SAA2520 SYNCDAI ta2 tas 4 FDIR tga a E a tas HIGH Z HIGH Z SDA SDA td FDAF HIGH Z SWS HIGH Z FDAC FS256 aa as SCL tq7 gt tag tag HIGH Z EDAF HIGHZ SWS SS EpAG lt FS256 SCL MEA646 1 Fig 13 Mode switch timing Notes to Fig 13 tpo FRESET HIGH to SYNCDAI HIGH gt 300 ns tsH SYNCDAI HIGH time gt 1280 ns tot SYNCDAI LOW to FRESET LOW gt 790 ns tp2 FDIR hold to FRESET HIGH lt 20 ns tp3 FRESET HIGH to FDIR valid lt 20 n
24. nal Bits 0 and 16 are transferred in the bit clock period one bit time after the change in SBWS Both SBWS and SBDA change state during the negative edge of SBCL In decode mode a byte error flag SBEF is also transferred This occurs approximately in the middle of the corresponding byte byte 0 bits 0 to 7 byte 1 bits 8 to 15 etc Table 3 Modes and source signals Preliminary specification SAA2520 Encoding mode SBCL SBWS and SBDA are generated by the SAA2520 However if the SBDIR signal is logic 1 the output buffers are not enabled and these signals do not appear on the pins This mode is available to permit a change of operating mode whilst the bus signals are driven from an external source Decoding mode SBCL SBWS and SBDA are generated by an external source Table 3 contains a summary of the source signals in the various modes source of Mode FDIR SBDIR SBWS SBCL SBDA SBEF SBMCLK Encode Encode 1 Decode 1 1 EXT EXT EXT EXT INT Notes 1 During encoding the SBEF signal is don t care 2 Incoming data is not decoded The SAA2520 operates in the encoding mode and the data does not enter the interface 3 Operation is undefined The SAA2520 is in decoding mode whilst the SBWS SBCL and SBDA output drivers are enabled August 1993 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 SAA2520 audio applications SBMCLK
25. o logic 1 The SAA2520 determines its required action and prepares to transfer data When the microcontroller supplies the LTCLK data is transferred to or from the SAA2520 in units of 8 bits 16 bit transfers are conveyed as two 8 bit units during which LTENA remains high Table 4 Extended Settings During the transfer of 8 bit units the least significant bit is first to be transferred When 16 bit units are transferred the most significant byte is sent first EXTENDED SETTINGS LTCNT1 0 LTCNTO 0 Four information bits together with four address bits are transferred in this mode The order in which the bits appear on the interface is DO D1 D2 D3 A0 A1 A2 A3 BIT AO DESCRIPTION 0 CODEC external settings see Table 5 7 1 not used FUNCTION connected to DAC mute input 1 connected to DAC attenuation input D2 D3 HOLDCLKOK 0 selects CLKOK hold mode Note If not used for DAC control the MUTEDAC ATTDAC and DEEMDAC can be used as general purpose output expanders August 1993 21 Philips Semiconductors Stereo filter and codec for MPEG layer 1 audio applications Bits DO to D3 are copied directly to the corresponding output pins mode flip flop For HOLDCLKOK logic 1 When CLKOK drops it will remain LOW until set by an encode decode mode sample frequency external 256FS or bit rate index change Note 1 When DO logic 1 default 12S mode is selected F
26. or DO logic 0 the alternative mode is selected The setting of DO remains dormant until activated by the occurrence of FRESET ALLOCATION SCALE FACTOR INFORMATION LTCNT1 LOGIC 0 LTCNTO Loaic 1 For encoding the allocation and scale factor arrays can be filled using this mode To completely fill the allocation array 16 complete transfers of 16 bits are required After the first transfer of allocation information a check must be made to determine when the SAA2520 is ready to receive the remaining information This will ensure synchronization with the internal program of the SAA2520 Transfer of the allocation information is completed by sending the internal settings Table 6 Allocation information format Preliminary specification SAA2520 This is then followed by the scale factor information In the event that only internal settings information is sent then a default allocation of logic 0 will be assigned to all sub bands If in addition no internal settings are sent then the previous settings remain valid The allocation information is transferred in 4 bit units Each of these units contains the number of bits allocated to the sub band MINUS 1 except in the case of a logic 0 value which indicates that no bits are allocated to that sub band Scale factor information is transferred in units of 8 bits containing the 6 bit scale factor which is extended to 8 bits by adding two logic 0 s at the most significant end
27. pins 40 and 41 is formed by similar peripheral components together with an appropriate crystal see Fig 6 The component values shown apply only to crystals from the Philips 4322 156 series which exhibit an equivalent series resistance of lt 40 Q Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 F Ge E P X22IN 22 5792 o MHz Ci E pF X1 X220UT il R2 TS godin SAA2520 C3 33pF 24 576 R4 MHz No 1 MQ T X240UT R3 1 kQ my C4 33 pF MLB130 Component values apply only to crystals from the Philips 4322 156 series Fig 6 Crystal oscillator components channel SR left 32 bits ai right SWS i 1k 18 bits a 13 bits R bit 11141 4_ 0 00 1 1 1 1 2 7654 2 10 7 65 4 MSB LSB MSB MADE ae Fig 7 Transfer of SDA data Standard I S default format August 1993 8 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 SAA2520 audio applications channel ale left 32 bits ga right UU UU UU 18 bits 14 bits Eo rrr bit Sees LASERE 3 3 MSB LSB MSB MLA924 2 Fig 8 Transfer of SDA data alternative format channel sir left 32 bits FDAC a FDAF ji bit 22 2 2__ _ 0 0 0 222 2 3 2 1 0 2 1 0 3 2 1 0 MSB LSB MSB
28. s tp4 SDA change to high impedance after FRESET HIGH gt Ons lt 170ns tos SDA remains high impedance after FRESET LOW gt 0ns lt 170 ns tbe FDAF FDAC change to high impedance after FRESET HIGH lt 20 ns tp7 FDAF FDAC remain high impedance August 1993 15 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 SAA2520 audio applications Notes to Fig 13 after FRESET HIGH gt 460 ns tps FS256 SWS SCL change to high impedance before SYNCDAI HIGH gt 140 ns tpg FS256 SWS SCL remain HIGH impedance after SYNCDAI HIGH 2 140 ns i 32 bits SBCL IL U ULU UU UUUUUUU i x A te ee bleed D bit o 0 0 0___ 1 1 1 1 1 1 1 oA ote G2 2 2 0 1 2 8 01 23 4 5 6 7 8 9 0 1 2 MSB LSB MSB ini i si A a byte 0 byte 1 byte 2 MEA649 2 Fig 14 Transferring MPEG data to and from the SAA2520 August 1993 16 Philips Semiconductors Stereo filter and codec for MPEG layer 1 audio applications MPEG Coded Interface Sub band IS The MPEG coded data is transferred to and from the SAA2520 using the format shown in Fig 14 Each period of SBWS contains 64 data bits 32 of which are used to convey data The half period during which SBWS is logic 0 is used to transfer the first 16 bits 0 to 15 of a sub band slot The remaining half period during which SBWS is logic 1 carries the remaining 16 bits 16 to 31 Thus one period of SBWS corresponds with one slot of the sub band sig
29. tput valid lt 380 ns tp LTENA LOW to LTDATA high impedance lt 50 ns tua LTENA hold after LTCLK HIGH 2 355 ns tps LTCLK HIGH to LTENA HIGH 2 190 ns tpe LTCLK HIGH to LTDATA output valid for bit O see Fig 21 lt 355 ns for first bit in the second 8 bit unit lt 520 ns ts LTCNTO 1 set up before LTENA HIGH 2 190 ns tH LTCNTO 1 hold after LTENA HIGH 2 190 ns ts2 LTDATA set up before LTCLK HIGH 2 190 ns tue LTDATA input hold after LTCLK HIGH 230 ns tH LTDATA output hold after LTCLK HIGH 2145 ns tua LTENA hold after LTCLK HIGH gt 355 ns August 1993 28 Philips Semiconductors Stereo filter and codec for MPEG layer 1 Preliminary specification eins SAA2520 audio applications LIMITING VALUES In accordance with the Absolute Maximum System IEC 134 SYMBOL PARAMETER CONDITIONS MIN MAX UNIT supply voltage input voltage supply current from Vss 0 5 6 5 V 0 5 Vpp 0 5 V mA supply current in Vpp input current 160 160 10 mA 10 mA output current total power dissipation 20 20 880 storage temperature range operating ambient temperature range 55 150 85 electrostatic handling 40 1500 1500 Ves2 electrostatic handling note 3 70 70 V Notes 1 Input voltage should not exceed 6 5 V unless otherwise specified 2 Equivalent to discharging a 100 pF capacitor through a 1 5 KQ series resistor 3 Equivalent to discharging a 200 pF capacitor through
30. ts are mixed on one printed circuit board However wave soldering is not always suitable for surface mounted ICs or for printed circuits with high population densities In these situations reflow soldering is often used This text gives a very brief insight to a complex technology A more in depth account of soldering ICs can be found in our IC Package Databook order code 9398 652 90011 Reflow soldering Reflow soldering techniques are suitable for all QFP packages The choice of heating method may be influenced by larger plastic QFP packages 44 leads or more If infrared or vapour phase heating is used and the large packages are not absolutely dry less than 0 1 moisture content by weight vaporization of the small amount of moisture in them can cause cracking of the plastic body For more information refer to the Drypack chapter in our Quality Reference Handbook order code 9397 750 00192 Reflow soldering requires solder paste a suspension of fine solder particles flux and binding agent to be applied to the printed circuit board by screen printing stencilling or pressure syringe dispensing before package placement Several techniques exist for reflowing for example thermal conduction by heated belt Dwell times vary between 50 and 300 seconds depending on heating method Typical reflow temperatures range from 215 to 250 C Preheating is necessary to dry the paste and evaporate the binding agent Pr
31. y encode decode encode decode not used sub band signal mode indication encode decode encode decode synchronization indication decode 1 0 k 0 not o k T2 TrO to Tr1 transparent bits encode decode TO EMPHASIS emphasis indication The bit rate index indicates the bit rate of the sub band signal in units of 32 kbits s bit rate index 0000 indicates the free format condition bit rate 1111 is illegal and should not be found The coding of the sample frequency indication is equal to the one in the internal settings August 1993 24 encode decode encode decode Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 eee SAA2520 audio applications Table 13 MODE identification msb Isb mode output stereo LandR joint stereo L and R 2 channel mono or Il as selected 1 channel mono mono no selection Ready to receive indicates whether the SAA2520 is ready to receive allocation scale factor or internal setting transfers This should be checked in order to synchronize the transfer of such information In 2 channel mono decode mode the selected samples are transferred to both output channels The same occurs with all samples in 1 channel mono decode mode In both of these instances the L and R filter output channels are identical In decode mode the SYNC bit is logic 0 when the SAA2520 is unable to decode the sub band frames Th
32. z fL t FS256 LOW time fs 32 kHz tsH SCL HIGH time L S S t SCL LOW time SDA FDAF FDAC input setup time before FS256 HIGH SDA FDAF FDAC input hold time after FS256 HIGH SDA FDAF FDAC output hold time after FS256 HIGH FS256 HIGH to SCL SWS SDA FDAF FDAC output valid FS256 slave mode FS256 SCL and SWS are input thy FS256 HIGH time 35 tsH SCL HIGH time T 35 tut SDA FDAF FDAC output hold 2T 15 time after SCL HIGH SCL HIGH to SDA FDAF FDAC output valid SDA FDAF FDAC input hold time after SCL HIGH SDA FDAF FDAC input valid 0 ns after SCL HIGH T SBMCLK cycle time ns tmH SBMCLK HIGH time 35 tm SBMCLK LOW time 75 August 1993 32 ns Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 SYMBOL PARAMETER CONDITIONS MIN SBMCLK master mode SBCL SBWS and SBDA are output Te SBCL cycle time 256 kB s Te SBCL cycle time 128 kB s teH SBCL HIGH time 256 kB s teH SBCL HIGH time 128 kB s teL SBCL LOW time 256 kB s teL SBCL LOW time 128 kB s tp1 SBWS SBDA hold to SBCL LOW tp2 SBWS SBDA valid after SBCLO 20 ns Te SBCL cycle time note 2 6 86T 8T 96T ns ns SBWS SBDA setup time before SBCL HIGH SBWS SBDA hold time after SBCL HIGH ts2 delay before SBEF valid after SBCL T 30 ns HIGH tHe SBEF hold t
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