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philips SAA2500 MPEG Audio Source Decoder handbook

1. X22IN EN 22 5792 MHz 256fs or 384fs FSCLKIN FSCLKM control FCKENA L3 256fs or 384fs FSCLK lt FSCLK384 contiol 64f SCK lt fs WS lt 64 interfaces ki 0 use master input to input 1 use slave input MSEL1 MSELO L3 MGB491 Italics internal signal designation Fig 3 SAA2500 clock generator Crystal oscillator The recommended crystal oscillator configuration is shown in Fig 4 The specified component values only apply to crystals with a low equivalent series resistance of lt 40 Q September 1994 7 Philips Semiconductors MPEG Audio Source Decoder Preliminary specification SAA2500 X1 R1 SAA2500 C3 gt CA C1 C2 33 pF R1 R4 1 MO R2 R3 1 kO X1 22 5792 MHz X2 24 5760 MHz or 12 2880 MHz The specified component values only apply to crystals with a low equivalent series resistance of lt 40 O Fig 4 Crystal oscillator components MGB492 Clock frequencies when using the slave input If the slave input is used MSEL1 and MSEL0 10 or 11 the SAA2500 clock sources are MCLKIN and FSCLKIN and X22IN is not used The I2S clocks SCK and WS are generated by the SAA2500 from FSCLKIN FSCLKIN may be designated to have a freguency of 256 times indicated by FSCLK384 0 or 384 times indicated by FSCLK384 1 the sample freguenc
2. SLAVE SIGNAL MICROCONTROLLER DEVICE L3MODE output input L3CLK output input L3DATA output input input output Notes 1 L3MODE is used for the identification of the operation mode 2 L3CLK is the bitclock to which the information transfer will be synchronized 3 L3DATA will carry the information to be transferred September 1994 31 Preliminary specification SAA2500 All slave devices in the system can be addressed using a 6 bit address This allows for up to 63 different slave devices as the all O address is reserved for special purposes In addition it is possible to extend the number of addressable devices using extended addressing In operation 2 modes can be identified 1 Addressing mode AM During addressing mode a single byte is sent by the microcontroller This byte consists of 2 data operation mode DOM bits and 6 operational address OA bits Each of the slave devices evaluates the operational address Only the device that has been issued the same operational address will become active during the following data mode The operation to be executed during the data mode is indicated by the two data operation mode bits Data mode DM During data mode information is transferred between microcontroller and slave device The transfer direction may be from microcontroller to slave write or from slave to microcontroller read However during one data mode the transfer direc
3. MPEG Audio Source Decoder SAA2500 INPUT DATA FRAME HEADER ITEMS Information about the input data derived by the SAA2500 from the input data frame headers may be read from the frame header items Both the frame header bytes decoded from the input bitstream and the header bytes used for the actual decoding may be read The decoded frame header item is valid independent of the value of status flag INSYNC it e g shows the decoded headers while the SAA2500 is in the process of synchronising The used frame header item is only valid if status flag INSYNC is set The used header bytes are derived by the SAA2500 from the decoded header bytes by overruling NOPROT to 0 if settings bit CRCACT 1 and overruling detected errors Table 24 Decoded input data frame header item 3 bytes read only SUBSEGUENT BYTES 7 6 5 4 3 2 1 0 Decoded header SY3 1 sy2i1 SY1 1 SY0 1 ID LAY 1 8 LAYO 4 NOPR byte 1 Decoded header BR36 BR26 BR1 6 BRO 6 FS10 ESOU undefined undefined byte 2 Decoded header MOD18 MOD0 8 MODX169 MODXOM COPR ORIGO EMPH1 2 EMPHO 2 byte 3 Notes to Tables 24 and 25 SY3 to SYO last 4 bits of the synchronization word ID algorithm identification LAY1 layer Most Significant Bit MSB LAYO layer Least Significant Bit LSB NOPR CRC on header bit allocation and scale factor select information activity flag BR3 to BRO bit rate index FS1 a
4. RL 3 1 RL2 1 RL 1 1 RLO 1 APU coefficient RR 0 RR 6 0 RR 5 0 RR4 0 RR 3 0 RR 2 0 RR1 0 RR 0 0 Notes 1 LL 00000000 no attenuation in the left to left APU path 2 LR 01111111 infinite attenuation in the left to right APU path 3 RL 01111111 infinite attenuation in the right to left APU path 4 RR 00000000 no attenuation in the right to right APU path September 1994 30 Philips Semiconductors MPEG Audio Source Decoder APPENDIX Preliminary specification 3 line L3 interface INTRODUCTION The main purpose of the new interface definition is to define a protocol that allows for the transfer of control information and operational details between a microcontroller uC and a number of slave devices at a rate that exceeds other common interfaces but with a sufficient low complexity for application in consumer products It should be clearly noted that the current interface definition is intended for use in a single apparatus preferably restricted to a single printed circuit board The new interface reguires 3 signal lines apart from a return ground between the microcontroller and the slave devices from this the name L3 is derived These 3 lines are common to all ICs connected to the bus L3MODE L3DATA and L3CLK L3MODE and L3CLK are always driven by the microcontroller L3DATA is bidirectional Table 31 The 3 lines common to all ICs L3MODE L3CLK and L3DATA
5. slope CDSCL frequency ooh P slope effective input bit rate i d 2 Effective transferring characteristic example 3 Actual transferring characteristic of the first frame example time 1 The actual transferring characteristics of all frames are restricted to this area Fig 10 Slave input data transferring for the first frame The shaded area in Fig 10 represents the restrictions to the actual transferring characteristic of all frames The actual transferring characteristic may not undercut the effective transferring characteristic by more than B bits to avoid an input underflow On the other hand the actual transferring characteristic may not cross the shown upper limit of the shaded area to prevent an input buffer overflow The slope of this upper limit is determined by the maximum effective input bit rate depending on the input data format Table 9 summarizes the slopes as determined by the bit rates supported by ISO MPEG Table 9 Slopes determined by bit rates supported by ISO MPEG EFFECTIVE ISO MPEG INPUT BIT TRANSFERRING UPPER LIMIT LAYER BATE SLOPE kbits s kbits s ISO MPEG layer 13 3 to 448 448 ISO MPEG layer ll 3 50 to 384 384 Note 1 Achieved using the free format option and the minimum amount of the side information that must be transmitted this means using single channel mode no CRC and 32 kHz sample rate September 199
6. 0 _ fase e MHz fsck 64fs SCH FSCLK384 1 _ Ke MHz fsck 64fs September 1994 43 Philips Semiconductors Preliminary specification MPEG Audio Source Decoder SAA2500 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT Inputs Ci input capacitance _ _ 10 pF La set up time TI to SCK HIGH CL lt 25pF 33 _ ns tsu2 set up time CDM and CDMEF to CL lt 25pF 42 _ _ ns CDMCL CDS CDSEF and CDSWA HIGH tsu3 set up time CDSSY to CDSCL HIGH Tmt 10 _ ns tat delay time L3MODE to L3LCK LOW 0 ns Du hold time TI to SCK HIGH 0 _ _ ns the hold time CDM CDMEF to CDMCL 0 _ _ ns CDS CDSEF and CDSWA HIGH th3 hold time CDSSY to CDSCL HIGH 10 _ _ ns th4 input hold time 0 _ _ ns tL L3MODE LOW time Tmt 10 ns Outputs Co output capacitance 50 pF th hold time SD WS TO TB and TA to notes 3 and 4 22 _ _ ns SCK LOW th hold time CDMWS to CDMCL LOW notes 3 and 4 15 _ _ ns ta delay time SD WS TO TB and TAto note 3 _ _ 10 ns CDMCL LOW ta delay time CDMWS to CDMCL LOW note 3 _ _ 0 ns Inputs outputs Co output capacitance _ _ 50 pF tsu input set up time note 5 Tm 10 ns th input hold time note 5 10 ns th output hold time notes 3 and 5 Tm ns tg output delay time notes 3 and 5 2Tm 30 ns tao 3 state enable time notes 3 and 6 _ _ 20 ns ta3 3 state stable time notes 3 and 6
7. If FSCLKM 1 the configuration is comparable to the configuration when using the slave input see Section Clock freguencies when using the slave input MCLKIN and FSCLKIN are used as the clock sources and X22IN is not required MCLKIN may again have a freguency of 12 288 MHz indicated by MCLK24 0 or 24 576 MHz indicated by MCLK24 1 and FSCLKIN may have a frequency of 256 times indicated by FSCLK384 0 or 384 times indicated by FSCLK384 1 the sample freguency of the input data MCLKIN and FSCLKIN do not have to be phase or freguency locked Target applications applying the SAA2500 with 2 ISO MPEG sources In Table 2the three target applications of the SAA2500 are summarised The slave input application is labelled S and the master input applications are labelled MO and M1 Philips Semiconductors Preliminary specification MPEG Audio Source Decoder SAA2500 Table 2 Target applications APPLICATION ATTRIBUTE CONDITIONS s M0 M1 INPUT INTERFACE CONDITIONS SLAVE INPUT MASTER INPUT MASTER INPUT FSCLKM X 0 1 MCLKIN MCLK24 1 24 576 MHz 24 576 MHz 24 576 MHz MCLK24 0 12 288 MHz illegal 12 288 MHz X22IN note 1 22 579 MHz note 1 FSCLKIN FSCLK384 1 384f illegal 384f FSCLK384 0 256fs note 1 256f FSCLK FCKENA 1 L3 copy of FSCLKIN 256fs copy of FSCLKIN Remarks note 2 note 3 S Notes 1 Must be electrically defined eg LOW 2 FSCLKIN must be locked to inp
8. The word select signal WS indicates the channel of the output samples LOW if left HIGH if right WS is used for the subband filter interface as well If indicated in the coded input data de emphasis filtering is performed digitally on the output data thus avoiding the need of analog de emphasis filter circuitry The L3 control interface The SAA2500 uses the L3 protocol with the associated bus as the control interface with an optional host microcontroller see Chapter Appendix for more September 1994 information In the programming sections a general transfer protocol outline is presented In Section SAA2500 L3 protocol enhancement options several optional protocol enhancements are given which on the one hand are less transparent from the applicant s point of view but on the other hand increase the efficiency of the L3 interfacing L3 SIGNALS The L3 protocol uses 3 signals see Table 12 Table 12 Signals of L3 protocol SIGNAL DIRECTION FUNCTION L3DATA input output L3 interface serial data L3CLK input L3 interface bit clock L3MODE input L3 interface address data select The signals operate according to the L3 protocol description After each device reset the L3 interface of the SAA2500 must be initialised and as a conseguence the L3 interface cannot be used while the device reset signal is activated L3 TRANSFER TYPES The L3 protocol enables the reading and writing of cont
9. adhesive the component can be soldered The adhesive can be applied by screen printing pin transfer or syringe dispensing Maximum permissible solder temperature is 260 C and maximum duration of package immersion in solder bath is 10 s if allowed to cool to less than 150 C within 6 s Typical dwell time is 4 s at 250 C A modified wave soldering technigue is recommended using two solder waves dual wave in which a turbulent wave with high upward pressure is followed by a smooth laminar wave Using a mildly activated flux eliminates the need for removal of corrosive residues in most applications BY SOLDER PASTE REFLOW Reflow soldering reguires the solder paste a suspension of fine solder particles flux and binding agent to be DEFINITIONS Preliminary specification SAA2500 applied to the substrate by screen printing stencilling or pressure syringe dispensing before device placement Several technigues exist for reflowing for example thermal conduction by heated belt infrared and vapour phase reflow Dwell times vary between 50 and 300 s according to method Typical reflow temperatures range from 215 to 250 C Preheating is necessary to dry the paste and evaporate the binding agent Preheating duration 45 min at 45 C REPAIRING SOLDERED JOINTS BY HAND HELD SOLDERING IRON OR PULSE HEATED SOLDER TOOL Fix the component by first soldering two diagonally opposite end pins Apply the heating tool to
10. 0 Table 4 Defaults master input bit rate Preliminary specification SAA2500 Master input bit rate selection As explained above the SAA2500 can be used to alternate between two applications one with the slave input and one with the master input When using the master input the SAA2500 should fetch data with the effective bit rate but cannot know what the bit rate of the input data is until it has established synchronisation To overcome this paradox the input requesting is done at the last selected bit rate After a device reset the master input bit rate selection defaults to the value indicated in Table 4 FSCLKM FSCLK384 DEFAULT MASTER INPUT FSCLKIN BIT RATE kbits s 0 X0 384 1 256 x 32 kHz 384 x 32 kHz 278 64 256 x 44 1 kHz 384 384 x 44 1 kHz 256 x 48 kHz 417 96 O O o 384 x 48 kHz Note 1 X don t care When FSCLKM O the default master input bit rate is 384 kbits s When FSCLKM 1 the SAA2500 uses signal FSCLKIN to derive the selected bit rate but it has no indication concerning the sample rate corresponding to FSCLKIN Therefore a bit rate of 384 kbits s is selected at an assumed sample rate of 44 1 KHz with other sample rates the bit rate changes proportionally The conseguence is that while the SAA2500 synchronises e g after a device reset the application must at least be able to supply at the given d
11. RNDO Notes 1 MSEL1 and MSELO these bits select the used input interface the input data format and the input synchronization type see Table 22 2 CRCACT automatic forced CRC activity a CRCACT 0 the SAA2500 uses the protection bit in the ISO MPEG frame header to determine the presence of the CRC b CRCACT 1 the SAA2500 assumes the CRC always to be present The protection bit in the used ISO MPEG frame header is forced to 0 3 MCKDIS buffered master clock MCLK disabling a MCKDIS 0 enable MCLK b MCKDIS 1 disable 3 state MCLK 4 FCKENA buffered 256f or 384f output signal FSCLK enabling a FCKENA 0 disable 3 sate FSCLK b FCKENA 1 enable FSCLK 5 SELCH2 with dual channel mode input data with other modes of input data don t care a SELCH2 0 select channel I b SELCH2 1 select channel Il 6 RND1 and RNDO these bits select the rounding of the baseband audio output samples see Table 23 Table 22 MSEL1 and MSELO MSEL1 MSELO USED INPUT INTERFACE INPUT SYNCHRONIZATION 0 0 master to ISO MPEG synchronization pattern 0 1 reserved reserved 1 0 slave to ISO MPEG synchronization pattern 1 1 slave to synchronization signal CDSSY Table 23 RND1 and RNDO RND1 RNDO OUTPUT SAMPLE ROUNDING LENGTH 0 0 16 bits 0 1 18 bits 1 0 20 bits 1 1 22 bits September 1994 27 Philips Semiconductors Preliminary specification
12. TCK 39 boundary scan test clock input September 1994 Philips Semiconductors Preliminary specification MPEG Audio Source Decoder SAA2500 SYMBOL PIN DESCRIPTION TYPE TMS 40 boundary scan test mode select input TDI 41 boundary scan test data input FSCLK384 42 sample rate clock freguency indication input FSCLKM 43 sample rate clock source selection for the master input MCLK24 44 master clock freguency indication S osen95e2asoda u uw F Et H k gt SS ISIS ISI IS e LS S els RESET TB FSCLK TI FSCLKIN TO MCLK ws Vpp SCK GND SEN GND MCLKOUT TA MCLKIN SD X220UT L3MODE X22IN L3DATA STOP L3CLK 6 8 o CDMWS CDMEF MGB490 ao J o u lt gt 2985 S BBS o ogo Fig 2 Pin configuration FUNCTIONAL DESCRIPTION Coding system The perceptual audio encoding decoding scheme defined within the ISO IEC 11172 3 MPEG Standard allows for a high reduction in the amount of data needed for digital audio whilst maintaining a high perceived sound quality The coding is based upon a psycho acoustic model of the human auditory system The coding scheme exploits the fact that the human ear does not perceive weak spectral components that are in the proximity both in time and frequency of loud components This phenomenon is called masking September 1994 For layers and II of ISO MPEG
13. _ _ 20 ns tas 3 state disable time L3DATA to note 3 _ _ 20 ns L3MODE LOW Notes 1 Short rise and fall times improve the tolerance of clocks to signal and supply noise 2 2 IfMCLK24 1 then T MCLKIN ger ei else Ta MCLKIN For maximum clock signal load of 25 pF L3DATA to L3CLK HIGH L3DATA to L3MODE HIGH September 1994 44 To allow for the effects of load capacitance the timing values should be de rated by 0 5 ns pF Philips Semiconductors Preliminary specification MPEG Audio Source Decoder SAA2500 50 DATA 70 OUTPUT 30 MGB511 Fig 23 Timing diagram September 1994 45 Philips Semiconductors Preliminary specification MPEG Audio Source Decoder SAA2500 PACKAGE OUTLINE seating plane x 0 85 0 75 1 8 1 65 0 25 A 0 25 1 7 0 05 0 14 i Y 4 Re 0 to 109 MBB944 2 detail X _ 0 95 Dimensions in mm Fig 24 Plastic quad flat package 44 leads lead length 1 3 mm body 10 x 10 x 1 75 mm QFP44 SOT307 2 September 1994 46 Philips Semiconductors MPEG Audio Source Decoder SOLDERING Plastic guad flat packs By WAVE During placement and before soldering the component must be fixed with a droplet of adhesive After curing the
14. i e status byte readings are performed Meanwhile LSMODE must be kept HIGH no L3 operational addresses may be written As a result L3RDY can be tested as shown in Table 37 Philips Semiconductors MPEG Audio Source Decoder Table 37 Status bytes DST1 and DSTO note 1 Preliminary specification SAA2500 TRANSFER L3DATA SOURCE L3MODE EXPLANATION 01100011 host 0 write read status operational address polled SAA2500 1 test L3DATA repeat this step until L3DATA 1 Note 1 No status byte transfers are needed the load of the host microcontroller can thus be reduced OPTIONS TO INCREASE THE TIMING ACCURACY OF THE APU COEFFICIENT WRITING The SAA2500 offers three enhancements to increase the timing accuracy with which APU coefficients can be updated by the application 1 Status polling is not reguired when APU coefficients are written L3 status flag L3RDY when read anyhow will always be HIGH indicating that the next APU coefficient transfer may be done The transfer speed is only limited by the maximum allowed freguency of L3CLK As a result also no write item data operational address is needed any more before writing each APU coefficient index Normally no more bytes may be written to a writeable data item than the length of that specific item An exception is formed by the APU coefficients They may be written continuously with a coefficient wrap After the writing of all 4 coefficie
15. inside the SAA2500 The incorporated Audio Processing Unit see Fig 5 can be used to apply inter channel crosstalk or independent volume control per channel The APU attenuation coefficients LL LR RL and RR may be changed dynamically by the host microcontroller writing their 8 bit indices to the SAA2500 over the L3 control bus The coefficient changes become effective within one sample period after the coefficient index writing To avoid clicks at coefficient changes the transition from the current attenuation to the next is smoothed The relation between the APU coefficient index and the actual coefficient i e the gain is given in Table 5 Philips Semiconductors MPEG Audio Source Decoder Table 5 APU coefficient index and actual coefficient APU COEFFICIENT INDEX C APU BINARY DECIMAL COEFFICIENT 00000000 to 00111111 0 to 63 C 2 12 01000000 to 01111110 64 to 126 _ C 32 2 6 01111111 127 0 1XXXXXXX 128 to 255 reserved left decoded gt left output audio gt audio samples D samples right decoded gt right output audio va p audio samples D samples MGB493 Fig 5 Audio Processing Unit APU Preliminary specification SAA2500 From Table 5 we learned that up to coefficient index 64 the step size is approximately 0 5 dB per coefficient increment and from coefficient index 64 to index 126 the step size is approximately 1 dB per increment Note that the APU has no bu
16. of the decoding process as well as the audio post processing features offered by the SAA2500 are described in more detail below Synchronization to input data bitstreams After a reset the SAA2500 mutes both sub band and baseband audio data After data inputting has started the SAA2500 searches either for a sync pattern or a sync pulse The speed at which input data is read by the master input to search for synchronisation is described below If the application is such that the SAA2500 starts at a random moment in time compared to the bitstream maximal one frame is skipped before a synchronisation pattern or pulse is encountered When the SAA2500 has detected the first synchronisation word or pulse a number of frames are decoded in order to verify synchronisation the input data for these frames is read and decoded but meanwhile the audio output is muted The number of muted frames depends on whether the ISO MPEG CRC is active and whether the bit rate is free format If the synchronisation is found to be false the SAA2500 resumes the initial synchronisation as described above If the detected pulse pattern is concluded to be a real synchronisation pulse pattern Table 3 indicates the number of muted frames Philips Semiconductors MPEG Audio Source Decoder Table 3 Muted frames MINIMUM NUMBER OF MUTED FRAMES DURING SYNCHRONIZATION CRC FREE FORMAT BIT NON FREE FORMAT RATE BIT RATE No CRC 2 1 CRC 1
17. the available 32 TO bits per sample per channel only 24 are used The MSB of a sample follows one SCK period after each transition in WS The 8 unused bits between individual samples in TO are zero SCK is used for the baseband audio output interface as well The optionally processed subband data signal is fed back as input TI in a similar format as TO but now the 8 unused bits between individual samples are undefined they are neglected by the SAA2500 Philips Semiconductors Preliminary specification MPEG Audio Source Decoder SAA2500 A leading edge in signal TB indicates the start of each TO index of the TI samples must be synchronised to TB a frame The length of each TB pulse is one sample period subband 0 sample pair must be input when TB is HIGH as TB is HIGH during a S 0 L and S 0 R pair Signal TA shown in Fig 12 This means that the delay of the external being HIGH indicates muting of TO due to input data errors processing is allowed to be any integer multiple of see Fig 13 32 sample periods If no external processing is to be TA can only change value at each TB leading edge i e applic TO MUSI PO input BACK diraciy ToT after each 384 sample periods ISO MPEG layer I input data or 1152 sample periods ISO MPEG layer II input data only whole frames are marked to be correct or The decoded baseband audio data is output in an I2S like muted As shown in detail in Fig 13 transitions of TB and format see Fig 14 TA t
18. will be an active partner for the microcontroller in the following data transfer mode During the data transfer mode bytes will be sent from or to the microcontroller In this example the L3MODE line is made LOW halt mode in between byte transfers This is the default operation although some ICs may allow the L3MODE line to be kept HIGH This exception must be specified clearly in the IC documentation and such ICs must be able to communicate with microcontrollers that Addressing mode make L3MODE LOW in between transfers It is suggested that new designs only use bytes as basic data transfer units After the data transfer the microcontroller does not need to send a new address until a new data transfer is necessary Alternatively it may also send the special address 000000 to indicate the end of the data transfer operation TIMING REQUIREMENTS These are requirements for the slave devices designed according to the L3 interface definitions L3MODE L3CLK L3DATA thy ber tsu La the _ XX XU MGB507 Fig 19 Timing addressing mode September 1994 Philips Semiconductors Preliminary specification MPEG Audio Source Decoder SAA2500 Table 34 Requirements for timing addressing mode see Fig 19 SYMBOL PARAMETER REQUIREMENT UNIT tat L3CLK HIGH to L3CLK LOW delay time after L3MODE
19. 0 0 SAA250U OO INTEGRATED CIRCUITS DATA SHEET SAA2500 MPEG Audio Source Decoder Preliminary specification September 1994 File under Integrated Circuits ICO1 Philips Semiconductors PHILIPS Philips Semiconductors Preliminary specification MPEG Audio Source Decoder SAA2500 FEATURES APPLICATIONS Advanced error protection Cable and satellite digital radio decoders Video CD Integrated audio post processing for control of signal level and inter channel crosstalk e Compact Disc Interactive CD I e Demultiplexing of ancillary data in the input bitstream e Sold state audio e Automatic digital de emphasis of the decoded e Multimedia Personal Computer PC audio signal Separate master and slave inputs GENERAL DESCRIPTION Automatic sample freguency and bit rate switching in I master input mode The SAA2500 supports all audio modes joint stereo stereo single channel and dual channel bit rates and sample frequencies of ISO MPEG 1 layers I and II as standardized in ISO IEC 11172 3 Automatic synchronization of input and output interface clocks in master input mode Selectable audio output precision 16 18 20 or 22 bit Low power consumption ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION SAA2500H QFP44 Plastic quad flat package 44 leads lead length 1 3 mm SOT307 2 body 10 x 10 x 1 75 mm Note 1 When using IR reflow soldering it
20. 0 to 85 C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT Clocks Ci input capacitance _ _ 10 pF MCLKIN folk clock frequency MCLK24 1 24 576 MHz MCLK24 0 _ 12 288 MHz tr rise time 12 ns t fall time 12 ns ty HIGH time 12 ns tL LOW time 12 _ _ ns X22IN folk clock frequency 22 579 MHz tr rise time _ 12 _ ns t fall time _ 12 _ ns ty HIGH time 12 _ _ ns tL LOW time 12 _ _ ns FSCLKIN folk clock frequency FSCLK384 1 384f Hz FSCLK384 0 _ 256f _ Hz tr rise time note 1 5 ns tr fall time note 1 _ 5 _ ns ty HIGH time 12 ns tL LOW time 12 ns September 1994 42 Philips Semiconductors Preliminary specification MPEG Audio Source Decoder SAA2500 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT CDSCL folk clock frequency 768 kHz tr rise time note 1 12 ns tr fall time note 1 _ 12 _ ns tu HIGH time note 2 Tm 20 ns tL LOW time note 2 Tm 20 ns CDMCL folk clock frequency note 2 1 Hz BT m L3CLK tH HIGH time Ta 10 _ _ ns tL LOW time Tmr10 _ _ ns FSCLK folk clock frequency MSEL 00 _ fain gt MHz FSCLKM 0 fs 44 1 kHz MSEL 00 f MHz FSCLKM 0 SSC fs 48 kHz MSEL 00 _ f MHz FSCLKM 0 MAIN fs 32 kHz MCLK folk clock frequency MCLKIN MHz SCK folk clock frequency FSCLK384
21. 01 host 0 5 indicates read item data transfer DDDDDDDD SAA2500 1 6 read first item data byte 01100011 host 0 7 indicates read status transfer SSSSSSSS SAA2500 1 8 read status repeat step 8 until LSRDY 1 01100001 host 0 9 indicates read item data transfer DDDDDDDD SAA2500 1 10 read second item data byte Each data item has its own length in bytes It is allowed to transfer less bytes than the data item length skipping the last one or more bytes it is even allowed to transfer no bytes at all It is not allowed to transfer more bytes than the item length This restriction does not hold for the APU coefficient item After writing all APU coefficients i e after writing all APU coefficient item bytes they may be rewritten by continuing writing bytes to the APU coefficient item Writing more than the specified number of bytes to a writeable data item or writing bytes to a read only data item may cause the SAA2500 to malfunction The reading of a write only data item yields irrelevant data September 1994 26 Philips Semiconductors MPEG Audio Source Decoder SAA2500 SETTINGS ITEM The SAA2500 is configured with the SAA2500 settings The initial value of the SAA2500 settings after reset is all zeros Table 21 SAA2500 settings item 1 byte read write 7 6 5 4 Preliminary specification SAA2500 3 2 1 0 MSEL1 9 MSELO CRCACT MCKDISO FCKENA SELCH2 RND1
22. 2 SAA2500 IS DECODING FRAME n SAA2500 IS DECODING FRAME n 1 DST2 0 DST2 1 DST1 AND DST1 AND DST1AND DST1 AND DST1 AND DST1 AND DST1 AND DST1 AND DSTO 0 DSTO 1 DSTO 2 DSTO 3 DSTO 0 DSTO 1 DSTO 2 DSTO 3 not valid Ancillary Data item frame n 1 not valid _ _ _ frame header items frame n _ _ _ _ not valid error report BALOK frame n not valid _ _ _ not valid error report DECFM not valid frame n Notes 1 The Table shows following a The received Ancillary Data that was multiplexed in frame n 1 becomes valid after subprocess 0 of frame n and may be read during subprocesses 1 2 and 3 of frame n b The decoded and used frame headers for frame n become valid after subprocess 0 of frame n and may be read during subprocesses 1 2 and 3 of frame n c Flag BALOK for frame n in the error report item becomes valid after subprocess 1 of frame n and may be read during subprocesses 2 and 3 of frame n and subprocess 0 of frame n 1 d Flag DECFM for frame n in the error report item becomes valid after subprocess 2 of frame n and may be read during subprocesses 3 of frame n and 0 of frame n 1 DATA ITEMS Data can be transferred to or from the SAA2500 in data items This section describes the general protocol to accomplish item data transfer followed by the individual SAA2500 data items Optional enhancements on the general protocol are describe
23. 36 Reguirements for timing halt mode see Fig 21 SYMBOL PARAMETER REQUIREMENT UNIT tai L3CLK HIGH to L3CLK LOW delay time after L3MODE HIGH gt 190 ns tL L3MODE LOW time 2190 ns tho L3CLK hold time before LMODE LOW gt 190 ns Slave device to microcontroller tao L3DATA enable time after L3IMODE HIGH 0 lt tgo lt 50 ns tas L3DATA disable time after LGSMODE LOW 0 lt tas lt 50 ns SAA2500 L3 protocol enhancement options The L3 interface on the SAA2500 is limited in speed dictated both by the maximum SAA2500 handling speed and the upper frequencies of the L3 interfacing standard On the other hand the SAA2500 offers several enhancements described in this section to make a better use of the SAA2500 L3 interface capacity The enhancements are optional The applicant chooses whether to use them or not TEsTING L3RDY BY POLLING L3DATA The host must test status flag LSRDY to make sure whether the SAA2500 L3 interface is ready to transfer data item bytes According to the general protocol described in Section Data items the status is read by first writing the September 1994 SAA2500 read status operational address after which the status byte can be transferred To avoid these status byte transfers thus reducing the host s load after writing the SAA2500 read status operational address L3RDY is continuously copied to signal L3IDATA during the period in which no L3 transfers
24. 4 17 SLAVE INPUT TRANSFER SPEED OF SUBSEQUENT FRAMES The SAA2500 starts decoding as soon as enough data of the first ISO MPEG input data frame has been received Thus the start moment of decoding depends on the actual transferring characteristic of the first frame Decoding start times of subseguent input data frames are also governed by this initial start time For this reason the transferring characteristic of all subseguent frames must approximate the characteristic of the first frame within the buffer margin B For the example shown in Fig 10 subseguent frames must be transferred within the shaded area shown in Fig 11 Philips Semiconductors MPEG Audio Source Decoder Preliminary specification SAA2500 transferred input frame bits ne MGB499 ie slope CDSCL freguency 3 y 1 1 wi Ce Sen B A slope effective input bit rate 2 d SE 2 Effective transferring characteristic example 1 The actual transferring characteristics of all subseguent frames are restricted to this area 3 Actual transferring characteristic of the first frame example Fig 11 Slave input data transferring for subseguent frames referenced to the first frame time gt Note that the actual transferring characteristics of all frames must also remain inside the shaded area The subband filter interface of Fig 11 As mentioned earlier decoded signals in th
25. ATA VALUES AFTER RESET Ata device reset the L3 interface initialisation procedure must be followed All writeable data items are pre loaded with a defined default value after the device reset signal has been de activated These default values are summarised in Table 29 Table 29 SAA2500 settings item default value after device reset notes 1 to 6 SUBSEGUENT BYTES 7 6 5 4 3 2 1 0 SAA2500 settings MSEL1 MSELO CRCACT MCKDIS FCKENA SELCH2 RND1 RNDO Value 0 0 0 0 0 0 0 0 Notes 1 MSEL1 0 and MSELO 0 the master input is selected The SAA2500 synchronizes to the ISO MPEG synchronization pattern na PON channels CRCACT 0 the SAA2500 uses the protection bit in the ISO MPEG frame header to determine if the CRC is active MCKDIS 0 the buffered master clock output MCLK is enabled FCKENA 0 the buffered 256f or 384f clock output is disabled SELCH2 0 when decoding input data with dual channel mode channel I is output on both baseband audio output 6 RND1 0 and RNDO 0 the baseband audio output signals are rounded to 16 bit Table 30 APU coefficients item default values after device reset SUBSEGUENT BYTES 7 6 5 4 3 2 1 0 APU coefficient LL 0 LL 6 0 LL5 0 LL4 0 LL3 0 LL2 0 LL1 0 LLO 0 APU coefficient LR 2 0 LR 6 1 LR5 1 LR4 1 LR 3 1 LR2 1 LR 1 1 LRO 1 APU coefficient RL 0 RL 6 1 RL 5 1 RL4 1
26. LOW 2190 ns tcL L3CLK LOW time gt 250 ns tcH L3CLK HIGH time gt 250 ns La L3DATA set up time before L3CLK HIGH 2190 ns thi L3DATA hold time after L3CLK HIGH 230 ns the L3CLK hold time before L3MODE HIGH 2190 ns Data mode th2 L3MODE SES L3CLK SH Ce L3DATA to IC L3DATA M SE TE TK XTX tga ker gt ths Le tas S tag 5 a aa MGB508 Fig 20 Timing data mode Table 35 Requirements for timing data mode see Fig 20 SYMBOL PARAMETER REQUIREMENT UNIT tai L3CLK HIGH to L3CLK LOW delay time after L3MODE HIGH gt 190 ns teL L3CLK LOW time 2250 ns tcH L3CLK HIGH time gt 250 ns Microcontroller to slave device La L3DATA set up time before L3CLK HIGH 2190 ns thi L3DATA hold time after L3CLK HIGH 230 ns tho L3CLK hold time before L3MODE HIGH 2190 ns Slave device to microcontroller tao L3DATA enable time after L3IMODE HIGH 0 lt tgo lt 50 ns ta3 L3DATA stable time after LIMODE HIGH 380 ns th3 L3DATA hold time after L3CLK HIGH 250 ns taa L3DATA stable time after LSCLK HIGH lt 360 ns Lou L3DATA stable time after L3CLK HIGH between bit 7 of a byte and 530 ns bit 0 of next byte if no halt mode is used tas L3DATA disable time after L3MODE LOW 0 lt tas lt 50 ns September 1994 36 Philips Semiconductors MPEG Audio Source Decoder Halt mode Preliminary specification SAA2500 L3MODE L3CLK L3DATA IC to microcontroller MGB509 Fig 21 Timing halt mode Table
27. PIA OSSA odd ovd SOE LOL wel6eip uomeoijdde jedidA 22614 Y0pauuo2 Ajddns eu 0 sojo po1e290J og pinoys syu GND pue A S abeyor Ajddns y 4 U p uqu 00150 3GOWST SOU 00SZVVS OneIS D3dW PBEMTOSA Wa OS adeyajul Jejseu 53dW mmm 9ScSd 13S3H 40 September 1994 Philips Semiconductors Preliminary specification MPEG Audio Source Decoder SAA2500 LIMITING VALUES In accordance with the Absolute Maximum Rating System IEC 134 SYMBOL PARAMETER CONDITIONS MIN MAX UNIT Vpp supply voltage 0 5 6 5 V Vi input voltage note 1 0 5 Vpp 0 5 V Jop supply current _ 100 mA li input current _ 10 mA lo output current 2 mA outputs _ 10 mA 4 mA outputs _ 20 mA Prot total power dissipation VDD 5 V 5 _ 165 mW Tstg storage temperature 65 4150 C Tamb operating ambient temperature 40 85 C Vest electrostatic handling note 2 2000 2000 V Ves2 electrostatic handling note 3 200 200 V Notes 1 Input voltage should not exceed 6 5 V unless otherwise specified 2 Equivalent to discharging a 100 pF capacitor through a 1 5 kQ series resistor 3 Equivalent to discharging a 200 pF capacitor through a 0 Q series resistor DC CHARACTERISTICS Vpp 5 V 10 Tamb 40 to 85 C unl
28. ake place one SCK period before a trailing edge of WS The optionally processed subband data TI must be synchronous to SCK and WS Furthermore the subband The baseband output interface The output interfacing consists of 3 signals see Table 11 384 layer I EE WER 3 4 1152 layer ll 1 2 1 H ws I 1 I 1 Fig 13 Filter data error flag TA timing September 1994 20 Philips Semiconductors MPEG Audio Source Decoder Preliminary specification SAA2500 SS SE 16 18 20 22 M valid data 0 CO AD ge sample LSB 16 18 20 22 err a Le MGB502 Fig 14 Baseband output data serial transfer format Table 11 Signals of output interfacing SIGNAL DIRECTION FUNCTION SD output baseband audio data SCK output data clock WS output word select The frequency of clock SCK is 64 times the sample frequency SCK is also used for the subband filter interface The signal SD is the serial baseband audio data sample by sample left right interleaved The left sample and the right immediately following it form one stereo pair 32 bits are transferred per sample per channel The samples are transmitted in two s complement MSB first The output samples are rounded to either 16 18 20 or 22 bit precision selectable by the host with L3 control interface flags RND1 and RNDO The remainder of the 32 transferred bits per sample per channel are zero
29. anging any of these 3 signals without simultaneously resetting the SAA2500 can result in malfunctioning Table 1 Clock interfacing signals SIGNAL DIRECTION FUNCTION MCLKIN input master clock oscillator input or signal input MCLKOUT output master clock oscillator output MCLK output master clock buffered signal MCLK24 input master clock freguency indication MCLK24 0 MCLKIN frequency is 12 288 MHz 256 x 48 kHz MCLK24 1 MCLKIN frequency is 24 576 MHz 512 x 48 kHz X22IN input 22 5792 MHz 512 x 44 1 kHz clock oscillator input or signal input X22OUT output 22 5792 MHz 512 x 44 1 kHz clock oscillator output FSCLKIN input sample rate clock signal input FSCLK output sample rate clock signal buffered signal FSCLK384 input sample rate clock signal freguency indication FSCLK384 0 FSCLKIN freguency is 256 times the sample rate FSCLK384 1 FSCLKIN frequency is 384 times the sample rate FSCLKM input sample rate clock source selection when using the master input FSCLKM 0 use MCLKIN or X22IN as source FSCLKM 1 use FSCLKIN as source September 1994 Philips Semiconductors Preliminary specification MPEG Audio Source Decoder SAA2500 control MCLK24 MCKDIS L3 MCLK in CONTROL out in DIVIDER internal master clocks MCLKIN MCLKOUT lt decoded sample rate index C 32 kHz 256f X220UT C 44 1 kHz
30. ata The SAA2500 can handle errors in the input data Errors are assumed to be present in 3 cases 1 If errors are indicated with the coded input data error flag CDSEF and or CDMEF 2 On CRC failure if ISO MPEG error protection is active 3 If input bitstream syntax errors are detected Errors in the input data have an effect on the decoding process if the corrupted data is inside the header bit September 1994 11 Preliminary specification SAA2500 allocation or scale factor select information field in a frame then the SAA2500 will mute or inside the scale factor field then the previous scale factor will be copied Errors in other data fields are not handled explicitly If the ISO MPEG CRC is active only the CRC result is interpreted CDSEF CDMEF un reliability indications for bit allocation and scale factor select information are neglected In applications where the ISO MPEG CRC is always present the protection bit which itself is not protected in the ISO MPEG header may be overruled by making L3 settings flag CRCACT HIGH In this manner the SAA2500 is made robust for data errors on the protection bit Subband filter signals The decoded subband signals are output so that they can be processed The optionally processed subband signals are put back into the SAA2500 for synthesis filtering Baseband audio processing The baseband audio de emphasis as indicated in the ISO MPEG input data is performed digitally
31. coded data slave input error flag CDSCL input coded data slave input clock CDSWA input coded data slave input burst windowing signal CDSSY input coded data slave input frame sync frame start NUN DDN cs ny ling lm xl sas TT IL DL eo es TE TA MO L T hal CDSWA i CDSSY S CDSEF 1 unreliable data bit example k MGB496 m valid data valid but unreliable data z invalid data CDSSY indicates frame start during valid data Fig 8 Input data serial transfer format slave input CDS is the SAA2500 input data bitstream Data clock CDSCL must have a frequency equal to or higher than the bit rate The maximum CDSCL frequency is 768 kHz Error flag CDSEF is handled in the same way as CDMEF is handled for the master input in Fig 8 one unreliable data bit is shown as an example The value of CDSEF is neglected for those bits where CDSWA is LOW Window signal CDSWA being HIGH indicates valid data in this way burst input data is allowed The constraints for the ability to use burst signals are explained below Frame sync signal CDSSY indicates the start of each input data frame CDSSY is synchronous with CDSCL CDSSY may be present or not as described below The first valid CDS bit after a leading edge of CDSSY is interpreted to be the first frame bit September 1994 15 The minimum time for CDSSY to stay HIGH is one CDSCL period the maximum HIGH period is constrained by the reguirement that CDSSY must be LOW at least d
32. cy of 768 kHz Signal CDM carries the coded data in bursts of 16 valid bits Coded data input frames may only start either at the first or at the ninth bit of a 16 bit valid data burst i e only at a byte boundary The value of word select signal CDMWS is changed every time new input data is needed one CDMOL period after each transition in CDMWS 16 bits of valid data are read serially Assume N is the number of CDMCL periods between two transitions of CDMWS and R is the number of CDMCL periods to obtain the effective bit rate E in kbits s at a transferring data rate of 768 kbits s i e R 16 768 E The SAA2500 keeps N close to R but N can vary plus or minus two N e round R 2 round R 2 September 1994 14 Error flag CDMEF is used to indicate input data insecurities e g due to erratic channel behaviour In Fig 7 an example with one unreliable bit is shown The value of CDMEF may vary for each valid data bit but is combined by the SAA2500 for every group of 8 input bits THE CODED DATA SLAVE INPUT INTERFACE The coded data slave input interface signals are shown in Fig 8 The coded data master input interface consists of 5 signals see Table 8 Philips Semiconductors MPEG Audio Source Decoder Table 8 Signals of coded data slave input interface Preliminary specification SAA2500 SIGNAL DIRECTION FUNCTION CDS input ISO MPEG coded input data slave input CDSEF input
33. d in Chapter Appendix Section SAA2500 L3 protocol enhancement options General data items The data items of the SAA2500 are transferred i e read or written depending on whether the data item is of readable or writeable type in bytes A data item transfer is September 1994 25 Note that during subprocess 3 all data items can be read initiated by writing the corresponding type I control byte see Section L3 interface control to the SAA2500 The transfer of every subseguent item data byte must be preceded by reading the status until status flag L3RDY see Section SAA2500 status is HIGH L3RDY may be tested alternatively by polling L3DATA avoiding the need to transfer the whole status byte Status polling is not reguired while transferring the APU coefficients item Table 20 shows an example of how bytes DDDDDDDD of a 2 byte data item with the corresponding control byte CCCCCCCC can be read The writing of item data bytes occurs in a similar way Philips Semiconductors MPEG Audio Source Decoder Table 20 Example of a 2 byte data item Preliminary specification SAA2500 L3DATA Pa L3MODE EXPLANATION 01100010 host 0 1 indicates write control transfer CCCCCCCC host 1 2 write transfer initiating type l control byte 01100011 host 0 3 indicates read status transfer SSSSSSSS SAA2500 1 4 read status repeat step 4 until L3RDY 1 011000
34. dent I2S timing signals SCK and WS are generated from FSCLKIN These configurations will normally be used in applications with a fixed sample rate Should the sample rate change then the SAA2500 must be reset Philips Semiconductors MPEG Audio Source Decoder When using the master input with FSCLKM 0 the SAA2500 selects the active sample rate autonomously and generates the signals SCK and WS from its crystal clocks After a device reset the SAA2500 selects a sample rate of 44 1 KHz by default SCK and WS may and will only show phase or freguency changes in any of the following 3 situations 1 When the SAA2500 establishes synchronization with the coded data input bitstream 2 When the active input interface is changed from the master input with FSCLKM 0 to the slave input i e the timing source for the generation of SCK and WS is switched from the crystal clocks to FSCLKIN 3 When the active input interface is changed from the slave input to the master input with FSCLKM 0 i e the timing source for the generation of SCK and WS is switched from FSCLKIN to the crystal clocks the sample rate is set to the last selected sample rate that was used with the master input the last selected sample rate is memorised while using the slave input In all other cases SCK and WS keep on running without phase or freguency changes and the sample rate selection remains unchanged Handling of errors in the coded input d
35. e status message Special function operational address Operational address 000000 bit 2 to bit 7 is the special transfer the L3IMODE line is HIGH The L3CLK line is lowered 8 times during which the L3DATA line carries 8 bits The information is presented LSB first and remains function address and is used forthe L3 device reset as well as for the declaration and invalidation of the extended sab aa an Uh addressing Both will be explained in Sections Device The preferred basic data transfer unit is an 8 bit byte interface reset and Extended addressing Some implementations that are modifications of older Data mode In the data mode the microcontroller sends or receives circuits with 16 bit registers may use a basic unit of 16 bits transferred as 2 bytes with the most significant byte presented first No other basic data transfer unit is allowed information to or from the selected device During data September 1994 32 Philips Semiconductors MPEG Audio Source Decoder Halt mode Preliminary specification SAA2500 L3MODE am IE MGB504 Fig 17 Data transfer mode In between units the L3MODE line will be driven LOW by the microcontroller to indicate the completion of a basic unit transfer This is called halt mode HM During halt mode the L3CLK line remains HIGH to distinguish it from an addressing mode The halt mode allows an implementation of an interface module without a bi
36. e subband domain before synthesis filtering are available externally for processing The associated interface has an S like format see Fig 12 September 1994 18 Philips Semiconductors MPEG Audio Source Decoder Preliminary specification SAA2500 MSB left sample TO SCK WS am valid data z subband ws L TB LSB Fig 12 Filter data serial transfer format MSB right sample MGB500 The filter data interface uses 6 signals as shown in Table 10 Table 10 Signals of filter data interface Two subband samples one per channel are transmitted per sample period with output TO The transmission pattern of the samples S sb ch sb subband index ch channel is S 0 L S 0 RJ S 1 L S 1 R S 31 R S 0 L S 0 RJ etc Word select signal WS indicates the channel of each sample WS is also used for the baseband audio output interfacing The subband sample bit clock SCK has a freguency of 64 times the sample freguency The subband samples are September 1994 19 SIGNAL DIRECTION FUNCTION TO output filter data output TA output filter data error flag TI input filter data input optionally processed SCK output filter data output input common bit clock WS output filter data output input common word select TB output filter data output frame synchronization transmitted in 24 bit two s complement PCM form MSB first Thus of
37. efault bit rate the reguired number of frames plus one additional frame because of the random decoding start point in the input bitstream Buffers in the application must thus be chosen sufficiently large to prevent under or overflows The speed with which input data is reguested by the master input is changed by the SAA2500 in each of the following cases 1 When input synchronization is established after checking a number of frames and the bit rate index of the newly decoded bitstream indicates a different bit rate than that currently selected In this case the bit rate is adapted to the newly decoded index September 1994 10 2 When the active input interface is changed from the master to the slave input or the signal STOP is activated in these cases input reguesting stops 3 When the active input interface is changed from the slave to the master input or the signal STOP is deactivated the bit rate is set to the last selected master input bit rate the last selected master input bit rate is memorised while using the slave input In all other cases e g when the SAA2500 goes and stays out of synchronisation the data reguesting speed of the master input is maintained Sample rate selection When using the slave input or when using the master input with FSCLKM 1 the application must know the sample rate FSCLKIN must be applied which has a freguency which is a multiple of the sample rate the sample rate depen
38. elect information fail b BALOK 1 bit allocation or scale factor select information are correct and the CRC if active over header bit allocation and scale factor select information passes 2 DECFM frame skipping decoding indication a DECFM 0 the current input data frame is skipped and the corresponding baseband audio output frame is muted due to input data errors or inconsistencies However synchronization to the input data is maintained b DECFM lt 1 the current frame is decoded normally ANCILLARY DATA ITEM The last 54 bytes of each ISO MPEG frame which may carry Ancillary Data AD are buffered by the SAA2500 to be read by the host The subseguent Ancillary Data bytes are read in reversed order with respect to their order in the input data bitstream The first item data byte is the last frame byte in the input bitstream The Ancillary Data item is refilled at every frame The host must either Know or determine itself how many of the Ancillary Data bytes are valid per frame The Ancillary Data item only has significance if status flag INSYNC is set Table 27 Ancillary data item 54 bytes read only SUBSEQUENT BYTES 7 6 5 4 3 2 1 0 AD byte 1 to bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 AD byte 54 APU COEFFICIENTS ITEM The APU coefficients are set by writing their 8 bit indices to the 4 byte APU coefficient item Only the 7 LSBs are valid The MSB must be zero At a device res
39. er combinations of DOM1 and DOMO initiate data transfers for extended addressing EXTENDED ADDRESSING L3 Devices with a programmable address can be informed of their operational address using a special data transfer Philips Semiconductors MPEG Audio Source Decoder Operational address declaration For the declaration programming of the operational address of an L3 device with a secondary L3 identification code the following action is reguired 1 First the microcontroller must issue an L3 operational address 000000 special function address with DOM1 0 and DOMO 1 This combination defines the operational address declaration operation Next the microcontroller will start a data transfer mode in which it first sends the secondary L3 identification code for the device that is to be issued an operational address followed by a byte containing the operational address the DOM bits in this byte are don t cares 2 Next the microcontroller will start a data transfer mode in which it first sends the secondary L3 identification code for the device that is to be issued an operational address followed by a byte containing the operational address the DOM bits in this byte are don t cares A secondary L3 identification code is unigue for any design Devices of the same design have the same identification code of one or more bytes However special Table 33 Example of L3 devices notes 1 to 4 Preliminary specificatio
40. ess otherwise specified SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT Supply Jop guiescent supply current note 1 100 _ _ uA Inputs notes 2 and 3 Vin HIGH level input voltage CMOS 0 7Vpp _ Vpp V VIL LOW level input voltage CMOS 0 O 3Vpp IV VIH HIGH level input voltage TTL 2 _ Vpp V VIL LOW level input voltage TTL 0 0 8 V ViLH positive going threshold voltage CMOS _ _ 0 8Vpp V Schmitt trigger ViHL negative going threshold voltage 0 2Vpb _ _ V CMOS Schmitt trigger Vhys hysteresis voltage CMOS Schmitt 0 3Vpp V trigger lil input current _ _ 1 uA Dout pull up resistor 14 _ 140 ko September 1994 41 Philips Semiconductors Preliminary specification MPEG Audio Source Decoder SAA2500 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT Outputs Vou HIGH level output voltage lo 4mA Vpp 0 5 V VoL LOW level output voltage lo 4mA _ _ 0 5 V llozl 3 state off leakage current 5 uA Notes 1 TDI TMS TRST and L3DATA not driven TC0 and TC1 driven HIGH all other inputs driven LOW 2 Inputs TRST TCK TMS and TDI are TTL level compatible all other inputs are CMOS level compatible 3 Input TRST pin 38 should be connected to ground for normal operation and connected to Vpp for boundary scan testing AC CHARACTERISTICS Vpp 5 V 21096 Tamb 4
41. et indices LL and RR are set to 00000000 no attenuation and indices LR and RL to 01111111 infinite attenuation no crosstalk Table 28 APU coefficients item 4 bytes write only see note 1 SUBSEQUENT BYTES 7 6 5 4 3 2 1 0 APU coefficient LL 0 LL 6 LL 5 LL 4 LL 3 LL 2 LL 1 LL O APU coefficient LR 0 LR 6 LR 5 LR 4 LR 3 LR 2 LR 1 LR O APU coefficient RL 0 RL 6 RL 5 RL 4 RL 3 RL 2 RL 1 RL O APU coefficient RR 0 RR 6 RR 5 RR 4 RR 3 RR 2 RR 1 RR 0 Note 1 Multiple options are supplied by the SAA2500 to increase the timing accuracy of the APU coefficient writing see Section SAA2500 L3 protocol enhancement options September 1994 29 Philips Semiconductors MPEG Audio Source Decoder SPEED LIMITATIONS OF THE L3 INTERFACE When reading the status of or writing control bytes to the SAA2500 no status polling is necessary so the speed of these transfers is only limited by the maximum freguency of signal L3CLK and the timing constraints of the L3 protocol When reading or writing data item bytes status polling is necessary In addition to the speed limitation this poses the application must take precautions that individual data item bytes are transferred at an interval of at least 200 us Neither the status polling nor a minimum interval between transfers is reguired when transferring the APU coefficient item Preliminary specification SAA2500 DEFAULT ITEM D
42. g LOW again differs in various situations An unreliable data indication can be given to the SAA2500 by making signal URDA HIGH URDA like STOP mutes the subband signals and forces the SAA2500 out of synchronisation However in contrast to STOP master input data reguesting continues at the bit rate that was decoded before URDA became active The maximum response time to URDA is half a sample period Coded data interfaces The SAA2500 contains e A coded data master input interface e A coded data slave input interface THE CODED DATA MASTER INPUT INTERFACE When using the master input the SAA2500 reguests for input data With the master input the coded input data may not use the ISO MPEG free format bit rate The coded data master input interface consists of 4 signals see Fig 7 Philips Semiconductors MPEG Audio Source Decoder Table 7 Signals of coded data master input interface Preliminary specification SAA2500 CDMEF M valid data valid but unreliable data SIGNAL DIRECTION FUNCTION CDM input ISO MPEG coded input data master input CDMEF input coded data master input error flag CDMCL output coded data master input clock CDMWS output coded data master input word select 2 16 17 n 1 2 1 unreliable data bit example MGB495 OA invalid data Fig 7 Input data serial transfer format master input Data clock CDMCL is being output having a fixed freguen
43. gher frequency than the bit rate CDSWA and CDSSY may be interconnected SLAVE INPUT TRANSFER SPEED OF FIRST FRAME Both the average and the instantaneous speed at which data is transferred to the slave input interface are limited The data transferring of the first ISO MPEG frame after starting to decode is shown in Fig 10 September 1994 It shows the transferring of nf bits in one frame between time 0 and t where t corresponds to 384 sample periods ISO MPEG layer I input data or 1152 sample periods ISO MPEG layer II input data Buffer margin B equals 16 bytes 128 bits In Fig 10 an effective transferring characteristic is drawn representing any of the possible ISO MPEG bit rates However input data may be transferred at a higher than effective speed in other words CDSCL may have a higher frequency than the effective bit rate in periods during which CDSWA is HIGH interleaved with invalid data periods where CDSWA is LOW In the example of Fig 9 this is used to transfer the data of the frame in two bursts as shown by the actual transferring characteristic The actual transferring characteristic has a slope equal to the CDSCL frequency while CDSWA is HIGH and is horizontal during the periods in which CDSWA is LOW no bits are being transferred Philips Semiconductors MPEG Audio Source Decoder Preliminary specification SAA2500 transferred input frame bits slope maximum input bit rate n MGB498
44. ilt in overflow protection so the application must take care that the output signals of the APU cannot exceed 0 dB level For an update of the APU coefficients it may be reguired to increase some of the coefficients and decrease some others The APU coefficients are always written seguentially in the fixed seguence LL LR RL and RR Therefore to prevent internal APU data overflow due to non simultaneous coefficient updating the following steps can be followed 1 Write LL LR RL RR once but change only those coefficients that must decrease overwrite the coefficients that must increase with their old value so do not change these yet 2 Write LL LR RL RR again but now change those coefficients that must increase keeping the other coefficients unchanged The conseguence of this two pass coefficient updating is that the application must keep a shadow of the current APU coefficients the L3 APU coefficients data item is write only APU coefficient index 126 127 1 Step 0 5 dB per coefficient increment 2 Step 1 dB per coefficient increment MGB494 Y Fig 6 Relation between APU coefficient index and gain September 1994 Philips Semiconductors MPEG Audio Source Decoder Decoding control signals The decoding is performed by 3 signals as shown in Table 6 Table 6 Signals for decoding control SIGNAL DIRECTION FUNCTION RESET input reset SAA2500 to defa
45. indicated in Section Input data frame header items some of the readable data item bits only have significance if INSYNC 1 4 L3RDY is L3 interface ready indication a L3RDY 0 the L3 interface cannot perform a new item data transfer yet b L3RDY 1 the L3 interface is ready for the next item data transfer After a device reset L3RDY is cleared and will only become set after writing the first L3 control byte to the SAA2500 The value of L3RDY can be tested by polling signal LSDATA instead of transferring the whole status byte Table 18 Status bytes DST1 and DSTO DST1 DSTO FUNCTION 0 0 subprocess 0 reading Ancillary Data or decoding header 0 1 subprocess 1 decoding bit allocation or scale factor select information 1 0 subprocess 2 decoding scale factors 1 1 subprocess 3 decoding samples The DST1 and DSTO values in general do not have a determined duration However subprocess 3 takes at least a frame period when ISO MPEG layer I data is decoded and frame period when ISO MPEG layer II data is decoded Table 19 indicates the validity of the SAA2500 readable data items with respect to the decoding subprocess Reading of a data item in a period when it is not valid renders undefined data September 1994 24 Philips Semiconductors MPEG Audio Source Decoder Preliminary specification SAA2500 Table 19 Validity of SAA2500 readable data items with respect to the decoding subprocess notes 1 and
46. is recommended that the Drypack instructions in the Quality Reference Pocketbook order number 9398 510 34011 are followed Supply of this ISO IEC 11172 3 audio standard Layer I or layer ll compatible IC does not convey a licence nor imply a right under any patent or any Industrial or Intellectual Property Right to use this IC in any ready to use electronic product September 1994 2 Philips Semiconductors Preliminary specification MPEG Audio Source Decoder SAA2500 BLOCK DIAGRAM 5 z lt 0 5 S x pas a x x z x a lt B dede 38 8898 28 22 gt gt z Ss ss SQ PP 34323 o5 GRE YI TO a TDI TDO CLOCK DECODING RESET GENERATOR CONTROL S TCK TMS TRST CDS CDSEF SAA2500 CDSCL SYNTHESYS CDSWA DEQUANTI SUBBAND CDSSY SECH a Se dir PROCESSOR SCALING AND C PROCESSOR OUTPUT CDMEF PROCESSING CDMCL CDMWS GND GND GND Me TCO TC TA TB TO Ti SCK WS Fig 1 Functional block diagram September 1994 Philips Semiconductors Preliminary specification MPEG Audio Source Decoder SAA2500 PINNING SYMBOL PIN DESCRIPTION TYPE RESET 1 master reset FSCLK 2 sample rate clock buffered signal O FSCLKIN 3 sample rate clock input MCLK 4 master clock buffered signal O Vppi 5 supply voltage _ GND 6 supply ground _ MCLKOUT 7 master clock oscillator ou
47. n SAA2500 designs may have a range of identification codes one of which can be selected by a hardware solution to enable the connection of more than one device of the same design to the L3 interface It is also possible to use separate L3MODE lines for multiple devices of the same design but the same L3 identification code this also enables parallel programming of these devices Bit 0 of any identification code byte will indicate whether or not an additional byte follows Bit 0 0 no additional byte as part of the identification code Bit 0 1 additional byte follows With this the number of secondary L3 identification codes is theoretically unlimited The operational address for the programmable device is preferable in the range 111000 to 111111 However it is possible in a given application to issue any operational address that is not used to address primary L3 devices or other secondary L3 devices An example is given in Table 33 ADDRESSING MODE DATA MODE SECONDARY L3 IDENTIFICATION CODE OPERATIONAL SPECIAL ADDRESS ADDRESS BYTE 1 BYTE 2 BYTE 3 ONE BYTE 10000000 1XXXXXXX 1XXXXXXX OXXXXXXXX MMYYYYYY Notes 1 Bits are shown in the order they appear on L3DATA bit 0 first bit 7 last 2 X bit of the identification code 3 M DOM bit of operational address don t care 4 Y bit of the operational address Operational address invalidation In order to re allocate an operatio
48. nal address that has been allocated to a secondary L3 device it is possible to invalidate an operational address e First the microcontroller must issue an L3 operational address 000000 special function address with DOMI1 1 and DOMO 0 This combination defines the operational address invalidation operation e Next the microcontroller will start a data transfer mode in which it only sends the secondary L3 identification code for the device that will no longer be addressed From this September 1994 moment on the device will not be able to communicate with the microcontroller until it is issued a new operational address by an OA declaration it will enter a device interface reset condition Remark the combination of a special function address 000000 and DOM1 and DOMO equa to 1 is reserved for future applications Designs based on this specification will react with a device interface reset 34 Philips Semiconductors MPEG Audio Source Decoder EXAMPLE OF A DATA TRANSFER Preliminary specification SAA2500 1 L3CLK is triggered by LIMODE 2 For more details see Fig 20 L3MODE L3cLK 1 III III III TIM address e bed data data byte 3 address MGB506 Fig 18 Example of transfer of 4 bytes A data transfer starts when the microcontroller sends an address on the bus All ICs will evaluate this address but only the IC addressed
49. nd FSO sample rate index MOD1 and MODO mode MODX1 and MODXO mode extension 10 COPR copyright flag 11 ORIG original or home copy flag 12 EMPH1 and EMPHO audio de emphasis these bits are only meant to monitor the current de emphasis mode the corresponding de emphasis is performed by the SAA2500 automatically before the baseband audio signal is output Oo WORN Re OD DO 2 Table 25 Used input data frame header item 3 bytes read only SUBSEQUENT BYTES 7 6 5 4 3 2 1 0 Used header byte 1 1 1 1 1 1 1 LAYO NOPR Used header byte 2 BR3 BR2 BR1 BRO FS1 FS0 undefined undefined Used header byte 3 MOD1 MODO MODX1 MODX0 COPR ORIG EMPH1 EMPH0 ERROR REPORT ITEM The validity of bit allocation plus scale factor select information may be read from the error report item The error report item is only valid if status flag INSYNC is set September 1994 28 Philips Semiconductors Preliminary specification MPEG Audio Source Decoder SAA2500 Table 26 Error report item 1 byte read only SUBSEGUENT BYTES 7 6 5 4 3 2 1 0 Error report BALOK DECFMO undefined undefined undefined undefined undefined undefined Notes 1 BALOK bit allocation and scale factor select information validity indication a BALOK 0 bit allocation or scale factor select information are incorrect or the CRC if active over header bit allocation and scale factor s
50. nsfer in order to write APU coefficients to return to the interrupted transfer SAA2500 STATUS The host can check the status of the SAA2500 by reading the one byte status word After writing the SAA2500 read status operational address the status byte may be read an arbitrary number of times If status is read more than once it is updated by the SAA2500 between the individual readings The status flags of the SAA2500 have the definition as shown in Table 17 September 1994 Philips Semiconductors Preliminary specification MPEG Audio Source Decoder SAA2500 Table 17 Status flag definitions 7 6 5 4 3 2 1 0 DST2 1 DST1 1 DSTO undefined undefined undefined INSYNC 3 L3RDY 4 Notes 1 By interpreting DST2 to DSTO the host can synchronize to the input frame frequency and also determine at which moment which L3 data item is available to be read The value of DST2 to DSTO is only valid if flag INSYNC is set a DST2 is a modulo 2 frame counter i e DST2 inverts at the moment the decoding of a new frame is started DST2 enables to host to sample the decoding subprocess DST1 to DSTO less frequently meanwhile enabling the host to see if it missed a state b DST1 and DSTO values are explained in Table 18 2 INSYNC is synchronization indication a INSYNC 0 the SAA2500 is not synchronized to the input data b INSYNC 1 the SAA2500 is synchronized to the input data 3 As
51. nts the writing can be continued at the first APU coefficient without having to write a new control byte The data item transfer protocol described in Section Data items although transparent allows only for the reading or writing of data items from their first data byte onwards This approach can lead to situations where e g 54 Ancillary Data item bytes must all be read which takes at least 54 x 200 us 10 8 ms due to the interface speed limitations see Section Data items before the next data item can be transferred The SAA2500 enables September 1994 38 the writing of APU coefficients without having to wait for the current item transfer to finish In order to do so a running transfer can be interrupted by an APU coefficient write transfer and then be resumed with the continue current transfer control byte An item transfer may be interrupted at any time to write APU coefficients After the continue previous transfer control byte a operational address must always follow indicating the type of L3 transfer that will follow An APU coefficient write transfer itself cannot be interrupted The 3 mentioned options are all illustrated in Table 38 where a data item transfer is interrupted between the reading of the n and n 1 th data item byte Philips Semiconductors MPEG Audio Source Decoder Preliminary specification SAA2500 Table 38 Example of 3 options to increase the timing accuracy of
52. processor The detour can be used to process the decoded audio in the sub band domain The baseband audio samples reconstructed by the sub band filter bank can be processed before being output The decoding control block houses the L3 control interface and handles the response to external control signals The L3 control interface enables the application to Preliminary specification SAA2500 configure the SAA2500 to read its decoding status to read Ancillary Data and so on Several pins are reserved for Boundary Scan Test and Scan Test purposes SAA2500 clocks The SAA2500 clock interfacing is designed for application versatility lt consists of 10 signals see Table 1 From a functional point of view the clock generator inside the device can be represented as shown in Fig 3 As described above the SAA2500 incorporates a master input interface on which it reguests for coded input data itself as well as a slave input interface for an imposed coded data input bitstream The input interface is selected with flags MSELO and MSEL1 controlled via the L3 microcontroller interface Depending on the selected input interface only a limited number of the three possible input clocks MCLKIN X22IN and FSCLKIN is actually reguired The various clock options are selected with the 3 external control signals MCLK24 FSCLKM and FSCLK384 These control signals must be stationary while the device reset signal RESET is de activated ch
53. rol status and data In the L3 protocol the host first issues an 8 bit wide operational address on L3DATA while keeping L3MODE LOW All devices connected to the L3 bus read the operational address Next data transfers from or to the Philips Semiconductors MPEG Audio Source Decoder Preliminary specification SAA2500 host are done while keeping L3MODE HIGH The devices with an L3 operational address differing from the issued one must ignore these data transfers until the next operational address is issued Only the device with an address egual to the issued operational address performs the transfer The SAA2500 has the L3 operational address as shown in Table 13 Table 13 L3 operational address 7 6 5 1 0 0 1 1 0 DOM1 DOMOD Note 1 The Data Operation Mode bits DOM1 and DOMO determine the mode in which the SAA2500 L3 interface will stay until the next time an L3 operational address is issued see Table 14 Table 14 DOM1 and DOMO bits DOM1 DOMO TRANSFER TYPE 0 0 write item data 0 1 read item data 1 0 write control to SAA2500 1 1 read SAA2500 status Control bytes can be written to the SAA2500 Data is transferred to or from the SAA2500 in so called data items The items can be a readable or writeable type A data item transfer is initiated by writing the corresponding control byte to the SAA2500 first Next the item data itself i
54. rt appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale September 1994 A7
55. s transferred always as an integer number of bytes The status of the SAA2500 can be read via L3 The SAA2500 status flag L3RDY must be monitored before transferring data item bytes to avoid transferring bytes faster than the L3 interface of the SAA2500 can handle L3 INTERFACE INITIALISATION AT AN SAA2500 DEVICE RESET Figure 15 shows the mandatory actions that must be taken for correct L3 interface start up at a device reset 1 RESET L3MODE Fig 15 L3 interface initialisation procedure 2 3 MGB503 September 1994 22 Philips Semiconductors MPEG Audio Source Decoder The actions shown in Fig 15 are 1 In order for the SAA2500 to keep L3DATA in 3 state L3MODE must be kept LOW during the whole period that reset signal RESET is asserted meanwhile no transfers can be performed L3CLK stays HIGH 2 For a proper initialisation of the L3 interface logic of the SAA2500 it is mandatory to make L3MODE HIGH and LOW again after the device reset has been de activated This must be done before any L3 transfer even to or from other devices than the SAA2500 is performed Figure 14 shows that L3CLK stays HIGH during this step 3 Now the first transfer can be performed on the L3 bus This transfer must be a operational address indicated in Fig 14 by L3MODE 0 addressing any of the devices connected to the L3 bus The first transfer to Table 15 L3 control Preliminary specification SAA2500
56. t counter However an implementation using a bit counter in the interface module may allow for the L3IMODE line to be kept HIGH in between units not using the halt mode This implementation must also operate correctly if the halt mode is used The documentation of the device will have to indicate clearly whether or not the halt mode is necessary for correct operation of the interface DEVICE INTERFACE RESET If the microcontroller sends an operational address 000000 with DOM1 and DOMO also equal to O this indicates that none of the L3 interface devices is allowed to communicate with the microcontroller during the following data mode This enables a different application of the L3CLK and L3DATA lines as the L3 devices will not September 1994 33 interfere with any communication on these lines as long as L3MODE remains HIGH e g the LSCLK and L3DATA lines are normally connected to USART circuits in the microcontrollers which allow for convenient communication between microcontrollers Any addressing mode with a valid L3 operational address will re enable the communication with the corresponding device Devices with a fixed operational address Primary L3 devices will react with a device reset condition regardless of the state of DOM1 and DOMO Devices with a programmable operational address Secondary L3 devices can only be put in the interface reset condition if the DOM1 and DOMO bits are 0 Oth
57. the APU coefficient writing L3DATA Ue EF L3MODE EXPLANATION DDDDDDDD SAA2500 1 read nth item data byte 01100010 host 0 indicate write control transfer 00000110 host 1 write write APU coefficients control byte 01100000 host 0 indicate write item data transfer DDDDDDDD host 1 write APU coefficient LL DDDDDDDD host 1 write APU coefficient LR DDDDDDDD host 1 write APU coefficient RL DDDDDDDD host 1 write APU coefficient RR DDDDDDDD host 1 write APU coefficient LL DDDDDDDD host 1 write APU coefficient LR DDDDDDDD host 1 write APU coefficient RL DDDDDDDD host 1 write APU coefficient RR 01100010 host 0 indicate write control transfer 00000111 host 1 write continue previous transfer control byte 01100011 host 0 indicate read status transfer SSSSSSSS SAA2500 1 read status repeat this step until LSRDY 1 01100001 host 0 indicate read item data transfer DDDDDDDD SAA2500 1 read n 1 h item data byte etc etc etc etc September 1994 39 Preliminary specification Philips Semiconductors SAA2500 MPEG Audio Source Decoder APPLICATION INFORMATION AS 0 S85W indino at ooL Ser VAL DI HI REI te ndo 301 Kl Wu mmm 4 IE o r 31001 9 Sp an T lt Eep AS ASS a ONIOSAS ou IW33d INTOSAS cz ZLS3L asnw aada awsa ass aSLV ZSMTO OA LSMTO Tolls viva HOI SM HOA
58. the SAA2500 itself must always be either the writing of a control word or the reading of the SAA2500 status the first transfer may never be a data item byte transfer Remark any deviation from these steps may result in illegal L3 protocol behaviour of the SAA2500 even with the possibility of disturbing transfers to other devices connected to the L3 bus L3 INTERFACE CONTROL The control of the SAA2500 L3 interface is performed with one byte control words Status polling is not necessary before writing control bytes After writing the SAA2500 write control operational address one or more control bytes may be written Each written control byte overrules the previously sent control byte 7 6 5 4 3 2 1 0 CTRL7 CTRL6 CTRL5 CTRL4 CTRL3 CTRL2 CTRL CTRLO The definitions of the control bytes CTRL7 to CTRLO are given in Table 16 Table 16 Explanation of control bytes CTRL7 TO CTRLO DEFINITION TYPE 00000000 read write SAA2500 settings item 00000001 read decoded frame header item 00000010 read used frame header item l 00000011 read error report item 00000100 reserved 00000101 read ancillary Data item 00000110 write APU coefficients item l 00000111 continue previous transfer C 00001000 to 11111111 reserved _ Note 1 Control bytes of type I initiate the transfer of a data item The control byte of type C may be used after interrupting a tra
59. the broadband audio signal spectrum is split into 32 sub bands of equal bandwidth For each sub band signal a masking threshold is calculated The sub band samples are then re quantized to such an accuracy that the spectral distribution of the re quantization noise does not exceed the masking threshold It is this reduction of representation accuracy which yields the data reduction The re quantized sub band signals are multiplexed together with ancillary information regarding the actual re quantization into a MPEG audio bitstream Philips Semiconductors MPEG Audio Source Decoder During decoding the SAA2500 de multiplexes the MPEG audio bitstream and with knowledge of the ancillary information reconstructs and combines the sub band signals into a broadband audio output signal Basic functionality From a functional point of view several blocks can be distinguished in the SAA2500 A clock generator section derives the internally and externally reguired clock signals from its clock inputs The SAA2500 can switch between a master and a slave input interface to receive the coded input data The input processor parses and de multiplexes the input data stream The de guantization and scaling processor performs the transformation and scaling operations on the sample representations in the input bitstream to yield sub band domain samples The sub band samples are transferred via an external detour to the synthesis sub band filter bank
60. the flat part of the pin only Contact time must be limited to 10 s at up to 300 C When using proper tools all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 C Pulse heated soldering is not recommended for SO packages For pulse heated solder tool resistance soldering of VSO packages solder is applied to the substrate by dipping or by an extra thick tin lead plating before package placement Data sheet status Objective specification This data sheet contains target or goal specifications for product development Preliminary specification This data sheet contains preliminary data supplementary data may be published later Product specification This data sheet contains final product specifications Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System IEC 134 Stress above one or more of the limiting values may cause permanent damage to the device These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied Exposure to limiting values for extended periods may affect device reliability Application information Where application information is given it is advisory and does not form part of the specification LIFE SUPPORT APPLICATIONS These products are not designed for use in life suppo
61. tion can not change Addressing mode In order to start an addressing mode the microcontroller will make the L3IMODE line LOW The L3CLK line is lowered 8 times and the DATA line will carry 8 bits The addressing mode is ended by making the L3MODE line HIGH Philips Semiconductors Preliminary specification MPEG Audio Source Decoder SAA2500 L3MODE J oT okt Reha seh MGB505 The meaning of the bits on L3DATA Bit 0 and bit 1 these are the data operation mode DOM bits that indicate the nature of the following data transfer Each slave device may have its own allocation of operation modes to the 4 possible codes of these bits For correct information about the operation the device will perform refer to the descriptions of the individual IC s For new designs the preferred allocations are given in Table 32 Bit 2 to bit 7 these bits act as 6 bit special function operational IC address with bit 7 as MSB and bit 2 as LSB Bit 7 to bit 5 act as system identification and bit 4 to bit 2 as identification of the device within the system Fig 16 Addressing mode Table 32 Preferred allocations DOM1 DOMO FUNCTION REMARKS 0 0 data from microcontroller to SAA2500 general purpose data transfer 0 1 data from SAA2500 to microcontroller general purpose data transfer 1 0 control from microcontroller to SAA2500 e g register selection for data transfer 1 1 status from SAA2500 to microcontroller short devic
62. tput O MCLKIN 8 master clock oscillator input or signal input X22OUT 9 22 579 MHz clock oscillator output O X22IN 10 22 579 MHz clock oscillator input or signal input STOP 11 stop decoding URDA 12 unreliable data input interrupt decoding CDMWS 13 coded data master input word select output O CDMEF 14 coded data master input error flag input CDM 15 ISO MPEG coded data master input l CDMCL 16 coded data master input bit clock output O GND 17 supply ground _ CDSCL 18 coded data slave input bit clock CDS 19 ISO MPEG coded data slave input CDSEF 20 coded data slave input error flag CDSWA 21 coded data slave input window signal CDSSY 22 coded data slave input frame sync L3CLK 23 L3 interface bit clock L3DATA 24 L3 interface serial data UO L3MODE 25 L3 interface address data select input SD 26 baseband audio I2S data output O TA 27 do not connect reserved O GND 28 supply ground _ SCK 29 baseband audio data I2S clock output O WS 30 baseband audio data I2S word select output O TO 31 connect to TI pin 32 O TI 32 connect to TO pin 31 TB 33 do not connect reserved O Vpp2 34 supply voltage _ TC1 35 do not connect factory test control 1 input with integrated pull down resistor TCO 36 do not connect factory test control 0 input with integrated pull down resistor TDO 37 boundary scan test data output O TRST 38 boundary scan test reset input this pin should be connected to ground for normal operation
63. ult state STOP input stop decoding URDA input unreliable input data interrupt decoding The master reset signal RESET forces the SAA2500 into its default state when HIGH RESET must stay HIGH during at least 24 MCLKIN periods if MCLKIN has frequency 24 MHz i e MCLK24 1 or 12 MCLKIN periods if MCLKIN has freguency 12 MHz MCLK24 0 At a reset the SAA2500 synchronization to the input bitstream is lost the subband filter and baseband audio output signals are muted and the SAA2500 settings are initialised The decoding can be stopped by making input signal STOP HIGH Stopping the decoding forces the SAA2500 to end decoding of input data yet feeding zeroed subband samples to the synthesis subband filter bank to create a soft muting When using the master input input reguesting is also stopped CDMWS stays in its current state while STOP is asserted The SAA2500 assumes the input synchronisation to be lost when the decoding is stopped September 1994 13 Preliminary specification SAA2500 thus causing re synchronization when STOP is de activated again Then the SAA2500 mutes meanwhile searching for a frame sync pattern or frame sync pulse the synchronisation mode is selected via the L3 control bus at the input If synchronisation is found the SAA2500 starts producing output data The maximum response time to the activation of signal STOP is half a sample period the re synchronisation time after STOP goin
64. uring one CDSCL period per frame a leading edge i e a frame start indication must be present every frame Leading edges of CDSSY can occur while CDSWA is HIGH as in Fig 8 Alternatively a situation as shown in Fig 9 is also allowed where CDSSY has a leading edge while CDSWA is LOW i e during invalid data The first CDS bit after CDSWA going HIGH is now interpreted to be the first frame bit Philips Semiconductors MPEG Audio Source Decoder Preliminary specification SAA2500 valid data ai invalid data CDSSY indicates frame start at next valid data frame start 003 ZZ ZC OC DN Fig 9 Input data serial transfer format slave input MGB497 Whether frame sync signal CDSSY is present or not must be selected with L3 settings flags MSEL1 and MSEL0 see Section SAA2500 settings item With respectto the presence of CDSSY two situations can be distinguished 1 If CDSSY is supplied CDSWA may change each CDSCL period 2 If CDSSY is not supplied CDSCL must have a frequency higher than the bit rate i e CDSWA cannot be continuously HIGH and CDSWA HIGH periods may have only lengths of a multiple of 8 CDSCL periods data is input in byte bursts Furthermore these bursts must be byte aligned with the frame bounds frames are only allowed to start at the 1st 9th 17th etc bit in a valid data burst For applications where data is input in bursts of exactly one frame and where CDSCL has a hi
65. ut data clock CDSCL see Section The coded data slave input interface 3 FSCLKIN is not used but FSCLK384 must be LOW Sections Clock freguencies when using the slave input and Clock freguencies when using the master input explain which clock sources are activated by the SAA2500 depending on the selected input interface This automatic clock source selection makes it easy to apply the SAA2500 in systems with two ISO MPEG coded data sources one connected to the master input an one to the slave input even if these data sources use different clocks Buffered clock outputs The SAA2500 provides a signal MCLK which is a buffered version of MCLKIN MCLK can be set to 3 state by setting the L3 control interface flag MCKDIS to 1 in applications where MCLK is not needed Signal FSCLK is copied from the FSCLKIN input for application types S and M1 or generated with a freguency of 256f by the SAA2500 for application type MO After a device reset FSCLK must be enabled explicitly by setting L3 flag FCKENA or can alternatively be left 3 stated in applications where it is not needed After a device reset MCLK is enabled FSCLK is disabled i e both MCKDIS and FCKENA are set to 0 Functionality issues The SAA2500 fully complies with ISO MPEG layer I and II with the slave input With the master input the SAA2500 complies with ISO MPEG layer I and II excluding the free September 1994 format bit rate Several aspects
66. y of the coded input data Master clock signal MCLKIN may be chosen to have a frequency of 12 288 MHz indicated by MCLK24 0 or 24 576 MHz indicated by MCLK24 1 MCLKIN and FSCLKIN do not have to be phase or freguency locked If the application is based on a sample freguency of 48 kHz or 32 kHz and a sample rate related clock of 12 288 MHz 256 x 48 kHz 384 x 32 KHz is available this can be taken advantage of by using this signal for both MCLKIN and FSCLKIN Clock freguencies when using the master input If the master input is used MSEL1 and MSELO 00 one out of two configurations is selected with signal FGCLKM with respect to the clock sources 1 If FSCLKM 0 MCLKIN and X22IN are the clock sources FSCLKIN is not used in this configuration FSCLK384 must be set to 0 for reasons of internal connections in the clock generator circuitry MCLKIN may have only freguency 24 576 MHz so mandatory accompanied by MCLK24 1 and X22IN must have a freguency of 22 5792 MHz MCLKIN and X22IN do not have to be phase or freguency locked The main September 1994 advantage of this configuration is that the SAA2500 determines automatically which sample rate is active from the sampling rate setting of the input data bitstream and then selects either MCLKIN or X22IN as the clock source for the I2S clocks SCK and WS This configuration is therefore particularly suited in applications with more than one possible sample rate setting 2

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