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philips SAA1575HL Global Positioning System (GPS) baseband processor handbook

1. A19 to A1 PMCS D15 to DO MHB475 Fig 16 External program memory read cycle non burst 1999 Jun 04 32 Philips Semiconductors Product specification Global Positioning System GPS 1575HL baseband processor SAA1575 A19 to A1 PMCS D15 to DO MHB476 taviv Fig 17 External program memory read cycle burst A19 to A1 DMCS D15 to DO MHB477 Default DMCS operation Fig 18 External data memory read cycle 1999 Jun 04 33 Philips Semiconductors Product specification Global Positioning System GPS baseband processor SAA1575HL tAVAU gt 24V 24V A19 to A1 04 V 0 4 V DMCS AVWL gt ja tWLWH tWHAU WRH 24V or WRL 0 4V tWHDH gt D15 to DO MHB478 tavay Default DMCS operation Fig 19 External data memory write cycle irFVsH sHEV SCLK 24V IF1 IF2 0 4 V MHB479 Fig 20 IF input timing 1999 Jun 04 34 Philips Semiconductors Product specification Global Positioning System GPS baseband processor SAA1575HL MHB480 Signal may be inverted under firmware control Fig 21 T1S output pulse timing 12 DEFAULT APPLICATION AND DEMONSTRATION BOARD VRTC VRTC RCLK RCLK VBB VBB SCLK SCLK BATT_ON BATT_ON SIGN SIGN BATT_OFF BATT OFF RFDATA RFDATA RFCLK RFCLK RFLE RFLE
2. 1 5 ko 2 Machine model C 200 pF L 0 75 uH R 0 Q 9 THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS VALUE UNIT Rih a thermal resistance from junction to ambient in free air 45 K W 1999 Jun 04 27 Philips Semiconductors Global Positioning System GPS baseband processor 10 DC CHARACTERISTICS Product specification SAA1575HL Vcc P Vcc B 25V VCCtcore Vcc R 3 V Tamb 20 C fose 30 MHz standard Philips firmware release HDOO note 1 unless otherwise specified SYMBOL PARAMETER CONDITIONS V c core core supply voltage Vcc P peripheral supply voltage backup peripheral supply voltage core supply current normal mode idle mode sleep mode normal mode note 2 idle mode sleep mode normal mode note 3 idle mode note 3 sleep mode note 3 normal mode note 2 idle mode sleep mode LOW level output voltage lot 2 0mA VoL VoH HIGH level output voltage ldrive max Maximum drive current C1 max maximum load capacitance tat transition delay Outputs HIGH drive current pins A19 to A1 LOW level output voltage lou 1 0mA VoL VoH HIGH level output voltage ldrive max Maximum drive current C1 max maximum load capacitance C 10 pF transition delay 1999 Jun 04 C 50 pF 28 Philips Semiconductors Product specification Global Positioning System GPS ba
3. LI SAA15HLI OO INTEGRATED CIRCUITS DATA SHEET SAA1575HL Global Positioning System GPS baseband processor Product specification 1999 Jun 04 Supersedes data of 1999 May 17 File under Integrated Circuits IC18 Philips PHILIPS Semiconductors DH l LI L Philips Semiconductors Product specification Global Positioning System GPS baseband processor SAA1575HL CONTENTS 1 FEATURES 2 GENERAL DESCRIPTION 3 QUICK REFERENCE DATA 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING 7 FUNCTIONAL DESCRIPTION 7 1 Overview 7 2 The 80C51 XA processor 7 3 The GPS correlators 7 4 Memory organization 7 4 1 Data memory space 7 4 2 Code memory space 7 5 CPU peripheral features 7 5 1 Timers counters 7 5 2 Watchdog timer 7 5 3 UARTs 7 5 4 RF IC programming port 7 5 5 General purpose I O 7 6 The real time clock 7 7 The external bus 7 7 1 Program memory chip select 7 7 2 Data memory chip select 7 7 3 Read strobe 7 7 4 Write LOW byte strobe 7 7 5 Write HIGH byte strobe 7 8 Backup supplies and reset 7 8 1 Supply domains 7 8 2 Power down design strategy 7 8 3 System reset control 7 8 4 Power saving modes 7 9 Clock signals and oscillators 7 9 1 System clock XTAL1 7 9 2 RTC clock XTAL3 7 9 3 Reference clock RCLK 1999 Jun 04 14 1 14 2 14 3 14 4 14 5 15 16 LIMITING VALUES THERMAL CHARACTERISTICS DC CHARACTERISTICS AC CHARACTERISTICS DEFAULT APPLICATION AND DEMONSTRATION BO
4. POWER DIGITAL RF SUPPLY PROCESSOR FRONT END MHB289 Fig 22 Overall schematic 1999 Jun 04 35 Philips Semiconductors Global Positioning System GPS baseband processor Product specification SAA1575HL Voc R207 gt D201 470 BAS16 U206 U207 ZM33064 ZM33164 Voc Voc R206 R205 10kQ 10kQ U204 PWRFAIL TP216 0 4 TP217 EWRDN 74 44 TP1 GND T 41 EMOS oTpai C207 TP215 o 3 XTAL1 DMCS GND H li 14 73 lap Sa lea 10PF L voi mawo XTAL2 b WRL La 0 TP229 0 F30MHz R204 WAH 1MG TP213 O XTAL3 45 o TP221 C208 R203 i 7S ap LAI GND 1 IL TP212 XTAL4 Ba 10 pF 1800 d H A3 C205 TxD0 A4 o Tx0 ono Fk TPoi ob a 34 AS 7PF vyaoa TP209 o 13D gi 33 AS 5 32 678 R202 TP208 o PD go 32 Ei kHz 10 MQ 8 29 TP4 C208 Rz01 V c 4 28 9 GND 11 ne tg 27 Ato 27 pF 99 DD 24 i V 23 TP230 co TP207 o 97 22 ae TESTI gg a A15 9JP201 5 TEST2 A16 JMP3 100 19 Faas JP202 TP2 n A18 GND 1 Vcc abi 10 A S 2 0 96 3 GPIO1 D0 95 70 i GPIO2 D1 94 69 5 GPIO3 D2 88 68 6 GPIO4 57 69 pa 2 GPIO7 ea 04 8 GPIO6 amp 05 GPIOS D6 9 7 62 D7 10 B5B
5. TIMERS COUNTERS Measure time intervals and pulse duration e Count external interrupts e Generate interrupt requests e Generate Pulse Width Modulation PWM or timed output waveforms The timers are used by the standard Philips firmware to generate the baud rates for the UART serial ports The additional features are not used in the standard Philips firmware but are available for use in custom firmware revisions All of the timers are configured in the 16 bit auto reload mode of operation Timer 1 is used to generate the baud rate for UARTO and Timer 2 is used to generate the baud rate for UART1 In the standard Philips firmware Timer 0 is not used 7 5 2 WATCHDOG TIMER The watchdog timer protects the system from incorrect code execution by causing a processor reset if the watchdog timer underflows as a result of a failure of the firmware to feed the timer prior to it reaching its terminal count In the standard Philips firmware the watchdog is enabled with a time out period of 130 ms at a clock frequency of 30 MHz 7 5 8 UARTS The SAA1575HL contains 2 UART ports compatible with the enhanced UART modes 1 to 3 on the 8xC51FB mode 0 operations not supported With the exception of the removal of the mode 0 operation the UARTs in the SAA1575HL are identical to those in the XA G3 product Each UART rate is determined by either a fixed division of the oscillator in UART mode 2 or by one of the timer overflow rates
6. Taiwan Philips Semiconductors 6F No 96 Chien Kuo N Rd Sec 1 TAIPEI Taiwan Tel 886 2 2134 2886 Fax 886 2 2134 2874 Thailand PHILIPS ELECTRONICS THAILAND Ltd 209 2 Sanpavuth Bangna Road Prakanong BANGKOK 10260 Tel 66 2 745 4090 Fax 66 2 398 0793 Turkey Yukari Dudullu Org San Blg 2 Cad Nr 28 81260 Umraniye ISTANBUL Tel 90 216 522 1500 Fax 90 216 522 1813 Ukraine PHILIPS UKRAINE 4 Patrice Lumumba str Building B Floor 7 252042 KIEV Tel 380 44 264 2776 Fax 380 44 268 0461 United Kingdom Philips Semiconductors Ltd 276 Bath Road Hayes MIDDLESEX UB3 5BX Tel 44 181 730 5000 Fax 44 181 754 8421 United States 811 East Arques Avenue SUNNYVALE CA 94088 3409 Tel 1 800 234 7381 Fax 1 800 943 0087 Uruguay see South America Vietnam see Singapore Yugoslavia PHILIPS Trg N Pasica 5 v 11000 BEOGRAD Tel 381 11 62 5344 Fax 381 11 63 5777 Internet http www semiconductors philips com SCA65 All rights are reserved Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner The information presented in this document does not form part of any quotation or contract is believed to be accurate and reliable and may be changed without notice No liability will be accepted by the publisher for any consequence of its use Publication thereof does not convey nor imply any license under patent or other industrial or intellectual p
7. L305 SMD inductor 6 8 nH 5 L308 SMD inductor 27 uH 596 1008 R101 R102 R103 R211 R212 R213 SMD resistor 10 596 603 R216 and R325 R108 and R322 SMD resistor 12 KQ 196 D EEEE Zr IEEE RIS and R14 SMD resistor 47 KQ 196 R117 SMD resistor 1kQ 1 603 R119 and R305 SMD resistor 820 Q 1 603 ee m 8 R121 SMD resistor 390 Q R201 R301 R302 and R304 SMD resistor R205 R206 R316 R317 R318 SMD resistor 10 KQ R326 and R327 R208 R209 R210 R309 and R324 Rn not loaded R222 to R224 SMD resistor 220 Q 5 R306 SMD resistor 1 R310 and R311 SMD resistor 1 R312 SMD resistor 1 R313 SMD resistor 6 8 kQ 1 R319 SMD resistor 20 kQ 5 COMPONENT TYPE U101 and U102 1 LM317T voltage TO220 regulator U103 LP2951CM voltage SO8 regulator National 1999 dun 04 48 Philips Semiconductors Product specification Global Positioning System GPS baseband processor SAA1575HL COMPONENT CHARACTERISTICS PACKAGE MAX213EAIRS2312 SSOP28 transceiver Maxim U202 and U203 SRAM M5M5256BFP 70LL 32k x 8 Mitsubishi U205 27C202 EPROM U206 ZM33064 power monitor U207 ZM33164 power monitor COMPONENT TYPE U302 MAX903ESA comparator Maxim V101 and V102 BC848 or BC847C NPN transistor V103 to V106 BC858 PNP transistor TCXO TCO 987Q 30 MHz crystal 16 pF load capacitance Y202 SMD crystal 32 768 kHz 30 ppm BPF301 and BPF302 MF1012S
8. Table 1 Supply domains SUPPLY DESCRIPTION PURPOSE main core provides power for all core supply 3 V circuits excluding those mentioned below main peripheral supply 8 to 5 V RTC core supply 2 4 to 3 V provides power for all pins excluding those mentioned below powers the real time clock the 32 kHz oscillator and the 32 kHz de bounce circuit it also produces the signals for DMCS PWRM and PWRB Voce backup provides power for the peripheral following pins DMCS supply PWRM PWRB and 2 4 to 5 V PWRFAIL In normal operation the backup core and pad supplies should be provided from the main power supply rather than a low capacity battery since the power drawn on the backup supplies while the processor is operating may be significant Two output pins PWRM and PWRB are provided to control this switching Philips Semiconductors Global Positioning System GPS baseband processor The power consumption of the SAA1575HL in the power down mode is minimal since no outputs are changing The only active circuit in power down is the real time clock Isolation between the power domains is controlled by the PWRFAIL input pin This must be driven LOW in a power failure situation to ensure that the backup domains are isolated from the main supply domains If this is not done it is possible that the registers contained in the backup supply domain will be corrupted as the main supply is cycled
9. equal to or smaller than 0 5 mm 15 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development Preliminary specification This data sheet contains preliminary data supplementary data may be published later Product specification This data sheet contains final product specifications Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System IEC 134 Stress above one or more of the limiting values may cause permanent damage to the device These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied Exposure to limiting values for extended periods may affect device reliability Application information Where application information is given it is advisory and does not form part of the specification 16 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale 1999 Jun 04 52 Philips Semiconductors Product specification Global Positioning
10. information dependent on firmware Transmitter output 0 transmit channel for serial port 0 UARTO of the embedded processor Receiver input 0 receive channel for serial port 0 UARTO of the embedded processor It is intended that this serial port is dedicated to the NMEA data stream dependent on firmware Ground 0 V reference Main I O power supply 2 7 to 5 5 V operating range main supply for the periphery in normal operation GPIO bit 4 standard general purpose I O mapped into the segment 15 of the address space The top 4 bits can be used as the XA external timer control access pins TO T1 T2 and T2EX GPIO bit 3 standard general purpose I O mapped into the segment 15 of the address space The top 4 bits can be used as the XA external timer control access pins TO T1 T2 and T2EX 1999 Jun 04 RFIC set up data serial data output used to set up the UAA1570HL front end IC RFIC set up data clock output for the serial data output used to set up the UAA1570HL front end IC The state of the RFDAT and RFLE lines is latched into the front end IC on the rising edge Philips Semiconductors Product specification Global Positioning System GPS baseband processor SAA1575HL SYMBOL DESCRIPTION RFLE RFIC setup latch output used to latch the RFIC set up into the active UAA1570HL control registers IF2 MSB IF input MSB of the 2 bit GPS digital IF signal input Clocked in on the rising edge of SCLK I
11. It is also possible that under these circumstances a high backup supply current will be drawn depending on details of the external supply circuitry 7 8 2 POWER DOWN DESIGN STRATEGY In power down operation the main supplies are assumed to have failed The backup core and pad supplies should be switched to backup power The detection of the power failure and the power supply switching is the responsibility of the user However the SAA1575HL does provide several functions to aid this task Table 2 Power down control signals SIGNAL Product specification SAA1575HL The power down and power fail operations of the SAA1575HL are controlled by two inputs PWRDN and PWRFAIL which are assumed to be connected to external voltage comparators The use of external comparators allows the voltage thresholds to be set by the system designer It also allows a certain amount of flexibility as to which supplies are monitored for power failure 7 8 2 1 Power down control signals The power down control signal pins see Table 2 are either inputs or outputs associated with the SAA1575HL power control The descriptions are for the intended use of the control signals in a normal application For a correct reset to occur it is important that PWRFAIL should be held LOW as long as minimum voltages have been established on all four of the power supply domains If this is not done various serious consequences may occur including main oscillator failu
12. System GPS baseband processor SAA1575HL VRF VRF L306 L307 R324 J cus I C308 3 L308 L309 R304 180 nH 180 nH open Je v I open 327uH open 02 R322 1 L R323 T 12 kQ AGND JAGND 2 21 kQ 1k 4700 pF VRF MIBIASP M1BIASN M2BIASP M2BIASN R317 VRF VCCA b n U302 VRF R320 MAX903ESA d 22iko TCO 987Q E es RCLK R326 C344 R321 10kQ conr I 50 V 2 21 KQ R318 R327 AGND 10ko 10 ko AGND DGND tL I AGND AGND AGND TT REFIN L 0341 I C340 4700 pF l P39GND 3 9nF TT 150 pF Baia Bis AGND nae R319 1 20 ka 2 7kQ 2 7kQ P12GND E L305 TANK 6 8nH 3 3 15 pF DATA AGND RFDATA RFCLK Sees TA AT STROBE D301 RFLE 4 SMV1233 004 1 SIGN SIGN AGND R313 C348 Sek SCLK T 6 8kQ 10 pF R316 L C339 np B Il ERU 10 ka 4 7 pF 9 kQ 33 nF L HIMINF UAA1570HL AGND AGND AGND LIMINN BFCN 1 Vcc VRF C335 33 nF ___YCCA LNA1 C334 V I C333 Y C346 0CA LNA2 33nF T 33nF 33 nF VCCA PLL C347 l k ccA LIM AGND open v VCCA MX2 C330 33 nF VCCA MXI1P 33 nF P41GND ab VCCA VCO 33 nF i Vppp 33 nF R310 DGND AGND 180
13. be parallel to the transport direction of the printed circuit board smaller than 1 27 mm the footprint longitudinal axis must be parallel to the transport direction of the printed circuit board The footprint must incorporate solder thieves at the downstream end For packages with leads on four sides the footprint must be placed at a 45 angle to the transport direction of the printed circuit board The footprint must incorporate solder thieves downstream and at the side corners During placement and before soldering the package must be fixed with a droplet of adhesive The adhesive can be applied by screen printing pin transfer or syringe dispensing The package can be soldered after the adhesive is cured Typical dwell time is 4 seconds at 250 C A mildly activated flux will eliminate the need for removal of corrosive residues in most applications 14 4 Manual soldering Fix the component by first soldering two diagonally opposite end leads Use a low voltage 24 V or less soldering iron applied to the flat part of the lead Contact time must be limited to 10 seconds at up to 300 C When using a dedicated tool all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C Philips Semiconductors Product specification Global Positioning System GPS baseband processor SAA1575HL 14 5 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDER
14. by two capacitors connected to ground a series resistor optional and a shunt resistor to ensure start up under all conditions Optimum values of C and Rp will depend on the crystal used However typical values would be C 22 pF and Rp 1 MQ Product specification SAA1575HL 7 9 3 REFERENCE CLOCK RCLK The reference clock input RCLK is used as the source for the sampling of the IF input signal A divided down version of RCLK is output on the sample clock pin SCLK for use by the front end IC The division ratio of RCLK SCLK is programmable in firmware In the standard Philips firmware this ratio is set to 3 off chip on chip XTAL3 lc XTAL Rp optional OSCILLATOR RTC clock iz XTAL4 MHB473 Fig 14 RTC clock oscillator circuit 1999 Jun 04 26 Philips Semiconductors Product specification Global Positioning System GPS SAA1575HL baseband processor 8 LIMITING VALUES In accordance with the Absolute Maximum Rating System IEC 134 SYMBOL PARAMETER CONDITIONS MIN MAX UNIT Vcc core Core supply voltage 0 5 3 6 V Vcc R RTC core supply voltage 0 5 3 6 V V absolute voltage differences between two Vcc pins total power dissipation storage temperature junction temperature ambient temperature electrostatic handling note 1 note 2 200 V Notes 1 Human body model C 100 pF R
15. in UART modes 1 and 3 1999 Jun 04 16 Product specification SAA1575HL With the standard Philips firmware both UARTs are configured to be in Mode 1 variable rate 8 bit operation Ten bits are transmitted via TXDn or received via RXDn a START bit 8 data bits LSB first and a STOP bit In general the UART clocks which are 16 times the baud rate are determined by the Timer 1 or Timer 2 overflow rate With the standard Philips firmware Timer 1 is used to generate the baud rate for UARTO and Timer 2 is used to generate the baud rate for UART1 The baud rate is set to be 4800 bits s for both UARTs 7 5 4 RF IC PROGRAMMING PORT The SAA1575HL is capable of programming the UAA1570HL via a standard 3 wire serial link This consists of a clock line SCLK data line D15 to DO and a latch enable RFLE Data is clocked into a holding register in the UAA1570HL serially on each rising edge of the output RFCLK Once the complete serial packet has been clocked into the RF IC the latch enable output RFLE is asserted which copies the new word from the holding register in the RF IC into the control registers Proper timing of the clock data and latch outputs is ensured by firmware An example sequence is illustrated in Fig 7 The signals shown would result in the value 1001 being loaded into the last 4 bits of the RF IC serial register Each loading operation of the RF IC reloads the complete RF control register With the
16. normal operation Ground 0 V reference External memory address bus bit 2 19 bit address bus used to address external RAM and program memory External memory address bus bit 1 19 bit address bus used to address external RAM and program memory LEN O External program memory select external program memory read strobe 42 Test pin tie LOW RSTIME Reset timer control this controls the on chip reset timer If this is HIGH reset will be de asserted approximately 10 ms after both PWRDN and PWRFAIL go HIGH If this is LOW reset will be de asserted approximately 10 us after both PWRDN and PWRFAIL go HIGH Test pin tie LOW Write MSB write strobe for external data memory asserted for both MSB and word write operations input mode only used for test purposes Write LSB write strobe for external data memory asserted for both LSB and word write operations input mode only used for test purposes External data read read strobe for external data memory input mode only used for test purposes 1999 Jun 04 7 Philips Semiconductors Global Positioning System GPS Product specification SAA1575HL baseband processor SYMBOL PIN DESCRIPTION D15 External memory data bus 16 bit data bus used to connect to external RAM and program memory D14 External memory data bus bit 14 16 bit data bus used to connect to external RAM and program memory Ground 0 V reference lt lt o o 0
17. standard Philips firmware a 20 bit long word 0X5E320 is transmitted in this manner on start up or re initialization This gives full compatibility with the Philips UAA1570HL front end IC See the UAA1570HL for more details about the configuration options of the front end IC Philips Semiconductors Product specification Global Positioning System GPS baseband processor SAA1575HL RFLE holding XXXX XXX1 XX10 X100 1001 control XXXX X 1001 MHB466 X don t care Fig 7 Example timing for UAA1570HL programming 7 5 5 GENERAL PURPOSE I O The SAA1575HL possesses an 8 bit general purpose I O register and 8 associated I Os see Fig 8 With the standard Philips firmware all 8 of these pins are configured as outputs With the standard Philips firmware only pin GPIOO is used This is switched on at the end of the firmware initialization sequence and remains on subsequently VCC P Em CFGn 10 pull up FET DATA BUS GPlOn C pin O READ E MHB467 Fig 8 GPIO pin drive circuits 1999 Jun 04 17 Philips Semiconductors Global Positioning System GPS baseband processor 7 6 The Real Time Clock RTC is a functional unit used to generate time information Its purpose is to supply approximate GPS time to the system firmware for the initial acquisition of satellites a warm start The power supply for the RTC is separate from the rest of the IC allowing a low capacity ba
18. the end of the interrupt routine the firmware places the SAA1575HL into reset As Vcc p continues to fall the second threshold is reached and is taken LOW This toggles the power controls both PWRM and PWRB and will force a reset if it has not already occurred On power up the power controls both PWRM and PWRB will be switched once the second threshold voltage is reached As the supply voltage rises further the first voltage threshold will be reached at which time both PWRDN and PWRFAIL will be HIGH This starts the reset counter and the SAA1575HL will remain in reset until a set time after this depending on the state of the input pin RSTIME Vi Vio PWRB PWRM delay while XA in interrupt routine VCC core a er a TT HH reset timer delay set by RSTIME MHB470 Fig 11 Example of power down strategy with slow supplies 1999 Jun 04 22 Philips Semiconductors Global Positioning System GPS baseband processor 7 8 2 3 Example of strategy for fast supplies The second example will operate correctly in circuits where the delay between the supplies to the peripheral and core power domains is significant compared to the rise times of the power supplies This may occur in cases where the core supply is a regulated delayed version of the peripheral supply If the previous strategy were used in this situation it would be possible for the SAA1575HL to miss the PWRFAI
19. 1 saw filter Note 1 With heat sink depending on input voltage 1999 Jun 04 49 Philips Semiconductors Product specification Global Positioning System GPS SAA1575HL baseband processor 13 PACKAGE OUTLINE LQFP100 plastic low profile quad flat package 100 leads body 14 x 14 x 1 4 mm SOT407 1 1 PA detail X DIMENSIONS mm are the original dimensions A UNIT max Ai A2 As bp 1 5 mm 1 6 13 0 25 Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION JEDEC EIAJ PROJECTION SOT407 1 E 97 08 04 ISSUE DATE 1999 Jun 04 50 Philips Semiconductors Global Positioning System GPS baseband processor 14 SOLDERING 14 1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology A more in depth account of soldering ICs can be found in our Data Handbook IC 26 Integrated Circuit Packages document order number 9398 652 90011 There is no soldering method that is ideal for all surface mount IC packages Wave soldering is not always suitable for surface mount ICs or for printe
20. 27 24825 Philips Electronics N V 1999 a worldwide company Netherlands Postbus 90050 5600 PB EINDHOVEN Bldg VB Tel 31 40 27 82785 Fax 31 40 27 88399 New Zealand 2 Wagener Place C P O Box 1041 AUCKLAND Tel 64 9 849 4160 Fax 64 9 849 7811 Norway Box 1 Manglerud 0612 OSLO Tel 47 22 74 8000 Fax 47 22 74 8341 Pakistan see Singapore Philippines Philips Semiconductors Philippines Inc 106 Valero St Salcedo Village P O Box 2108 MCC MAKATI Metro MANILA Tel 63 2 816 6380 Fax 63 2 817 3474 Poland UI Lukiska 10 PL 04 123 WARSZAWA Tel 48 22 612 2831 Fax 48 22 612 2327 Portugal see Spain Romania see Italy Russia Philips Russia Ul Usatcheva 35A 119048 MOSCOW Tel 7 095 755 6918 Fax 7 095 755 6919 Singapore Lorong 1 Toa Payoh SINGAPORE 319762 Tel 65 350 2538 Fax 65 251 6500 Slovakia see Austria Slovenia see Italy South Africa S A PHILIPS Pty Ltd 195 215 Main Road Martindale 2092 JOHANNESBURG P O Box 58088 Newville 2114 Tel 27 11 471 5401 Fax 27 11 471 5398 South America Al Vicente Pinzon 173 6th floor 04547 130 SAO PAULO SP Brazil Tel 55 11 821 2333 Fax 55 11 821 2382 Spain Balmes 22 08007 BARCELONA Tel 34 93 301 6312 Fax 34 93 301 4107 Sweden Kottbygatan 7 Akalla S 16485 STOCKHOLM Tel 46 8 5985 2000 Fax 46 8 5985 2745 Switzerland Allmendstrasse 140 CH 8027 ZURICH Tel 41 1 488 2741 Fax 41 1 488 3263
21. 58 HB HEADEHRI0 ND SAA1575HL 57 Bo 56 oi 55 l p TP201 e H 98 sa DIS 0 TP202 o S9E 49 HE 48 TP203 o SIGN 71 oa TPa 22 gg REDAT oTpaaa V RFCLK cc 3 90 Ha 0 TP223 Eie RCLK 31 RFLE DES gt F9 SCLK SCLK gt T1S_OUT T18 v SeN SIGN TP204o SO 5 d8 bo Yoo eun BATT ON Tp2os o BATON PWRB 25 KE vocz ON BATT OFF PWRM COIP BATT OFF TP206 o BATLOFF PWRM mE 78 S Hog Yoos Voc o gt E V Gc Ven 48 51 yore C4 SS l a 61 LOO V cg Vss YooiP 17 86 Voce _Vss gs V V sS si 12 CC core boi Vss VcC core 38 30 7 DD2 Vss CC core toy 66 Vpp3 ss l U V Vss 5 72 oe VRTC1 T Hee CC B ss 5 80 VBBi t 79 41 SS a5 GND Vppi Vbpp2 Vpps Vesi vatci Veci Vcc2 Voca Vcc4 Vocs Vccs Vcc m la i io l les m la m i C221 C222 C223 L C224 UP TUE Jes Te Peepe jee Jum Saas IST sd Se ad Sab T 33 nF T MHB290 GND Fig 23 Baseband circuitry continued in Fig 24 1999 Jun 04 36 Philips Semiconductors Global Positioning System GPS baseband processor Product specification SAA1575HL D0 D8 Di D9 D2 D10 D3 D11 D4 D12 D5 D13 D6 D14 D7 D15 VBB D0 D0 Dt D
22. 5HL 63 D5 XTAL1 62 D6 XTAL2 15 61 Vcc p VCC P 60 Vss 59 D7 58 D8 57 D9 56 D10 55 D11 54 D12 53 D13 52 PWRDN VCC P 51 Voc P e B IRIS 5 II 5 18 s IS a S El S e Ee ST ST B Bete Presse CPR BE se gEra s 2 m o F 2 Fig 2 Pin configuration 1999 Jun 04 11 Philips Semiconductors Global Positioning System GPS baseband processor 7 FUNCTIONAL DESCRIPTION 7 1 Overview The function of the SAA1575HL is to accept any IF data 1 or 2 bit from a front end RF IC such as the UAA1570HL and provide a serial NMEA compatible GPS position and time output The IF input is sampled synchronously with the front end reference clock SCLK Data is decoded from the IF input stream by one of eight parallel correlators which allow up to eight satellites to be tracked at one time The acquisition allocation and tracking of the satellites is performed under firmware control by the on chip processor In addition to the SAA1575HL and an appropriate front end IC such as the UAA1570HL the only external components required to complete a functional GPS receiver are some RAM the firmware ROM and some discrete devices to control the power supplies The need for external glue logic is eliminated by various chip select functions implemented on the SAA1575HL The SAA1575HL also contains an optional independent Real Time Clock RTC which requires a separate 32 768 kHz crystal This can be set to GPS
23. 9 Jun 04 6 Philips Semiconductors Product specification Global Positioning System GPS baseband processor SAA1575HL SYMBOL A11 DESCRIPTION External memory address bus bit 11 19 bit address bus used to address external RAM and program memory Main I O power supply 2 7 to 5 5 V operating range main supply for the periphery in normal operation Voc p C P Ground 0 V reference External memory address bus bit 10 19 bit address bus used to address external RAM and program memory External memory address bus bit 9 19 bit address bus used to address external RAM and program memory External memory address bus bit 8 19 bit address bus used to address external RAM and program memory Main core power supply 2 7 to 3 6 V only main supply for the core in normal operation Ground 0 V reference External memory address bus bit 7 19 bit address bus used to address external RAM and program memory External memory address bus bit 6 19 bit address bus used to address external RAM and program memory External memory address bus bit 5 19 bit address bus used to address external RAM and program memory External memory address bus bit 4 19 bit address bus used to address external RAM and program memory External memory address bus bit 3 19 bit address bus used to address external RAM and program memory VcciP Main I O power supply 2 7 to 5 5 V operating range main supply for the periphery in
24. ARD PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DEFINITIONS LIFE SUPPORT APPLICATIONS Philips Semiconductors Global Positioning System GPS baseband processor 1 FEATURES Single chip GPS baseband solution with built in 16 bit microcontroller All digital 0 5 micron CMOS technology Single power supply with full 3 V operation Separate I O power supply pins for operation with 3 or 5 V external devices Up to 30 MHz system clock from on chip crystal oscillator or external clock input 2 kbytes words internal data memory for fast execution External bus for up to 512 kbytes words data memory and 512 kbytes words program memory Programmable external bus timing to match external memory speed Chip selection outputs to reduce glue logic requirements Reset controller for power down detection and servicing 8 GPS channel correlators driven by firmware for flexible GPS correlation algorithms 1 second pulse output of GPS time 2 bit digital IF GPS signal input synchronized to external sample clock 2 fully duplex UARTs for communication with host System processor and other devices Real time clock with 32 768 kHz crystal and supply for low power timekeeping Watchdog timer Power down modes under firmware control 100 pin LQFP package 50 mA supply cur
25. BC858 A pmo VRTC J C113 22 uF TP103 Jc 6 3 V U103 VDD IN GND LP2951CM E i G3 O lt Is le Vcc Ta R106 C106 18 kQ 100 nF C111 G105 10 uF 100 nF 6 3 V R108 12 ka GND GND GND GND GND GND MHB294 Fig 27 Power supply circuitry 1999 Jun 04 40 Philips Semiconductors Global Positioning System GPS baseband processor Product specification SAA1575HL The GPS system application demonstration board consists of 6 layers with a total final thickness of 1 5 mm The PCB material is FR4 o Ole GPS DEMO BOARD Version 1 3 PHILIPS DNCCNECO U102 C116 00445 o e000 0 R303 R307 o C325 R319 CINE 9 Sh no C329 Rao2 Eel 3vi70mAh o Q o o 0308 C338 3 oL Thate lk gt O BPF3021 C317 o L303 cLlcai4 O o IBA_ID 801291 RS232 10 O0 O 0 O O O O O Cy RS232 0 e 00000 O OOO MHB295 Fig 28 Demonstration board top layer plus components real size 88 9 mm x 88 9 mm 1999 Jun 04 41 Philips Semiconductors Product specification Global Positioning System GPS baseband processor SAA1575HL MHB296 Fig 29 Demonstration board 2nd layer 1999 Jun 04 42 Philips Semiconductors
26. ELATORS RFDAT IF1 CONTROL RFCLK REGISTERS RFLE t dM GPIO7 to GPIOO 94 to 96 RCLK XTAL3 XTAL4 SCLK PWRFAIL T18 PWRDN RESET SAA1575HL CONTROLLER RSTIME PWRM PWRB TEST1 16 25 13 17 26 31 TEST2 12 30 37 51 38 50 60 65 66 61 86 71 79 85 n c Voc R Vcc B VCC core VOCC P Vss TP4 TP3 TP2 TP1 MHB460 Fig 1 Block diagram 1999 Jun 04 5 Philips Semiconductors Product specification Global Positioning System GPS baseband processor SAA1575HL 6 PINNING SYMBOL PIN yo DESCRIPTION Sample clock sample clock generated internally by dividing down the RCLK reference clock input This output is provided for use by the front end IC GPS time pulse a 1 pulse per second output whose rising or falling edge firmware controlled is synchronized to GPS time when the receiver is tracking a GPS signal The pulse length is approximately 1 ms Test pin tie HIGH Test pin tie HIGH GPIO bit 5 standard general purpose I O mapped into the segment 15 of the address space The top 4 bits can be used as the XA external timer control access pins TO T1 T2 and T2EX GPIO bit 6 standard general purpose I O mapped into the segment 15 of the address space The top 4 bits can be used as the XA external timer control access pins TO T1 T2 and T2EX GPIO bit 7 standard general purpose I O mapped into the segment 15 of the address space The top 4 bits can be used as the XA external timer control a
27. I D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 VBB C201 C202 walt volt m U201 C203 ni ni 60V Gov Le 12 AF vec Ci V 100 nF car te HE 50 V C2 i C204 TIOUT LIUN TXDO 100nF T2OUT 5 o T2N TxDi 50V T8OUT 2o T3IN GND T4OUT T4IN 28 21 Vec RIIN a RIOUT RXDO TR2IN s R2OUT RxDi B N 2 25 R3OUT TRAIN 53 29 R4OUT Voc REIN 2 19 RSOUT 24 LEN 7SHDN U202 25 Voc 10 11 MAX213EAI A2 9 12 A3 8 13 A4 7 15 AS 6 16 aL A6 E na DB9 GND A7 2 H A8 3 19 A9 oe A10 24 AT A12 23 A13 A14 A15 h RFD R224 RFDATA 1 4 RFDATA DMCS EL R210 TP226 20 28 open o 22 14 WRH 27 RFC R223 RFCLK M5M5256BVP H RFCLK 2200 R209 TP227 open O U203 n AT 10 11 9 12 RFL R222 RFLE A3 C HHH T RFLE ad 8 18 RD R208 TP228 A5 T 15 Oben AG 6 16 5 17 A7 4 18 A8 3 19 _ A9 GND Aio 25 24 AM 21 A12 25 A13 A A14 A15 2 i Vect DMCS 5 PS BD 22 14 V cc2 MRL 27 V _ _ 1 C225 m TT uF MSM5256BVP Veca 63v Ves 4 GND Rate U205 Vece a Voc 21 20 VDD1 19 0226 47 uF 6 3 V Vpp2 2155 16 GND M R213 i Vpp3 Vpp 10 11 R212 10 VRTCI T 1 VRTC 9 10 8 R211 7 VBB1 3 VBB 6 10 5 4 43 27C202 Fig 24 Baseband circuitry continued from Fig 23 MHB291 1999 Jun 04 37 Philips Semiconductors Product specification Global Positioning
28. II T BIASGND2 L MI1BIASN S pF Se pk C305 open LNA2GND1 TL P42GND AGND PLLGND LIMGND MX2GND MXPGND C302 C303 C311 MX1GND li II l II II LIMINP o 47 pF 47 pF I 1000 pF COGN oe C301 C309 3L301 L302 L G310 R305 82 pF 18pF 2 22uH 22uH F 68 pF 8202 DGND C304 R301 C312 1k m LIMINN E open 0o 1000 pF M2BIASN Rado L 09 DGND AGND ch AGND MHB293 Fig 26 RF front end circuit continued from Fig 25 1999 Jun 04 39 Philips Semiconductors Product specification Global Positioning System GPS baseband processor SAA1575HL D101 LL4007 den PL101 CC JMP3 I U101 os R101 o Voc I To R118 D102 LM317T 3 270 Q LL4007 C102 C108 1nF 22 uF G101 C107 4 108 R119 5V 1nF 1 uF 10 uF 8200 I il 20 V I aov GND GND GND GND GND GND GND TP102 VRF R102 VRF V I TG BAT D104 LL4007 Gade C104 C110 1kQ 1nF 22 uF B101 6V w 170 mAh GND R122 3V 5V 330 Q Voc VBAT Voc RNB vios vies HH C we me R111 47ko P858 BC858 A oMo 1MQ VBB p Rio es Rie T ens 1700 la BC848 TRO 22 uF R110 V101 6 3 V BATT OFF TMQ BC848 GND C112 VDD VBAT s nF Je L H114 yog vioo P116 GND GND GND 47ko N BC858
29. ING METHOD PACKAGE WAVE REFLOW BGA SQFP not suitable HLQFP HSQFP HSOP HTSSOP SMS not suitable PLCCG SO SOJ suitable LQFP QFP TQFP not recommended 34 SSOP TSSOP VSO not recommended Notes 1 All surface mount SMD packages are moisture sensitive Depending upon the moisture content the maximum temperature with respect to time and body size of the package there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them the so called popcorn effect For details refer to the Drypack information in the Data Handbook IC26 Integrated Circuit Packages Section Packing Methods 2 These packages are not suitable for wave soldering as a solder joint between the printed circuit board and heatsink at bottom version can not be achieved and as solder may stick to the heatsink on top version 3 If wave soldering is considered then the package must be placed at a 45 angle to the solder wave direction The package footprint must incorporate solder thieves downstream and at the side corners 4 Wave soldering is only suitable for LQFP TQFP and QFP packages with a pitch e equal to or larger than 0 8 mm it is definitely not suitable for packages with a pitch e equal to or smaller than 0 65 mm 5 Wave soldering is only suitable for SSOP and TSSOP packages with a pitch e equal to or larger than 0 65 mm it is definitely not suitable for packages with a pitch e
30. L LOW state at power up resulting in the IC not being given a correct reset In this example the PWRDN logic input is derived as before by comparing the Vcc p supply voltage against a known reference voltage But in this instance the PWRFAIL logic input is derived by comparing the Vcc core core supply against a threshold voltage AS Vccip falls the first threshold level is reached and PWRDN is taken LOW This triggers an interrupt in the firmware which is used to perform any required housekeeping At the end of the interrupt routine the firmware places the SAA1575HL into reset Vt Product specification SAA1575HL However if the fall times on the supplies is fast it is likely that the PWRFAIL input will go LOW before the interrupt routine has been completed This would force the SAA1575HL into immediate reset At this time both PWRM and PWRB toggle to switch backup supply sources On power up the Vcc p supply rises quickly However since this only controls an interrupt flag and the SAA1575HL is still held in reset by PWRFAIL this has no effect Only once the Vcc core supply rises will PWRFAIL be de asserted This can only occur once the Vcc core voltage has reached the set threshold and so there is no risk of the IC missing the reset pulse The SAA1575HL will come out of reset a set time after this depending on the state of the input pin RSTIME Voc P PWRB PWRM delay while XA in interrupt
31. Product specification Global Positioning System GPS baseband processor SAA1575HL O wooo O 8 O ooog eere O MHB297 Fig 30 Demonstration board 3rd layer 1999 Jun 04 43 Philips Semiconductors Product specification Global Positioning System GPS baseband processor SAA1575HL MHB298 Fig 31 Demonstration board 4th layer 1999 Jun 04 44 Philips Semiconductors Product specification Global Positioning System GPS baseband processor SAA1575HL MHB299 Fig 32 Demonstration board 5th layer 1999 Jun 04 45 Philips Semiconductors Product specification Global Positioning System GPS baseband processor SAA1575HL RS232 10 3VA170mAh o O o a o O o o O Oo GPS DEMO BOARD Version 1 3 PHILIPS 00000 OOOO OCOoo U102 C116 009115 o o 009 0 o oBATT OFFU201 e o o Oo o RS232 0 R OQ Ooooo C212 C214 o O G324 L C325_ 6341L LIR319 PA 0 oOo C329 R302 C211 C217 o is OOOO O00000 C306 C338 9L7n316 o BPF302 QO EJ cat gs e IBA_1TD 801291 MHB300 Fig 33 Demonstration board bottom layer plus components 1999 Jun 04 46 Philips Semiconductors Product spec
32. R311 180 VRF R309 VDDD E 1 open R325 Vccb MHB292 12 Fig 25 RF front end circuit continued in Fig 26 1999 Jun 04 38 Philips Semiconductors Product specification Global Positioning System GPS baseband processor SAA1575HL L 900 mils L 1020 mils W 8 8 mils W 8 8 mils R303 R307 VRF 9o 92 ii C328 li C327 33 nF 10pF T 60v T 60V AGND AGND J301 C325 SMA F 1 Q L 315 mils 8 1 mm 27 pF L 367 mils 9 3 mm W 6 mils C324 W 33 mils C326 100 0 T 1 5 pF 500 qos pF AGND AGND AGND L 355 mils 9 mm BPF301 W 6 mils MF1012S 1 100 2 vO T C321 li C307 0 27 pF open LNA1IN T P I p AGND AGND L 286 mils 7 3 mm LNA1OUT LNA2IN W 6 mils 1000 LNA2OUT MX1IN L 412 mils 10 5 mm L 217 mils 5 5 mm BPF302 W 6 mils W 33 mils MF1012S 1 IFIP 100 Q 502 vO IFN I I C320 C306 IF2INN T8 Tos IF2INP AGND AGND L 386 mils 10 mm uui W 6mils 1000 IF2N C315 C317 UAA1570HL EROI II Il x Lipase I 6 8 pF I 8 2 pF I BIASGND1 C313 L303 C314 L304 C319 R306 36 pF 330 nH T 36 pF 330 nH TF 39 pF 9092 LNA1GND2 C316 C318 LNA2GND2
33. S is an active LOW strobe used to enable the output of the external code memory It remains HIGH when a read code is not in progress 7 7 2 DATA MEMORY CHIP SELECT This signal DMCS is an active LOW strobe used to enable the external data memory The SAA1575HL hardware supports two distinct modes of operation of this signal selected in firmware designed for optimum power or optimum speed The standard Philips firmware is configured for optimum power DMCS is taken LOW during an external data read or write operation to segments 0 to 14 of the memory map To prevent the corruption of external data memory the DMCS pin is driven on the backup supply voltage and will be held HIGH once the PWRFAIL signal has been asserted LOW With the standard Philips firmware the DMCS signal is gated by the external access read and write strobes This should significantly reduce the power consumption of the external RAM but may require the use of a slightly faster external memory depending on clock speed and details of the external memory used 7 7 3 READ STROBE This signal RD is an active LOW strobe used to indicate that the XA is expecting data from the external bus 7 7 4 WRITE LOW BYTE STROBE This signal WRL is an active LOW strobe used to indicate that the XA is performing an external write This strobe only applies to the lower data byte of the 16 bit data word allowing byte writes to be performed from the 16 bit data
34. System GPS baseband processor SAA1575HL NOTES 1999 Jun 04 53 Philips Semiconductors Product specification Global Positioning System GPS baseband processor SAA1575HL NOTES 1999 Jun 04 54 Philips Semiconductors Product specification Global Positioning System GPS baseband processor SAA1575HL NOTES 1999 Jun 04 55 Philips Semiconductors Argentina see South America Australia 34 Waterloo Road NORTH RYDE NSW 2113 Tel 61 2 9805 4455 Fax 61 2 9805 4466 Austria Computerstr 6 A 1101 WIEN P O Box 213 Tel 43 1 60 101 1248 Fax 43 1 60 101 1210 Belarus Hotel Minsk Business Center Bld 3 r 1211 Volodarski Str 6 220050 MINSK Tel 375 172 20 0733 Fax 375 172 20 0773 Belgium see The Netherlands Brazil see South America Bulgaria Philips Bulgaria Ltd Energoproject 15th floor 51 James Bourchier Blvd 1407 SOFIA Tel 359 2 68 9211 Fax 359 2 68 9102 Canada PHILIPS SEMICONDUCTORS COMPONENTS Tel 1 800 234 7381 Fax 1 800 943 0087 China Hong Kong 501 Hong Kong Industrial Technology Centre 72 Tat Chee Avenue Kowloon Tong HONG KONG Tel 852 2319 7888 Fax 852 2319 7700 Colombia see South America Czech Republic see Austria Denmark Sydhavnsgade 23 1780 COPENHAGEN V Tel 45 33 29 3333 Fax 45 33 29 3905 Finland Sinikalliontie 3 FIN 02630 ESPOO Tel 358 9 615 800 Fax 358 9 6158 0920 France 51 Rue Carnot BP317 92156 SURESNES Cedex
35. Tel 33 1 4099 6161 Fax 33 1 4099 6427 Germany Hammerbrookstra3e 69 D 20097 HAMBURG Tel 49 40 2353 60 Fax 49 40 2353 6300 Hungary see Austria India Philips INDIA Ltd Band Box Building 2nd floor 254 D Dr Annie Besant Road Worli MUMBAI 400 025 Tel 91 22 493 8541 Fax 91 22 493 0966 Indonesia PT Philips Development Corporation Semiconductors Division Gedung Philips Jl Buncit Raya Kav 99 100 JAKARTA 12510 Tel 62 21 794 0040 ext 2501 Fax 62 21 794 0080 Ireland Newstead Clonskeagh DUBLIN 14 Tel 353 1 7640 000 Fax 353 1 7640 200 Israel RAPAC Electronics 7 Kehilat Saloniki St PO Box 18053 TEL AVIV 61180 Tel 972 3 645 0444 Fax 972 3 649 1007 Italy PHILIPS SEMICONDUCTORS Piazza IV Novembre 3 20124 MILANO Tel 39 02 67 52 2531 Fax 39 02 67 52 2557 Japan Philips Bldg 13 37 Kohnan 2 chome Minato ku TOKYO 108 8507 Tel 81 3 3740 5130 Fax 81 3 3740 5057 Korea Philips House 260 199 ltaewon dong Yongsan ku SEOUL Tel 82 2 709 1412 Fax 82 2 709 1415 Malaysia No 76 Jalan Universiti 46200 PETALING JAYA SELANGOR Tel 60 3 750 5214 Fax 60 3 757 4880 Mexico 5900 Gateway East Suite 200 EL PASO TEXAS 79905 Tel 9 5 800 234 7381 Fax 9 5 800 943 0087 Middle East see ltaly For all other countries apply to Philips Semiconductors International Marketing amp Sales Communications Building BE p P O Box 218 5600 MD EINDHOVEN The Netherlands Fax 31 40
36. This strobe will also be taken LOW for word write operations 7 7 5 This signal WRH is an active LOW strobe used to indicate that the XA is performing an external write This strobe only applies to the higher data byte of the 16 bit data word allowing byte writes to be performed from the 16 bit data This strobe will also be taken LOW for word write operations WRITE HIGH BYTE STROBE 1999 Jun 04 Product specification SAA1575HL 7 8 Backup supplies and reset The SAA1575HL is designed to operate correctly in situations when the main power supply fails In addition to the main core and peripheral power supplies separate pins are provided for backup core and peripheral supplies which enable critical and low power functions to be maintained during the loss of main power There is also an on chip reset timer which will aid the design of a full power down strategy 7 8 1 SUPPLY DOMAINS To allow for the use of inexpensive 5 V external components the periphery of the SAA1575HL can be powered with a higher voltage than the core Therefore there is a distinction between the core and peripheral power supplies In addition there is the need to maintain certain functionality on a low power supply in the event of main power failure Therefore there are 2 additional supplies required for so called backup operation Thus there are four distinct power supply domains two for the core supplies and two for the peripheral supplies
37. U address valid time twLDL WRH and WRL asserted to DMCS asserted twiomcs DMCS pulse width WRH and WRL de asserted to DMCS de asserted address valid to WRH and WRL asserted tWHDH AVWL note 1 twLwH WRH and WRL pulse width tavav address valid to data valid data valid to WRH and WRL de asserted WRH and WRL de asserted to address undefined data hold time after WRH and WRL de asserted GPS IF input timing see Fig 20 tPvsH IF set up time before rising edge of SCLK tsurv IF hold time after rising edge of SCLK 1 second pulse output see Fig 21 lw T1S T1S pulse width 10 ns ns S Tris T1S pulse period Notes 1 For default DCMS operation note 2 1 0 u 1 0 S 2 The 1 s pulse output is only valid when at least one channel is locked Table4 Explanation of symbol characters in Chapter AC characteristics SYMBOL CHARACTER gt DESCRIPTION address O clock input data m o DMCS strobe instruction program memory Ol 0 PCMS strobe output data R RD W WRH or WRL strobes logic high FHE logic low undefined N lt C valid high impedance or pull up 1999 dun 04 31 Philips Semiconductors Product specification Global Positioning System GPS baseband processor SAA1575HL tCLCH tcHc avira MHB474 Fig 15 External XTAL1 clock drive
38. be reset by the watchdog timer this may be disabled on some custom firmware revisions 7 8 4 POWER SAVING MODES The SAA1575HL supports two power saving modes Idle mode and sleep mode Both modes are selected by firmware or message over the serial link if included in the firmware In addition the input to any of the correlators can be inhibited individually by firmware which will reduce the power consumed by the block to only the clock tree dissipation Philips Semiconductors Global Positioning System GPS baseband processor 7 8 4 1 Sleep mode The sleep mode is intended to overlay the function of the standard 80C51XA Idle mode Sleep is initiated by a firmware or external serial link command This initiates a firmware routine which performs the following 1 Send serial command to power down RF IC UAA1570HL 2 Inhibit RCLK IF2 and IF1 inputs to SAA1575HL 3 Enter standard 80C51XA Idle state In sleep mode the RCLK and IF inputs are prevented from entering the IC This capability is included to cover the situation in which the SAA1575HL is used with a front end which does not respond to the power down command ina similar way to the UAA1570HL Sleep mode can be exited by any active hardware interrupt for example a UART interrupt The sleep mode has no effect on the operation of the RTC 7 8 4 2 Idle mode The Idle mode is initiated by a firmware or external serial link command This is a direct use of the standar
39. c1 c1 O1 no oO 1 Co Main I O power supply 2 7 to 5 5 V operating range main supply for the periphery in normal operation Power down indicator a LOW on this pin asserts an XA interrupt intended for use as a power fail interrupt Once reset is asserted either by PWRFAIL or the firmware it will remain asserted until a set time after this pin goes HIGH External memory data bus bit 13 16 bit data bus used to connect to external RAM and program memory iw PO o R w _ 4 c1 C1 External memory data bus bit 12 16 bit data bus used to connect to external RAM and program memory External memory data bus bit 11 16 bit data bus used to connect to external RAM and program memory oO o External memory data bus bit 10 16 bit data bus used to connect to external RAM and program memory g e O External memory data bus bit 9 16 bit data bus used to connect to external RAM and program memory External memory data bus bit 8 16 bit data bus used to connect to external RAM and program memory Oo N lt External memory data bus bit 7 16 bit data bus used to connect to external RAM and program memory Ground 0 V reference lt Q fe O a Main I O power supply 2 7 to 5 5 V operating range main supply for the periphery in normal operation External memory data bus bit 6 16 bit data bus used to connect to external RAM and program memory External mem
40. cc g supplies to ensure that the external RAM is not enabled during power down PWRFAIL Power fail indicator a LOW on this pin forces the embedded microcontroller into reset Reset will not be de asserted until a set time after both PWRDN and PWRFAIL go HIGH For correct start up this pin should be LOW on power up Crystal 4 output from the RTC oscillator amplifier this pin is only 3 V tolerant Crystal 3 input to inverting amplifier used in the RTC oscillator circuits 32 768 kHz this pin is only 3 V tolerant Backup supply select this output is intended to drive an external FET used to switch the battery backup supply s It is active LOW and is controlled directly by the PWRFAIL Main supply select this output is intended to drive an external FET used to switch the main supply s It is active LOW and is controlled directly by PWRFAIL Ground 0 V reference Backup I O power supply 2 4 to 5 5 V only Supply for the RAM select power fail and power switching I O pads only allowing these functions to be powered when the main power supply fails This should be powered from the main supply during normal operation and switched to battery backup when the main supply fails Transmitter output 1 transmit channel for serial port 1 UART1 of the embedded processor Receiver input 1 receive channel for serial port 1 UART1 of the embedded processor It is intended that this serial port is dedicated to differential GPS
41. ccess pins TO T1 T2 and T2EX Not connected do not connect Not connected do not connect External memory address bus bit 19 19 bit address bus used to address external RAM and program memory External memory address bus bit 18 19 bit address bus used to address external RAM and program memory VCC core Main core power supply 2 7 to 3 6 V only main supply for the core in normal operation Vss 13 Ground 0 V reference Crystal 1 input to the inverting amplifier used in the system oscillator circuit and input to the internal clock generator circuits 1 2 3 4 5 7 8 9 10 11 12 Crystal 2 output from the system oscillator amplifier Main I O power supply 2 7 to 5 5 V operating range main supply for the periphery in normal operation Ground 0 V reference O External memory address bus bit 17 19 bit address bus used to address external RAM and program memory External memory address bus bit 16 19 bit address bus used to address external RAM and program memory External memory address bus bit 15 19 bit address bus used to address external RAM and program memory External memory address bus bit 14 19 bit address bus used to address external RAM and program memory External memory address bus bit 13 19 bit address bus used to address external RAM and program memory External memory address bus bit 12 19 bit address bus used to address external RAM and program memory 199
42. ch the main supplies to all of the supply input pins In normal operation the backup pad supply pin should be driven by the main supply and the backup core supply pins should be driven by the main core supply When the IC goes into power down mode this output goes HIGH In power down the backup supply pins should be driven by their appropriate supplies Backup power supply control this is the inverse of PWRM 1999 Jun 04 21 Philips Semiconductors Global Positioning System GPS baseband processor 7 8 22 Example of strategy for slow supplies The ultimate use of the power control signals is up to the user However two possibilities are presented as design examples The first example will operate correctly in circuits where the rise times of the power supplies is slow compared to any delay between the supplies to the peripheral and core power domains In this example both the PWRDN and PWRFAIL logic inputs to the SAA1575HL are derived by comparing the Vccip supply voltage against known references In general since it is a lower voltage the Vcc core supply may hold and reach it s nominal voltage quicker than the Voc p supply AS Vccip falls the first threshold is reached and PWRDN is taken LOW This triggers an interrupt in the firmware which is used to perform any required housekeeping It is assumed that there is time for this to be completed before complete supply failure Product specification SAA1575HL At
43. d 80C51XA Idle mode The interrupt signals from the active peripherals such as UARTS timers host interface and external interrupts will cause the CPU to resume execution from the point at which it was halted In the Idle mode all of the output pins retain their logic states from their pre idle position No other action is taken on entering Idle mode In particular the correlators will remain active since RCLK IF1 and IF2 will not be prevented from entering the IC Product specification SAA1575HL 7 9 Clock signals and oscillators The SAA1575HL requires 3 clock signals for full operation e XTAL1 Processor system clock e XTAL3 Real time clock crystal frequency optional e RCLK GPS reference clock Two of these clocks XTAL1 and XTAL3 can be generated by on chip oscillator circuits The third RCLK must be supplied from an external source in most applications a temperature compensated oscillator module 7 9 1 SYSTEM CLOCK XTAL1 The SAA1575HL requires a system clock for the on chip processor and related peripheral blocks This can be provided from an external clock source via the XTAL1 input pin or by using the on chip oscillator circuit with an external resonating element connected between the XTAL1 and XTAL2 pins In most circumstances this would be an external crystal accompanied by two capacitors connected to ground a series resistor to optimize power consumption and a shunt resistor to ensure start up und
44. d non burst code read see Fig 16 tAVAU address valid time period 163 7 165 7 ns tAVPL address valid to PMCS asserted twemcs PMCS pulse width 97 0 98 0 l ns pLiv PMCS LOW to instruction valid thi instruction hold time after PMCS de asserted e ns taviv address valid to instruction valid access time eee instruction set up time before PMCS 14 0 ns de asserted bus 3 state after PMCS de asserted hold time of a 3 1 after PMCS de asserted 0 External program memory read burst code read see Figs 16 and 17 tAVAU address valid time period address valid to instruction valid access time 115 3 instruction valid to address undefined 15 0 17 0 taulu address valid to instruction undefined External data memory read see Fig 18 tavau address valid time period RLEL RD asserted to DMCS asserted W DMCS DMCS pulse width TRHEH RD de asserted to DMCS de asserted tAVRL address valid to RD asserted tw RD RD pulse width tAVDV address valid to data valid access time taLpv RD asserted to data valid tsu D data set up time before RD de asserted th D data hold time after RD de asserted tRHDZ bus 3 state after RD de asserted 1999 Jun 04 30 Philips Semiconductors Global Positioning System GPS baseband processor SYMBOL PARAMETER Product specification SAA1575HL CONDITIONS MIN External data memory write see Fig 19 tAVA
45. d circuit boards with high population densities In these situations reflow soldering is often used 14 2 Reflow soldering Reflow soldering requires solder paste a suspension of fine solder particles flux and binding agent to be applied to the printed circuit board by screen printing stencilling or pressure syringe dispensing before package placement Several methods exist for reflowing for example infrared convection heating in a conveyor type oven Throughput times preheating soldering and cooling vary between 100 and 200 seconds depending on heating method Typical reflow peak temperatures range from 215 to 250 C The top surface temperature of the packages should preferable be kept below 230 C 14 3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices SMDs or printed circuit boards with a high component density as solder bridging and non wetting can present major problems To overcome these problems the double wave soldering method was specifically developed 1999 Jun 04 51 Product specification SAA1575HL If wave soldering is used the following conditions must be observed for optimal results e Use a double wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave For packages with leads on two sides and a pitch e larger than or equal to 1 27 mm the footprint longitudinal axis is preferred to
46. eded by an internal Arithmetic and Logic Elements ALEs cycle as in any standard 80C51 system The multiplexed address data bus and the ALE signal are not available externally However for clarity these are illustrated in Figs 3 to 6 internal signals MHB462 Fig 3 Example of external data read standard firmware 1999 Jun 04 13 Philips Semiconductors Global Positioning System GPS Product specification SAA1575HL baseband processor ALE internal signals ue address bus WRH WRL DMCS The timing is configurable under firmware control 7 4 2 CODE MEMORY SPACE The SAA1575HL has no internal code memory The GPS solution firmware resides in external memory With the standard Philips firmware a ROM with a maximum access time of 100 ns is required The classic operation of a multiplexed address data bus involves an address being set up for every bus cycle The internal ALE signal is used to latch the address prior to the cycle on which the data is set up An example of the resulting timing is illustrated in Fig 5 The SAA1575HL does not require an internal ALE cycle for each code fetch The lowest 3 address lines are not multiplexed with the data lines and so these can be used to incrementally read code locations 1999 Jun 04 Fig 4 Example of external data write standard firmware 14 MHB463 The XA core can therefore issue up to 8 word reads through
47. er all conditions Optimum values of C Rp and Rs will depend on the crystal used However typical values would be C 20 pF Rp 1 MQ and Rg 200 The hardware places a restriction on the range of frequencies for which correct operation will occur 26 MHz lt fxrAL1 lt 32 MHz However the restriction on operating frequency imposed by the firmware is tighter than this The standard Philips firmware has been written on the assumption of a 30 MHz system clock frequency zb optional off chip i on chip E XTAL1 n l I System XTAL Rp OSCILLATOR clock optional i l I L1 C Rs XTAL2 l l MHB472 Fig 13 System clock oscillator circuit 1999 Jun 04 25 Philips Semiconductors Global Positioning System GPS baseband processor 7 9 2 RTC CLOCK XTAL3 If the on chip real time clock is required as with the standard Philips firmware a low frequency clock signal is required to run the clock The SAA1575HL is designed so that a standard 32 768 kHz watch crystal can be used for this purpose Since this is much slower than the system clock a much lower power is required to run just the real time clock allowing it to be powered from a low capacity battery when the main power supply fails As with the system clock there is an on chip oscillator so that only a few passive external components are required These would be an external crystal accompanied
48. ers and a watchdog timer To summarise the SAA1575HL has the following functional units e 16 bit 80051 XA microcontroller core e 2 kbytes words on chip SRAM 16 bit words e 8 GPS channel correlators e 2UARTS 8 general purpose l O lines 3 timer counters 1 real time clock e 1 watchdog timer e 1 power down reset controller The structure is based on a 16 bit microcontroller core operating on all other units as memory mapped peripherals and registers A 16 bit data bus and a 19 bit address bus are extended to external pins so that external data and program memory can be accessed On chip decoder circuits eliminate the need for external glue logic for external memory access Each of the 8 GPS channel correlators includes a carrier Numerically Controlled Oscillator NCO PN code generator phase rotator and low pass filter They correlate the local PN sequence with the digitized input GPS signal and generate the filtered correlation result for the microcontroller The firmware provided then generates a navigation solution and provides standard GPS data outputs to the user Philips Semiconductors Product specification Global Positioning System GPS baseband processor SAA1575HL The GPS firmware is located in off chip program memory It processes the GPS signals from up to 8 satellites and generates GPS information that can be output to the host processor through one of the two serial ports Much of hardware configuration o
49. f only a 1 bit IF input is available this input should be held HIGH LSB IF input LSB of the 2 bit GPS digital IF signal input Clocked in on the rising edge of SCLK GPIO bit 2 standard general purpose I O mapped into the segment 15 of the address space The top 4 bits can be used as the XA external timer control access pins TO T1 T2 and T2EX GPIO bit 1 standard general purpose I O mapped into the segment 15 of the address space The top 4 bits can be used as the XA external timer control access pins TO T1 T2 and T2EX GPIO bit 0 standard general purpose I O mapped into the segment 15 of the address space The top 4 bits can be used as the XA external timer control access pins TO T1 T2 and T2EX Not connected do not connect Reference clock input from the TXCO reference Not used internally This is divided under firmware control to produce the sample clock SCLK used to gate the IF inputs Test pin connect to pin 100 Test pin connect to pin 99 1999 Jun 04 10 Philips Semiconductors Product specification Global Positioning System GPS baseband processor SAA1575HL EE S858 JITEREEHHHHE ITE PHP SSESGSGEREREESGESLERER OLE ES S lgl le l5 S S S SS S S S S ls 2l 18 13 j S e 8 fel SCLK O 75 XTAL4 74 PWRFAIL 73 DMCS 72 VCC R GPIO7 5 71 Vss GPIO6 6 70 D0 GPIO5 7 69 D1 68 D2 67 D3 66 VCC core 65 Vss VCC core 64 D4 SAA157
50. f the SAA1575HL can be controlled by the firmware and so details such as the external bus timing may change between firmware revisions For the purpose of this document the standard Philips firmware has been assumed release HDOO 3 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS core supply voltage peripheral supply voltage real time clock core supply voltage backup peripheral supply voltage core supply current normal mode sleep mode real time clock core supply current Rrc 32 768 kHz backup peripheral supply current normal mode dependent on load sleep mode peripheral supply current normal mode ee eg oscillator frequency 26 ambient temperature 4 ORDERING INFORMATION PACKAGE NUMBER NAME DESCRIPTION VERSION SAA1575HL LQFP100 plastic low profile quad flat package 100 leads body 14 x 14 x 1 4 mm SOT407 1 1999 Jun 04 4 Philips Semiconductors Product specification Global Positioning System GPS baseband processor SAA1575HL 5 BLOCK DIAGRAM 80C51XA PROCESSOR MODULE TXDO RXDO TXD1 RXD1 STATIC RAM 80C51XA 2 kbytes WORDS CORE lt gt TIMER 0 1 XTAL1 SYSTEM CLOCK MERE XTAL2 GENERATOR ADDRESS gt WATCHDOG AND TIMER DATA 48 49 53 to 59 62 to 64 67 to 70 D15 to DO 10 11 18 to 24 27 to 29 32 to 36 39 40 WAHA 45 A19 to A1 EXTERNAL BUS 41 Sess WREX INTERFACE sa T EMGS Dos gt DMCS RD lt CORR
51. firmware and interrupts 7 2 The 80C51XA processor The microcontroller core in the SAA1575HL is a Philips design called the XA eXtended Architecture which is an extended 80C51 like 16 bit microcontroller This is largely compatible with the 8051 but with various improvements The main features of the XA compared to the 8051 can be summarized as follows e 16 bit versus 8 bit data processing e 20 bit versus 16 bit address bus e 3 clock instruction cycle versus 12 clock instruction cycle e 10 Mips versus 1 Mips e 20 CPU registers versus 1 accumulator All 20 CPU registers in the XA can be used as the accumulator register in the 8051 e 16 x 16 multiplication in 12 clocks 3246 division in 22 clocks e New type of instructions such as normalization sign extension and trap Multi tasking support versus no multi tasking support 7 3 The GPS correlators The correlator block forms the GPS specific hardware for correlating with the direct sequence spread spectrum GPS signals The 8 identical correlators share the 2 bit IF input and the sample clock of the Analog to Digital Converter ADC of the front end The input signal is the 50 bits s GPS data spread by the 1 023 Mbits s PN code and modulated by the residual carrier The residual carrier frequency is composed of the Doppler frequency and the receiver local oscillator frequency offset To recover the GPS data and find the accurate timing of the received data for GPS navi
52. gation from the low level as low as 130 dBm GPS signal the residual carrier frequency and phase have to be found by a Phase Locked Loop PLL with minimum tracking phase error The starting position of the PN code in the received signal is found by correlation within a Delay Locked Loop DLL The channel correlator includes a local numerically controlled oscillator and a programmable local PN code generator with the phase rotation and correlation circuit Philips Semiconductors Global Positioning System GPS baseband processor 7 4 Memory organization The memory space in the SAA1575HL is configured in a Harvard architecture which means that the code and data memory are organized in separate address spaces This section describes the SAA1575HL memory requirements 7 4 1 DATA MEMORY SPACE The SAA1575HL contains 2 kbytes words of internal data memory For correct firmware operation a further 32 kbytes words of external data memory is needed with a maximum access time of 100 ns XTAL1 ALE data address bus DMCS The timing is configurable under firmware control Product specification SAA1575HL The specifications of this external memory are firmware dependent The figures given in this document are for the standard Philips firmware With other revisions of firmware the timings could differ by integer numbers of XTAL1 clock cycles In the SAA1575HL all of the data read and write cycles are prec
53. ification Global Positioning System GPS baseband processor SAA1575HL Table 5 Component list for GPS demonstration board COMPONENT CHARACTERISTICS COMPONENT B101 Lithium battery 3 V 170 mAh CR1 3 C105 C106 C201 to C204 ceramic capacitor 100 nF 50 V 20 603 C109 and C116 tantalum capacitor 10 uF 16 V 2096 C112 ceramic capacitor 470 nF 63 V 2096 C205 C206 and C325 ceramic capacitor 27 pF 50 V 596 C210 to C224 C328 to C337 and C346 ceramic capacitor 33 nF 63 V 1096 C301 ceramic capacitor 82 pF 50 V 596 C304 C305 C307 C308 and C347 not loaded C306 ceramic capacitor 0 47 pF 50 V 0 1 pF C309 ceramic capacitor 18 pF 50 V 596 C310 ceramic capacitor 68 pF 50 V 596 C313 and C314 ceramic capacitor 36 pF 50 V 596 C315 and C316 ceramic capacitor 6 8 pF 50 V 0 25 pF C319 ceramic capacitor 39 pF 50 V 596 C321 ceramic capacitor 0 27 pF 50 V 0 1 pF C324 ceramic capacitor 1 5 pF 50 V 0 25 pF C838 0398 C339 ceramic capacitor 4 7 pF 50 V 0 25 pF C341 ceramic capacitor 3 9 nF 50 V 10 C344 ceramic capacitor 10 nF 50 V 10 6 D101 to D104 LL4007 diode equivalent to 1N4007 D201 SMD diode BAS 16 SOT23 1999 Jun 04 47 Philips Semiconductors Product specification Global Positioning System GPS baseband processor SAA1575HL COMPONENT CHARACTERISTICS TOLERANCE PACKAGE Alpha SMV1204 133 SOT23 varactor L301 and L302 SMD inductor 22 uH 596 1008
54. nd the off chip memories is controlled by a block known as the external bus interface In addition certain chip enable signals are decoded within the block to reduce the amount of external glue logic required in the complete system The address latch normally required on 80C51 systems is implemented within the SAA1575HL Therefore no ALE signal is seen outside the IC and address and data lines are brought out on separate pins Product specification SAA1575HL However since internally there is still the need to latch the address from a common address data bus signals on the data bus will be seen to change during the address set up cycles The lower 3 external address lines are driven directly by the XA core and are not latched This allows burst code reads to be performed in which adjacent code locations are accessed without the need for an address latch cycle Signals similar to those used by a standard 80C51 or XA system are used to control the external bus activity to MMRS XA A3 to A1 AitoA8 D15toD0 ENABLE A A 16 ADDRESS eae DECODER CS 16 A4 to A19 ADDRESS LATCH i 16 D15to DO 3 gt A3 to Al WRH WRL RD gt WRH WRL RD gt PMCS PMCS 1999 Jun 04 MHB469 Fig 10 SAA1575HL internal address and data routing Philips Semiconductors Global Positioning System GPS baseband processor 7 7 1 PROGRAM MEMORY CHIP SELECT This signal PMC
55. ory data bus bit 5 16 bit data bus used to connect to external RAM and program memory D4 Vss External memory data bus bit 4 16 bit data bus used to connect to external RAM and program memory Ground 0 V reference Vcc core 57 58 59 60 61 ES 63 64 65 66 i Co N O N Main core power supply 2 7 to 3 6 V only main supply for the core in normal operation External memory data bus bit 3 16 bit data bus used to connect to external RAM and program memory External memory data bus bit 2 16 bit data bus used to connect to external RAM and program memory g e o External memory data bus bit 1 16 bit data bus used to connect to external RAM and program memory External memory data bus bit 0 16 bit data bus used to connect to external RAM and program memory 1999 Jun 04 Ground 0 V reference Philips Semiconductors Global Positioning System GPS Product specification SAA1575HL baseband processor SYMBOL DESCRIPTION Vcc n Backup core power supply 2 4 to 3 6 V only Separate from the core supply to allow a low capacity battery to be used to maintain the Real Time Clock RTC function This should be powered from the main supply during normal operation and switched to battery backup when the main supply fails External data memory select external RAM select pin active LOW when the external data memory space is addressed This output is driven from Vccr and V
56. re a high supply current state a processor crash or RTC register corruption FUNCTION PWRDN controlled by the RSTIME input PWRFAIL Power down indicator this should be driven LOW by an external comparator to indicate impending power failure Internally it sends an interrupt to the processor used to initiate a power fail routine At the end of this routine the standard firmware forces the processor into reset This also inhibits the external RAM chip select Reset is only de asserted a set time after both PWRDN and PWRFAIL go HIGH Power fail indicator this should be driven LOW by an external comparator to indicate immediate power failure Internally it forces immediate reset of the processor isolation of the RTC and inhibition of the external RAM chip select It also controls the power switch outputs PWRB and PWRM Reset is only de asserted a set time after both go HIGH controlled by the RSTIME input RSTIME Reset timer control this sets the time delay between de assertion of both PWRDN and PWRFAIL and the de assertion of the processor reset If HIGH the delay is approximately 10 ms If LOW the delay is approximately 10 us External RAM chip select this is driven via the backup supplied core and pads In power down this is isolated from the rest of the IC and the output held HIGH to prevent corruption of the external RAM DMCS Main power supply control in normal operation this is held LOW This can be used to swit
57. rent typ when 8 GPS channels in track approximate 2 GENERAL DESCRIPTION The SAA1575HL is an integrated circuit which implements a complete baseband function for Global Positioning System GPS receivers It combines a 16 bit Philips 80C51XA microcontroller 8 GPS channel correlators and related peripherals in a single IC Users can implement a complete GPS receiver using only the SAA1575HL the UAA1570HL front end Philips IC or similar external memory and a few discrete components The IC is aimed at low cost applications A low power solution was also used where possible although this was of secondary importance to cost The core of the SAA1575HL operates at 3 V 1999 Jun 04 Product specification SAA1575HL However for compatibility with current automotive applications the periphery is supplied from separate pins and can be operated between 3 and 5 V as required The function of the SAA1575HL is to read the 1 or 2 bit sampled IF bitstream from a front end IC and under control of firmware on an external ROM calculate the full GPS solution The results are communicated to a host in National Maritime Electronics Association NMEA format via a standard serial port A second serial port can be used to provide differential GPS information to the processor for more advance applications In addition various other functions are integrated onto the IC such as a real time GPS clock a power down reset controller timer count
58. roperty rights Printed in The Netherlands 285002 02 pp56 Philips Semiconductors Date of release 1999 Jun 04 Document order number 9397 750 06055 Lott make things bette S PHILIPS
59. routine 1999 Jun 04 x9 VCC core N 7 PWRDN PWRFAIL reset timer delay set by RSTIME o MHB471 Fig 12 Example of power down strategy with fast supplies Philips Semiconductors Global Positioning System GPS baseband processor 7 8 3 SYSTEM RESET CONTROL The SAA1575HL contains an internal timer and control logic to perform various system reset tasks Control of this logic is by three external pins PWRDN PWRFAIL and RSTIME This allows the system designer to set the voltage thresholds at which the system goes into and comes out of reset 7 8 3 1 The reset timer The heart of the reset system is a 20 bit counter with asynchronous reset clocked from the XTAL1 system clock The reset counter is asynchronously reset if the PWRFAIL pin is LOW Once reset the counter will only be enabled once both PWRFAIL and PWRDN go HIGH This prevents the SAA1575HL from leaving the reset state until both power detect inputs have flagged the power system as healthy The internal reset signal is generated by decoding the reset counter The decode value and hence the time delay is controlled by the reset time control pin RSTIME Table 3 Reset time control NUMBER OF RSTIME CYCLES BEFORE TIME DELAY INPUT RESET fxraL1 30 MHz DE ASSERTED 1 294912 9 8 ms 0 288 9 6 us The internal reset is de asserted a given number of XTAL1 clock cycles after PWRFAIL and PWRDOWN go HIGH It i
60. s suggested that for most applications RSTIME should be held HIGH giving a reset time of approximately 10 ms This would be needed to allow the on chip oscillator to stabilize after power up The shorter reset time can be used for applications using an external XTAL1 clock signal which does not need a long stabilization period It is important that PWRFAIL should be LOW during power up of the IC to give the correct reset 1999 Jun 04 24 Product specification SAA1575HL 7 8 3 2 Overall reset operation The assertion of the reset signal by means already described will cause the following to occur e Internal XA processor reset Internal registers reset Data bus pins set to be inputs Read and write strobes de asserted GPIO pins set to be inputs On chip XTAL1 oscillator enabled 7 8 9 8 CPU reset operation Assuming that the correct external PWRFAIL sequence is generated on power up the internal XA will receive the correct reset signal from the on chip reset block If the proper PWRFAIL is not performed the operation of the on chip reset block cannot be guaranteed and the XA may fail wholly or in part The embedded XA requires a minimum length of reset to complete the various tasks This minimum length is guaranteed by the on chip reset block The only restriction on the length of the pulse is that is should be long enough to be asynchronously detected by the SAA1575HL typically 10 ns The embedded CPU can also
61. seband processor SAA1575HL SYMBOL PARAMETER CONDITIONS MIN 1 0 pins WRL WRH and RD V LOW level input voltage V HIGH level input voltage IL IH VoL LOW level output voltage lo 4 0 mA VoH CL max maximum load capacitance tat transition delay HIGH level output voltage lon 1 0 mA 2 4 ldrive max Maximum drive current I O pull up pins D15 to D0 and GPIO7 to GPIOO Vit LOW level input voltage Vin HIGH level input voltage LOW level output voltage Vou HIGH level output voltage maximum drive current CL max maximum load capacitance transition delay pull up current Notes 1 XTAL1 XTAL2 XTAL3 and XTAL4 are not specified with respect to levels 2 Depends on all the external circuit driven by outputs 3 Specified at RTC clock frequency of 32 768 kHz 1999 Jun 04 29 Philips Semiconductors Product specification Global Positioning System GPS baseband processor SAA1575HL 11 AC CHARACTERISTICS Vcc P Vcc B 25V VCCtcore Vcc R 3 V Tamb 20 C fose 30 MHz standard Philips firmware release HD00 unless otherwise specified SYMBOL PARAMETER CONDITIONS External clock oscillator frequency 26 30 clock period and CPU timing cycle 33 3 clock HIGH time 40 to 60 duty cycle clock LOW time 40 to 60 duty cycle 6 7 clock rise time 5 clock fall time 5 folk ret reference clock frequency 14 4 MHz External program memory rea
62. sequential code memory for each ALE cycle This is termed a burst code read An example of the resulting timing is illustrated in Fig 6 Any type of branch or jump in the program may require a code fetch in a non sequential manner and a new ALE cycle will be needed This may occur at any stage ina code read Thus the length of the read strobe in a burst read is not necessarily an integer multiple of the individual code read length Philips Semiconductors Product specification Global Positioning System GPS SAA1575HL baseband processor The timing is configurable under firmware control ALE nme internal signals data PMCS MHB464 Fig 5 Example of code read with ALE standard firmware XTAL1 ALE address data address bus PMCS DATA BUS zb qr succo du cL internal signals MHB465 The timing is configurable under firmware control Fig 6 Example of burst mode code read standard firmware 1999 Jun 04 15 Philips Semiconductors Global Positioning System GPS baseband processor 7 5 The SAA1575HL contains the hardware for 3 timers 2 UARTS a watchdog timer a 3 bit RF IC programming link and an 8 bit general purpose l O port CPU peripheral features 7 5 1 The SAA1575HL has 2 standard 16 bit timer counters and a third 16 bit up down timer counter These timer event counters can perform the following functions
63. time by the processor and enables fast re acquisition a warm start of satellites after power has been switched off A separate supply pin is provided to allow the RTC to be powered while the rest of the IC is turned off The block diagram of the SAA1575HL is shown in Fig 1 The IC consists of a processor core its associated peripherals some internal memory and a series of GPS correlators The processor core is based on an embedded Philips 80C51XA known as the XA The XA peripherals UARTS timers watchdog and general purpose l Os are termed special function registers and are memory mapped in parallel with an area of the data memory They are connected to the core by dedicated data and address buses The internal data memory is also connected to the core by a dedicated bus The rest of the IC the correlators RTC and system control is mapped into the external data memory space The multiplexed data and address buses provided by the XA core are separated by an on chip latch to provide the distinct 16 bit data bus and 19 bit address bus These are made available externally for connection to external memory via the external bus interface The correlators RTC and system control blocks are memory mapped into the highest page of the 16 pages in the XA data structure 1999 Jun 04 12 Product specification SAA1575HL Both the RTC and the correlators are asynchronous to the system clock with synchronization being achieved by
64. ttery to be used to maintain the low power RTC function The timebase for the RTC should be provided by a dedicated 32 768 kHz crystal which can be omitted if the RTC is not required This is divided down by a fixed divider to provide the 1 Hz timebase used for the rest of the RTC block A digital sampling circuit is also included to prevent digital noise due to the on chip processor causing incorrect timekeeping The real time clock Product specification SAA1575HL The SAA1575HL uses a digital under sampling system to ensure that ground bounce does not cause RTC timekeeping errors This places a restriction on the ratio of XTAL1 and XTAL3 frequencies for which the RTC will operate correctly This has been optimistic for the case fxraL1 30 MHZ fxrALa 32 kHz and assuming that the RTC crystal frequency will always be 32 kHz will operate correctly for the entire specified range of system frequencies XTAL4 I off chip l _ XTAL3 ue T 4 7 I XTAL OSCILLATOR optional l I E I I SAMPLER system clock REAL TIME CLOCK COUNTERS PRE SCALER MHB468 Fig 9 Real time clock circuit 1999 Jun 04 18 Philips Semiconductors Global Positioning System GPS baseband processor 7 7 The external bus The off chip memories and the on chip registers are on the same address and data bus The routing of the data and address signals between the on chip registers a

philips SAA1575HL Global Positioning System (GPS) baseband processor handbook

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