National Semiconductor DS90C383/DS90CF384 +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link 65 MHz +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link 65 MHz
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1. U U U lt C lt lt 2 Z O 212 OJO Z O Z O DS90CF384 MTD56 TSSOP Package Pin Description FPD Link Receiver Pin Name RxIN RxIN RxOUT RxCLK IN RxCLK IN FPSHIFT OUT PWR DOWN Voc GND PLL PLL GND LVDS Vec LVDS GND Description Positive LVDS differential data inputs Negative LVDS differential data inputs TTL level data outputs This includes 8 Red 8 Green 8 Blue and 4 control lines FPLINE FPFRAME DRDY also referred to as HSYNC VSYNC Data Enable Positive LVDS differential clock input Negative LVDS differential clock input TTL level clock output The falling edge acts as data strobe Pin name RxCLK OUT TTL level input When asserted low input the receiver outputs are low Power supply pins for TTL outputs Ground pins for TTL outputs Power supply for PLL Ground pin for PLL Power supply pin for LVDS inputs Ground pins for LVDS inputs DS90CF384 64 ball FBGA Package Pin Description FPD Link Receiver Pin Name RxIN RxIN RxOUT RxCLK IN RxCLK IN FPSHIFT OUT PWR DOWN Voc GND PLL Vec PLL GND LVDS Vac Description Positive LVDS differential data inputs Negative LVDS differential data inputs TTL level data outputs This includes 8 Red 8 Green 8 Blue and 4 control lines FPLINE FPFRAME DRDY also referred to as HSYNC VSYNC Data Enable Positive LVDS di2. 9 o mw 1 o 1 No No 9 oum o uwe P mM 1 mw 1 o ms 1 we mw 1 _ mv 1 mie 1 wo ma ns No No mw 1 mw 1 1 NW 1 1 mia 1 _ 1 olw wojo rm 0 1 TY mim m1 0 BR RI A N TI ITI a Oe ee nm CO N NIN oy oy Bl Rl Oo MIN oO bari LVDS GND LVDS GND LVDS GND PLL GND PLL GND PWR DWN R FB TxCLKIN TxINO TxIN1 TxIN2 TxIN3 TxIN5 TxIN6 TxIN7 TxIN8 TxIN9 TxIN10 TxIN1 1 TxIN12 TxIN13 TxIN14 TxIN15 TxIN16 TxIN17 TxIN18 TxIN19 TxIN20 TxIN21 TxIN22 TxIN23 TxIN24 TxIN25 TxIN26 TxIN27 TxCLKOUT TxCLKOUT TxOUTO TxOUTO TxOUT1 TXOUT 1 TxOUT2 TxOUT2 TxOUT3 TxOUT3 LVDS VCC LVDS VCC U UlO O O O O O O 0 QO 09 DS90C383SLC SLC64A FBGA Package Pin Description FPD Link Transmitter Continued e P wi 1 Hb Na m ws 1 Ground Input Output P Power NC No Connect By Pin TxIN23 TxIN19 By Pin Type PLL VCC O N
3. Worst Case 3 www national com 86420650 6862065 0 DS90C383 DS90CF384 Electrical Characteristics continued Over recommended operating supply and temperature ranges unless otherwise specified TRANSMITTER SUPPLY CURRENT Figures 1 3 TA f 65 MHz 42 55 mA 40 C to 485 C ICCTG Transmitter Supply Current R 1000 32 5 MHz NM Edd mA C 5 pF 16 Grayscale 16 Grayscale Pattern f 37 5 MHz NES Figures 2 3 Ta f 65 MHz mA 40 C to 85 C ICCTZ Transmitter Supply Current Power Down Low Power Down Driver Outputs TRI STATE under Power Down Mode RECEIVER SUPPLY CURRENT ICCRW Receiver Supply Current C 8pF f 325MHz 49 65 mA Worst Case Worst Case Pattern f 2 37 5 MHz ne mA 40 C to 85 C ICCRG Receiver Supply Current f 325MHz 28 45 16 Grayscale 16 Grayscale Pattern ME CON mA Figures 2 4 f 65 MHz mA 40 C to 85 C ICCRZ Receiver Supply Current Power Down Low uA Power Down Receiver Outputs Stay Low during Power Down Mode Note 1 Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed They are not meant to imply that the device should be operated at these limits The tables of Electrical Characteristics specify conditions for device operation Note 2 Typical values are given for Voc 3 3V and 25 Note 3 Current into d
4. 2000 National Semiconductor Corporation D590C383 1 0 November 2000 National Semiconductor DS90C383 DS90CF384 3 3V Programmable LVDS Transmitter 24 Bit Flat Panel Display FPD Link 65 MHz 3 3V LVDS Receiver 24 Bit Flat Panel Display FPD Link 65 MHz General Description DS90C383 transmitter converts 28 bits of LVCMOS LVTTL data into four LVDS Low Voltage Differential Signal ing data streams A phase locked transmit clock is transmit ted in parallel with the data streams over a fifth LVDS link Every cycle of the transmit clock 28 bits of input data are sampled and transmitted The DS90CF384 receiver con verts the LVDS data streams back into 28 bits of LI VCMOS LVTTL data At a transmit clock frequency of 65 MHz 24 bits of RGB data and 3 bits of LCD timing and control data FPLINE FPFRAME DRDY are transmitted at a rate of 455 Mbps per LVDS data channel Using a 65 MHz clock the data throughputs is 227 Mbytes sec The transmitter is of fered with programmable edge data strobes for convenient interface with a variety of graphics controllers The transmit ter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin A Rising edge trans mitter will inter operate with a Falling edge receiver DS90CF384 without any translation logic Both devices are also offered in a 64 ball 0 8mm fine pitch ball grid array FBGA package which provides a 44 96 reduction in PCB
5. 1 5V POWER DOWN RxCLK IN RxOUT Low DS012887 18 FIGURE 16 Receiver Power Down Delay Previous Cycle i Next Cycle TxiN5 1 Y TxIN27 1 TxIN 15 TxIN6 TxIN 14 TxIN9 1 TxIN18 TxIN1 1 TxINO 1 TxIN7 J i i 0 1 TPPos2 TPPos3 TPPos4 TPPos5 TPPos6 FIGURE 17 Transmitter LVDS Output Pulse Position Measurement DS012887 26 DS90C383 DS90CF384 e x e 5 5 5 S 2 E E 6 amp iming RxCLK IN Differential AC T Rspos6 min Rspos6 max Rspos5 RsposS max Rspos4 min Rspos4 max Rspos3 min Rspos3 max Rspos2 min Rspos2 max 50 min 0 max Rs Rs DS012887 25 FIGURE 18 Receiver LVDS Input Strobe Position www national com 11 DS90C383 DS90CF384 AC Timing Diagrams Continued Ideal Strobe Position RxIN or RxIN 1 RxIN RxIN 1 0V Tpposn min max 1 DS012887 21 C Setup and Hold Time Internal data sampling window defined by Rspos receiver input strobe position min and max Tppos Transmitter output pulse position min and max RSKM Cable Skew type length Source Clock Jitter cycle to cycle Note 10 ISI Inter symbol interference Note 11 Cable Skew typically 10 ps 40 ps per foot media dependent Note 1
6. ap support nsc com www national com Frangais Tel 33 0 1 41 91 8790 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications
7. 0 Cycle to cycle jitter is less than 250 ps at 65 MHZ Note 11 ISI is dependent on interconnect length may be zero FIGURE 19 Receiver LVDS Input Skew Margin Applications Information The DS90C383 and DS90CF384 are backward compatible with the existing 5V FPD Link transmitter receiver pair DS90CR583 DS90CR584 DS90CF583 and DS90CF584 To upgrade from a 5V to a 3 3V system the following must be addressed 1 Change 5V power supply to 3 3V Provide this supply to the Voc LVDS Vec and Vec of both the transmitter and receiver devices This change may enable the re moval of a 5V supply from the system and power may be supplied from an existing 3V power source 2 The DS90C383 transmitter incorporates a rise fall strobe select pin This select function is on pin 17 formerly a Voc connection on the 5V products When the rise fall strobe select pin is connected to Vec the part is configured with a rising edge strobe In a system cur rently using a 5V rising edge strobe transmitter DS90CR583 no layout changes are required to ac commodate the new rise fall select pin on the 3 3V transmitter The signal may remain at pin 17 and the device will be configured with a rising edge strobe When converting from a 5V falling edge transmitter DS90CF583 to the 3V transmitter a minimal board layout change is necessary The 3 3V transmitter will not be configured with a falling edge strobe if re mains connected to the s
8. FIGURE 9 0590 383 Transmitter Clock In to Clock Out Delay Falling Edge Strobe RxCLK IN RxCLK OUT 5012887 12 FIGURE 10 DS90CF384 Receiver Clock In to Clock Out Delay 3 0V POWER DOWN 3 0V e TPLLS e 3V TxCLK IN a FIGURE 11 DS90C383 Transmitter Phase Lock Loop Set Time POWER DOWN RxCLK IN RxCLK OUT DS012887 14 FIGURE 12 DS90CF384 Receiver Phase Lock Loop Set Time www national com 8 AC Timing Diagrams continued TxCLK OUT RxCLK IN Differential TxOUT RxIN Single Ended TxCLK OUT RxCLK IN Differential TxOUT3 RxIN3 Single Ended TxOUT2 RxIN2 Single Ended TxOUT 1 RxIN 1 Single Ended TxOUTO RxINO Single Ended FIGURE 13 Seven Bits of LVDS in Once Clock Cycle Previous Cycle TxIN5 1 TxIN23 TxIN17 TxIN16 TxIN 1 1 TxIN 10 TxINS TxIN27 DS012887 15 TxIN26 TxIN25 TxIN24 TxIN22 TxIN21 TxIN20 TxIN19 TxIN9 1 TxIN8 1 TxIN18 TxIN 15 TxIN 14 TxIN13 TxIN 12 9 TxIN8 TxINO 1 TxIN7 FIGURE 14 21 Parallel TTL Data Inputs Mapped to LVDS Outputs PWR DWN TxCLK TxOUT FIGURE 15 Transmitter Power Down Delay TxINO DS012887 16 www national com 86420650 6862065 0 DS90C383 DS90CF384 AC Timing Diagrams Continued TxCLK OUT Differential TxOUT3 Single Ended TxOUT2 Single Ended TxOUT 1 Single Ended TxOUTO Single Ended www national com
9. G Gd Gd G o DS90CF384 64 ball FBGA Package Pin Definition Link Receiver Continued By Pin moms o m w 1 m 1 Fo mo uwo P m we Gi mos o ag w am o 5 mw 1 G6 1 7 o d 1 a 1 Ground Input Output P Power NC Not Connect 17 By Pin Type tvs veo uve ___ vwe voc v v v DU www national com 86420650 6862065 0 DS90C383 DS90CF384 Pin Diagrams for TSSOP Packages DS90C383MTD DS90CF384MTD Vec RxOUT21 RxOUT20 RxOUT19 GND RxOUT18 RxOUT17 RxOUT16 Vec RxOUT15 RxOUT 14 RxOUT13 GND RxOUT 12 RxOUT 1 RxOUT10 Vec RxOUT9 RxOUT8 RxOUT7 GND RxOUT6 RxOUT5 RxOUT4 RxOUT3 Vec RxOUT2 RxOUT 1 TxIN4 RxOUT22 TxIN3 RxOUT23 TxIN2 RxOUT24 GND GND TxIN 1 RxOUT25 TxINO RxOUT26 TxIN27 RxOUT27 LVDS GND LVDS GND TxOUTO RxINO TxOUTO RxINO TxOUT1 RxIN1 TxOUT1 RxIN1 LVDS Veg LVDS Vec LVDS GND LVDS GND TxOUT2 RxIN2 TxOUT2 RxIN2 TxCLKOUT RxCLKIN TxCLKOUT RxCLKIN TxOUT3 RxIN3 TxOUT3 RXIN3 LVDS GND LVDS GND PLL GND PLL GND PLL Voc PLL Vec PLL GND PLL GND PWR DWN PWR DWN TxCLK IN RxCLK OUT TxIN26 RxOUTO GND GND DS012887 22 DS012887 23 TABLE 1 Program
10. Mbit s 8 7 On Each LVDS BLU Channel 24 FPLINE HSYNC E FPFRAME VSYNC DRDY DATA ENABLE CNTL FPSHIFT IN CLOCK LVDS TRANSMIT CLOCK IN 20 MHz To 65 MHz 20 MHz To 65 MHz POWER DOWN DS012887 1 Order Number DS90C383MTD or DS90C383SLC See NS Package Number MTD56 or SLC64A DS90CF384 DATA LVDS CMOS TTL OUTPUTS RED 8 GRN 140 Mbit s To 455 Mbit s On Each LVDS 8 Channel BLU FPLINE HSYNC FPFRAME VSYNC DRDY DATA ENABLE CNTL CLOCK LVDS 20 MHz To 65 MHz RECEIVER CLOCK OUT POWER DOWN DS012887 24 Order Number DS90CF384MTD DS90CF384SLC See NS Package Number MTD56 or SLC64A www national com 2 Absolute Maximum Ratings note 1 If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office DS90CF384MTD 12 4 mW C above 25 C Maximum Package Power Dissipation Capacity 25 C SLC64A Package Distributors for availability and specifications DS90C383SLC 20W Supply Voltage 0 3V to 44V 2 0 CMOS TTL Input Voltage 0 3 to 0 3V Package Derating CMOS TTL Output Voltage 0 3V to Vac 0 3V DS90C383SLC 10 2 mW C above 25 C LVDS Receiver Input Voltage 0 3V to 0 3V DS90CF384SLC 10 2 mW C above 25 C LVDS Driver Output Voltage 0 3V to Voc 0 3V LVDS Output Short Circuit ESD Rating Duration Continuous HBM 1 5 kO 100 pF gt 7 Junction Temperature 150 C Recommen
11. OS TTL Low to High Transition Time Figure 4 22 50 ns CHLT CMOS TTL High to Low Transition Time Figure 4 22 50 ns RSPos0 65 M2 RSPos3 73 77 RSPos6 RSKM Skew Margin Note 5 Figure 19 f265MHz 40 ps RCOP RxCLK OUT Period Figure 8 ns RCOH RxCLK OUT High Time Figure 8 f 65MHz 73 86 ns RCOL RxCLK OUT Low Time Figure 8 345 49 ms RSRC RxOUT Setup to RxCLK OUT Figure 8 25 69 m RHRC RxOUT Hold to RxCLK OUT Figure 8 25 57 RCCD RxCLK IN to RxCLK OUT Delay 25 C 3 3V Figure 10 50 71 90 ns HPLES Receiver Phase Lock Loop Set Figure 12 O J ms RPDD Receiver Power Down Delay Figure 16 dq 44 Us Note 5 Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs This margin takes into account the transmitter pulse positions min and max and the receiver input setup and hold time internal data sampling window RSPOS This margin allows for LVDS interconnect skew inter symbol interference both dependent type length of cable and clock jitter less than 250 ps AC Timing Diagrams TxCLK IN RxCLK OUT ODD TxIN RxOUT EVEN TxIN RxOUT DS012887 3 FIGURE 1 Worst Case Test Pattern 5 www national com 86420650 6862065 0 DS90C383 DS90CF384 AC Timing Diagrams Continued Device Pin Name Signal Signal Pattern Signa
12. TL I O Note 7 The 16 grayscale test pattern tests device power consumption for a typical LCD display pattern The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display Note 8 Figures 1 2 show a falling edge data strobe TxCLK IN RxCLK OUT Note 9 Recommended pin to signal mapping Customer may choose to define differently 80 Differential 20 LHLT DS012887 5 FIGURE 3 DS90C383 Transmitter LVDS Output Load and Transition Times CMOS TTL Output g CHLT DS012887 6 FIGURE 4 DS90CF384 Receiver CMOS TTL Output Load and Transition Times DS90CF384 www national com 6 AC Timing Diagrams Continued TxCLK IN DS012887 7 FIGURE 5 DS90C383 Transmitter Input Clock Transition Time TxOUTO rom TOO v 00 TxCLK OUT TIME DS012887 8 Measurements at TCCS measured between earliest and latest LVDS edges TxCLK Differential Low gt High Edge FIGURE 6 DS90C383 Transmitter Channel to Channel Skew Sample on H L Edge TxCLK IN TxIN 0 27 DS012887 9 FIGURE 7 DS90C383 Transmitter Setup Hold and High Low Times Falling Edge Strobe RxCLK OUT RxOUT 0 27 DS012887 10 FIGURE 8 DS90CF384 Receiver Setup Hold and High Low Times www national com 86420650 6862065 0 DS90C383 DS90CF384 AC Timing Diagrams Continued TxCLK IN TxCLK OUT 05012887 11
13. ded Operating Storage Temperature 65 to 150 C Lead Temperature Conditions Soldering 4 sec for TSSOP 260 C Solder Reflow Temperature Min Nom Units 20 sec for FBGA 220 C Supply Voltage Vcc 3 0 3 3 3 6 V Maximum Package Power Dissipation Capacity 25 C Operating Free Air MTD56 TSSOP Package Temperature T4 40 25 85 C DS90C383MTD 1 63 W Receiver Input Range 0 2 4 V DS90CF384MTD 1 61 W Supply Noise Voltage Voc 100 MV pp Package Derating DS90C383MTD 12 5 mW C above 25 C Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified LVCMOS LVTTL DC SPECIFICATIONS High Level put Votage Jo v Low Level Input Votage High Level Output Vonage ____ 27 38 Level Output Votlage ____ 93 input Clamp Vote ocasem Output Short Curent o Offset Voltage Note 4 Change in Vos between complimentary output states Output Short Circuit Current Vour 1000 __ gt 1 Output TRI STATE Current Power Down 10 Vour OV or Voc Differential Input High Threshold Vom 1 2V Differential Input Low Threshold Vin OV 56 r wsw 2 60 m Input Current TRANSMITTER SUPPLY CURRENT ICCTW Transmitter Supply Current 1000 C 5 pF Worst Case Pattern
14. elect pin To guarantee the 3 3V transmitter functions with a falling edge strobe pin 17 should be connected to ground OR left unconnected When not connected left open and internal pull down resistor ties pin 17 to ground thus configuring the trans mitter with a falling edge strobe 3 DS90C383 transmitter input and control inputs ac cept 3 3V TTL CMOS levels They are not 5V tolerant www national com 12 DS90C383 TSSOP Package Pin Description Link Transmitter Pin Name TxIN TxOUT TxOUT FPSHIFT IN R FB RTxCLK OUT TxCLK OUT PWR DOWN Voc GND PLL Voc PLL GND LVDS Vac LVDS GND DS90C383SLC SLC64A FBGA Package Pin Summary FPD Link Transmitter Pin Name TxIN TxOUT TxCLK OUT TxCLK OUT PWR DWN R FB Voc GND PLL Voc PLL GND LVDS Vac LVDS GND NC Description TTL level input This includes 8 Red 8 Green 8 Blue and 4 control lines FPLINE FPFRAME and DRDY also referred to as HSYNC VSYNC Data Enable Positive LVDS differential data output Negative LVDS differential data output TTL level clock input The falling edge acts as data strobe Pin name TxCLK IN Programmable strobe select Positive LVDS differential clock output Negative LVDS differential clock output TTL level input When asserted low input TRI STATES the outputs ensuring low current at power down Power supply pins for TTL inputs Ground pins for TTL inpu
15. evice pins is defined as positive Current out of device pins is defined as negative Voltages are referenced to ground unless otherwise specified except and AVop Note 4 previously referred as Transmitter Switching Characteristics Over recommended operating supply and 40 C to 85 C ranges unless otherwise specified Symbol Parameter Min Typ Units LLHT LVDS Low to High Transition Time Figure 3 075 15 ns LHLT LVDS High to Low Transition Time Figure 3 ____ 075 15 ms TCIT TxCLK IN Transition Time Figure 5 5 TCCS TxOUT Channel to Channel Skew Figure 6 250 ps TCIP TxCLK IN Period Figure 7 ns TCIH TxCLK IN High Time Figure 7 ns TCIL TxCLK IN Low Time Figure 7 ns TSTC TxIN Setup to TxCLK IN Figure 7 f 65 MHz 25 ns THTC TxIN Hold to TxCLK IN Figure 7 ns TCCD TxCLK IN to TXCLK OUT Delay 25 C 3 3V Figure 9 ns www national com 4 Transmitter Switching Characteristics continued Over recommended operating supply and 407 to 85 C ranges unless otherwise specified TPLLS Transmitter Phase Lock Loop Set Figure 11 10 ms TPDD Transmitter Power Down Delay Figure 15 o 4100 ns Receiver Switching Characteristics Over recommended operating supply and 407 to 85 C ranges unless otherwise specified Symbol Parameter Units CLHT CM
16. fferential clock input Negative LVDS differential clock input TTL level clock output The falling edge acts as data strobe Pin name RxCLK OUT TTL level input When asserted low input the receiver outputs are low Power supply pins for TTL outputs Ground pins for TTL outputs Power supply for PLL Ground pin for PLL Power supply pin for LVDS inputs 15 www national com 86420650 6862065 0 DS90C383 DS90CF384 DS90CF384 64 ball FBGA Package Pin Description FPD Link Receiver Continued Pin Name LVDS GND NC Vo 4 Ground pins for LVDS inputs 6 Pins not connected Description DS90CF384 64 ball FBGA Package Pin Definition FPD Link Receiver Pin www national com By Pin Pin Name o P mous o o o o o gt ours o o Boum o mou o o o o Cow Bow o o mous o Roms o o e o Boum o o P _ _ 9 o Ros o By Pin Type e muo es PWRDWN s M o Gs BN rs OJO O O OJO O OJOJO O O OJ O O O O OF OF
17. footprint compared to the TSSOP package This chipset is an ideal means to solve EMI and cable size problems associated with wide high speed TTL interfaces Block Diagrams Features 20 to 65 MHz shift clock support Programmable transmitter DS90C383 strobe select Rising or Falling edge strobe Single 3 3V supply Chipset Tx Rx power consumption 250 mW typ Power down mode 0 5 mW total Single pixel per clock XGA 1024x768 ready Supports VGA SVGA XGA and higher addressability Up to 227 Megabytes sec bandwidth Up to 1 8 Gbps throughput Narrow bus reduces cable size and cost 290 mV swing LVDS devices for low EMI PLL requires no external components Low profile 56 lead TSSOP package Also available in a 64 ball 0 8mm fine pitch ball grid array FBGA package Falling edge data strobe Receiver Compatible with TIA EIA 644 LVDS standard ESD rating gt 7 kV Operating Temperature 40 C to 85 C Typical Application DATA LVDS HOST GRAPHICS CONTROLLER LCD PANEL CONTROLLER CLOCK LVDS TRI STATES is a registered trademark of National Semiconductor Corporation 05012887 FPSHIFT OUT RxCLK OUT DS012887 2 www national com ZHIN 9 Ur dda Aejdsig l4 10105 2 782400650 28220658 DS90C383 DS90CF384 Block Diagrams continued DS90C383 CMOS TTL INPUTS DATA LVDS 8 RED 8 gt GRN e 140 Mbit s To 455
18. l Frequency TxCLKIN RxCLKOUT TxINO RxOUTO RO 1 16 mi EoU 81 007 TxIN2 Rx0UT2 R2 LC LT I LILTILTLTLTLTLTILTIL TxIN4 RxXOUT4 R4 _ Steady State Low TxIN5 RxOUT5 R7 Steady State Low TxIN6 RxOUT6 R5 Steady State Low TxIN7 RxOUT7 60 Steady State Low TxIN8 RxOUT8 G1 1 16 TxIN10 RxOUT10 G6 1 4 TxIN11 RxOUT11 67 LILILILILILILTIJTTL TxIN12 RxXOUT12 63 1 4 Steady State Low TXINT3 RXOUTI3 64 ___________________________________ Steady State Low Tx INTA RXOUTIA 65 Steady State Low TxIN15 RxOUT15 BO Steady State Low TxIN16 RxOUT16 B6 L 16 TxIN17 RxOUT17 B7 1 8 L TI LI L TxiNig RxouTt9 LYE LE LY LILI LP TxIN20 RxOUT20 835 Ly Steady State Low TxIN21 RXOUT21 84 _ steady State Low TxIN22 RxOUT22 B5 Steady State Low TxIN23 RxOUT23 RES Steady State Low TxIN24 RxOUT24 HSYNC mme sie Steady State High TxIN25 RxOUT25 5 Steady State High TxIN26 RxOUT26 EN Steady State High TxIN27 RxOUT27 R6 Steady State High DS012887 4 FIGURE 2 16 Grayscale Test Pattern Notes 6 7 8 9 Note 6 The worst case test pattern produces a maximum toggling of digital circuits LVDS I O and CMOS T
19. mable Transmitter Condton Strobe Status R FB FB Vec Rising edge strobe GND Falling edge strobe www national com 18 Physical Dimensions inches millimeters unless otherwise noted 0 1 DU 8 1 TITE 9 2 i 5 6 TYP 4 05 p o 2 EE EN __ _ _ 1 8 1 28 2 0 21 ALL LEAD TIPS n 0 3 TYP 0 5 LAND PATTERN RECOMMENDATION 0 90 7 SEE DETAIL A SS Se 7 2 NM 707 soena li 0 13 5 6 7 5 PLANE 39408 NN PLANE 0 6019 DETAIL TYPICAL MTD56 REV B 56 Lead Molded Thin Shrink Small Outline Package JEDEC Dimensions show in millimeters Order Number DS90C383MTD DS90CF384MTD NS Package Number MTD56 19 www national com 86420650 6862065 0 Physical Dimensions inches millimeters unless otherwise noted Continued A1 BALL PAD CORNER 4 Link 65 MHz 430 5 6 A1 BALL PAD CORNER LP d 1 2 TYP 0 8 r oc gt DIMENSIONS ARE IN MILLIMETERS SLC64A Rev B 64 ball 0 8mm fine pitch ball g
20. rid array FBGA Package Dimensions show in millimeters only Order Number DS90CF384SLC or DS90C383SLC NS Package Number SLC64A LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which a are intended for surgical implant support device or system whose failure to perform into the body or b support or sustain life and can be reasonably expected to cause the failure of whose failure to perform when properly used in the life support device or system or to affect its accordance with instructions for use provided in the safety or effectiveness labeling can be reasonably expected to result in a significant injury to the user DS90C383 DS90CF384 3 3V Programmable LVDS 24 Bit Color Flat Panel Display National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Asia Pacific Customer Japan Ltd Americas Fax 49 0 180 530 85 86 Response Group Tel 81 3 5639 7560 Tel 1 800 272 9959 Email europe support nsc com Tel 65 2544466 Fax 81 3 5639 7507 Fax 1 800 737 7018 Deutsch Tel 49 0 69 9508 6208 Fax 65 2504466 Email support nsc com English Tel 44 0 870 24 0 2171 Email
21. ts Power supply pin for PLL Ground pins for PLL Power supply pin for LVDS outputs Ground pins for LVDS outputs TTL level input Description Positive LVDS differential data output Negative LVDS differential data output TTL level clock input The rising edge acts as data strobe Pin name TxCLK IN Positive LVDS differential clock output Negative LVDS differential clock output TTL level input Assertion low input TRI STATES the outputs ensuring low current at power down Programmable strobe select HIGH rising edge LOW falling edge Power supply pins for TTL inputs Ground pins for TTL inputs Power supply pin for PLL Ground pins for PLL Power supply pin for LVDS outputs Ground pins for LVDS outputs Pins not connected DS90C383SLC SLC64A FBGA Package Pin Description Link Transmitter Pin 1 2 4 5 6 PmName mw o 0 P P 9o By Pin Type www national com 86420650 6862065 0 DS90C383 DS90CF384 DS90C383SLC SLC64A FBGA Package Pin Description FPD Link Transmitter continued A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 C1 C2 C3 C4 C5 C6 C7 C8 D1 D2 03 04 05 06 07 D8 E1 E2 E3 E4 EG 7 8 F1 F2 F3 F4 F5 F6 F7 F8 G1 G2 G3 G4 G5 G6 www national com By Pin wow
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National Semiconductor DS90C383/DS90CF384 3.3V Programmable LVDS Transmitter 24 Bit Flat Panel Disp