National DS90C2501 handbook
Contents
1. Symbol Parameter Conditions Units Vin 1 Logical 1 input voltage V Vin 0 Logical O input voltage V VoL Serial Bus Low level output V voltage V Recommended DVO Port Input Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Min Typ Max Units TCIT TxCLK IN Transition Time Figure 4 DUAL Gnd 0 8 1 2 2 4 ns TCIP TxCLK IN Period Figure 5 DUAL Gnd 5 9 T 40 ns TCIH TxCLK in High Time Figure 5 0 35T 0 5T 0 65T ns TCIL TxCLK in Low Time Figure 5 0 35T 0 5T 0 65T ns TXIT DO to D23 Transition Time 1 ns VDDQ Low Swing Voltage Amplitude from GMCH V www national com L0Sz906SC DS90C2501 AC Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Min Typ Max Units LLHT LVDS Low to High Transition Time Figure 3 Note 7 0 14 0 8 ns LHLT LVDS High to Low Transition Time Figure 3 Note 7 0 11 0 8 ns TBIT Transmitter Output Bit Width DUAL pin Voc or 1 7 TCIP ns Gnd DUAL pin 42Vcc 2 7 TCIP ns TCCS TXOUT Channel to Channel Skew 100 ps TPPOSO Transmitter Output Pulse Position for BitO f 65 MHz DUAL pin 0 49 0 0 49 ns previous cycle from CLK1P rising edge Vec Note 7 TPPOS1 Transmitter Output Pulse Position for Biti f 65 MHz DUAL pin 1 7 TCIP 1 7 TCIP 1 7 TCIP ns previous cycle f2. DS90C2501 Pin Description continued Pin Name Pin No VO Type Description OPTION SELECTION VREF 83 I ANALOG This pin is never to be left floating and never tie to GND For LVTTL level data input tie Vgep to Vec3V When Vper gt 1 8V input data is set to LVTTL level For low voltage swing level data input tie Vper to VeVppa Vppa provided by host interface Vbpa is from the host When Vrer lt 1 0V indicates input data is in low voltage swing mode Input data logic High Vger 100 mV in low voltage swing level Input data logic Low Vper 100 mV in low voltage swing level TST1 TST2 19 20 85 I LVTTL 2 5 These pins are used in production testing and should be tied to GND in TST3 normal operation POWER See Application Information for power supply decoupling requirements VeciDVec 81 82 PVVR Power supply pins pin 75 77 81 82 96 119 123 and 125 for 2 5V LVTTL 15 TI inputs and digital circuitry 96 119 123 125 GND DGND 33 73 PWR GND or DGND reference for 2 5V TTL inputs and digital circuitry 74 76 78 79 80 84 118 122 124 Voc3V 121 127 PWR The V c3V is required for internal logic and certain 3V I O During power up stage voltage readings on these pins must be higher than 2 5V pins GND3V 120 126 PWR Ground return pins for Vcc3V powered logic 128 SPLLVce 87 89 PWR 2 5V power supply pins for scaler PLL circuitry It is not recommended to share this powe
3. Transmitter output pulse position min and max RSKM Cable Skew type length Source Clock Jitter cycle to cycle ISI Inter symbol interference Note 10 Cable Skew typically 10 ps 40 ps per foot media dependent Note 10 ISI is dependent on interconnect length may be zero FIGURE 10 Receiver Skew Margin Voc R1 Input R2 20004508 FIGURE 11 Resistor Network for DUAL pin input recommend using R1 R2 10kQ 1 for single to dual mode www national com L0Sz906SC DS90C2501 DS90C2501 Pin Description Pin Name DVO INTERFACE Pin No VO Type Description DO D23 17 16 I LVTTL Low DVO Port RGB input data 15 14 Swing See When DUAL pin GND inputs DO D11 correspond to LVDS ports AO AS 13 12 9 Vrer Signal When DUAL pin 4Vcc 1st pixel from DO D11 corresponds to LVDS ports 8 7 6 5 description A0 A3 2nd pixel from DO D11 corresponds to LVDS ports A4 A7 4 32 31 for more When DUAL pin Vec 1st pixel from DO D11 corresponds to LVDS ports 30 29 information AO A3 2nd pixel from D12 D23 corresponds to LVDS ports A4 A7 28 27 on Low Note Ports refer to the corresponding differential LVDS pin pairs The port A nomenclature should not 26 25 Swing be confused with the serial interface slave address pins AO A2 24 23 22 21 DE I LVTTL Low Display Data Enable When High input pixel data is valid to DS90C2501 Swing when R_FDE bit High def
4. G21 GE1 GE3 G22 GE2 GE4 G23 GE3 GE5 G24 GE4 GE6 G25 GE5 GE7 B26 BEO B27 BE1 B20 BEO BE2 www national com L0Sz906SC DS90C2501 LVDS Interface Continued TABLE 4 Conventional Data mapping for one 12 bit two data per clock single pixel in to dual pixel out application DUAL 1 2Vcc Porti A0 A3 and Port2 A4 A7 are active BAL Gnd Continued VGA TFT Data Transmitter input pin names Receiver output pin names TFT Panel Data Signals Color Bits Signals B3 E3 D3 B21 BE1 BE3 B4 E3 D4 B22 BE2 BE4 B5 E3 D5 B23 BE3 BE5 B6 E3 D6 B24 BE4 BE6 MSB B7 E3 D7 B25 BE5 BE7 www national com 24 LVDS Interface Continued TABLE 5 Conventional Data Mapping for two 12 bit two data per clock dual pixel in to dual pixel out application DUAL Vec Porti AO A3 and Port2 A4 A7 are active BAL Gnd VGA TFT Data Transmitter input pin names Receiver output pin names TFT Panel Data DS900F388 18bit 24bi Port 1 Primary the first active RGB pixel RE RO RI R17 RI R2 R10 RO R2 R3 R11 R1 R3 R4 R12 R2 R4 R5 R13 R3 R5 R6_ RTA ma re G16 Go G1 G17 G1 G2 G10 GO G2 G3 G11 G1 G3 G4 G12 G2 G4 G5 G13 G3 G5 Gra Ga c G15 as 07 se e eo O B16 Bo BI B17 BI B2 B10 BO B2 B3 B11 B1 B3 B4 B12 B2 B4 B5 B13 B3 B5 Do e o 0 B14 B4 Be MSB
5. AVos Change in Vos between 35 mV Complimentary Output States los Output Short Circuit Current Vour OV 0 15 mA loz Output TRI STATE Current PD OV Vgyr OV or Voc 0 1 10 HA SUPPLY CURRENT loot Transmitter Supply Current R 1009 C f 65MHz 70 120 mA when data input and clock 5 pF DUAL pin scaler off 2 75V input are at Low Swing level GND BAL supply GND one 12bit f 65 MHz 90 mA input Pattern scaler off 3 6V Figure 1 supply loc2 Transmitter Supply Current R 1000 C f 108MHz 130 mA when data input and clock 5 pF DUAL pin scaler off 2 75V input are at Low Swing level Ve VCC BAL supply GND one 12bit f 108 MHz 130 mA input Pattern scaler off 3 6V Figure 1 supply lcc3 Transmitter Supply Current RL 1000 C f 65 MHz 415 mA when data input and clock 5 pF DUAL pin scaler on 2 75V input are at Low Swing level GND BAL supply GND one 12bit input loc4 Transmitter Supply Current R 1009 C f 108 MHz 610 mA when data input and clock 5 pF DUAL pin scaler on 2 75V input are at Low Swing level Vce BAL supply GND one 12bit input ICCTZ Transmitter Supply Current PD GND TST1 TST2 TST3 IDO 75 LA Power Down ID1 ID2 ID3 AO A1 A2 RES1 RES2 RES3 RES4 GND BAL GND www national com Two Wire Serial Communication Interface Unless otherwise noted below specifications apply for Vcc3V pin 3 0V to 3 6V
6. 24bit 48bit Conventional Data Inputs Mapped to LVDS Outputs BAL Gnd DUAL 1 2Vcc for AO to A7 first pixel and second pixel 20004538 www national com 34 LVDS Interface Continued CLK1 2 Differential AO Al A2 AS A4 AS A6 A7 Current Cycle FIGURE 17 24bit 48bit Non Conventional Data Inputs Mapped to LVDS Outputs 20004558 BAL Gnd DUAL Gnd for AO to A3 first pixel DUAL Vec for AO to A7 first pixel and second pixel 35 www national com L0Sz906SC DS90C2501 LVDS Interface Continued CLK1 2 Differential AO Al A2 A3 A4 AS A6 A7 Current Cycle cfo RISI RIA R 3 R 2 RIM FIGURE 18 24bit 48bit Non Conventional Data Inputs Mapped to LVDS Outputs BAL Gnd DUAL 1 2Vcc for AO to A7 first pixel and second pixel 20004560 www national com 36 Scaler Information DVO Input and Bypass Mode The input single port DVO data is translated into 18bit 24bit RGB data for scaling Single port data over 108MHz or dual port data will be bypassed and not scaled The LVDS output can be single or dual port Input Timing Control The DS90C2501 input timing control can detect the input timing information such as horizontal and vertical sync width pixel total and line total count and t
7. Information Continued Scan Lines Pixels Vsync Vertical Sync Vertical Back Porch Active Video Horizontal Front Porch Extension Horizontal Sync Horizontal Back Porch Horizontal Front Porch Vertical Front Porch Enable Vsync start 1 2 Vsync end 3 Vertical action region start 4 Vertical action region end 5 Total vertical scan lines in a frame 6 7 8 9 1 Hsync start Hsync end Horizontal active region start Horizontal active region end 0 Total horizontal pixels in a scan line FIGURE 21 Display Signal Timing of DS90C2501 scaler 1of 2 Data Enable 20004568 39 www national com L0Sz906SC DS90C2501 Scaler Information continued Vertical back porch Display background window Display active window Vertical front porch FIGURE 22 Display Signal Timing of DS90C2501 scaler 2 of 2 I D TI lt q pl 4 lt lt O L 1 LVDS Valid Data Interface ENABKL 20004562 FIGURE 23 Sample LCD Power Up Sequence DVS 20004557 www national com 40 Applications Information How to configure the DS90C2501 with DS90C364 or DS90CF364A or DS90CF366 for most common applica tion 1 To configure for single pixel in to single pixel out applica tion using the DS90C2501 with DS90CF364 or DS90CF364A or DS90CF 366 the DUAL pin must be set to Gnd single In thi
8. for PD Vocav 2 0 Voc V dual pixel in to dual pixel out Vim DUAL High Level Input Voltage for PD Vecay VeVcc O 1 VeNcc20 1 V single pixel in to dual pixel out Vi DUAL High Level Input Voltage for PD Vocav 0 4 V single pixel in to single pixel out Ver Input Clamp Voltage lop 18 mA 0 9 1 5 V CP af ua LVCMOS LVTTL DC SPECIFICATIONS for MSEN pin 98 VoL Low level Open Drain Output lo 2 mA 0 1 0 3 V Voltage LVCMOS LVTTL DC SPECIFICATIONS Pin 62 to pin 69 when operate in 3 3V LVTTL level Vou High Level Input Voltage lop 2 MA 2 2 2 95 V VoL Low Level Input Voltage 0 055 0 4 V los Output Short Circuit Current Vour OV 50 120 mA 3 www national com DS90C2501 DC Characteristics continued Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Conditions Min Typ Max Units Low Voltage Level DC SPECIFICATIONS pins DO to D23 CLKINP CLKINM DE HSYNC VSYNC Vppe Low Swing Voltage from GMCH 1 1 8 V VitsH Low Swing High Level Input Verert Vppe V Voltage 100mV VisL Low Swing Low Level Input 0 VREF V Voltage VREF Differential Input Reference 0 475 V Voltage LVDS DRIVER DC SPECIFICATIONS Output pins AnP AnM CLKnP and CLKnM Von Differential Output Voltage RL 1000 250 345 450 mV AVop Change in Vop between 3 35 mV Complimentary Output States Vos Offset Voltage 1 125 1 32 1 475 V
9. in to dual pixel out application DUAL 1 2Vcc Porti AO A3 and Port2 A4 A7 are active BAL Gnd Continued VGA TFT Data Transmitter input pin names Receiver output pin names TFT Panel Data Signals Color Bits Signals B21 BE1 BE3 B4 E3 D4 B22 BE2 BE4 B5 E3 D5 B23 BE3 BE5 B6 E3 D6 B24 BE4 BE6 MSB B7 E3 D7 B25 BE5 BE7 29 www national com L0ST906SC DS90C2501 LVDS Interface TABLE 8 Non Conventional Data Mapping for two 12 bit two data per clock dual pixel in to dual pixel out application Continued DUAL Vec Porti A0 A3 and Port2 A4 A7 are active BAL Gnd VGA TFT Data Transmitter input pin names Receiver output pin names TFT Panel Data Signals Color Bits Signals 24 bit DS90C2501 DS90CF388 18 bit 24 bit Port 1 Primary the first active RGB pixel LSB RO E2 D4 R16 RO RI E2 D5 R17 R1 R2 E2 D6 R10 RO R2 R3 E2 D7 R11 R1 R3 R4 E2 D8 R12 R2 R4 R5 E2 D9 R13 R3 R5 R6 E2 D10 R14 R4 R6 MSB R7 E2 D11 R15 R5 R7 LSB GO E1 D8 G16 GO GI E1 D9 G17 G1 G2 E1 D10 G10 GO G2 G3 E1 D11 G11 G1 G3 G4 E2 DO G12 G2 G4 G5 E2 D1 G13 G3 G5 G6 E2 D2 G14 G4 G6 MSB G7 E2 D3 G15 G5 G7 LSB BO E1 DO B16 BO B1 E1 D1 B17 B1 B2 E1 D2 B10 BO B2 B3 E1 D3 B11 B1 B3 B4 E1 D4 B12 B2 B4 B5 E1 D5 B13 B3 B5 B6 E1 D6 B14 B4 B6 MSB B7 E1 D7 B15 B5 B7 Port 2 Secondary the second active RGB pixel LSB RO E2 D16 R26 RO R
10. 1 www national com L0Sz906SC DS90C2501 Applications Information continued TABLE 10 Connection for SISO Operation Continued PD DVCC or equivalent RSETN DVCC or equivalent VREF VV ppa of GMCH www national com 42 Applications Information Continued see Table 10 The DUAL pin must be set to Gnd In this mode outputs A0 to A7 and CLK1 CLK2 are enabled 3 To configure for single pixel in to dual pixel out application using the DS90C2501 for Single In Single Out operation TABLE 11 Connection for SIDO Operation From DS90C2501 To GMCH RGB data signal connection DO DVOxDATAO D1 DVOxDATA1 D2 DVOxDATA2 D3 DVOxDATA3 D D5 06 D7 DVOxDATA7 D8 DVOxDATA8 D9 DVOXDATA9 D10 DVOxDATA10 D11 DVOXxDATA11 OLKINP CLKINM DE HSYNC DVOXHSYNC VSYNC DVOXVYSNC connection for other pins DUAL YNCC EDGE GND AO A A2 Pull Up Pull Down Based on Device Address IDO Pull Up Pull Down Based on Panel ID ID1 Pull Up Pull Down Based on Panel ID ID2 Pull Up Pull Down Based on Panel ID ID3 Pull Up Pull Down Based on Panel ID RES1 RES2 RES3 RES4 TST1 TST2 TST3 S2Cclk I2CCLK S2Cdat REFOLKI COLOR PD DVCC or equivalent RSETN DVCC or equivalent VREF VaNbpa of GMCH www national com L0ST906SCA DS90C2501 Applications Information continued 4 To configure for dual pixel in to dual pix
11. 1 2Vcc Porti A0 A3 and Port2 A4 A7 are active BAL Gnd VGA TFT Data Transmitter input pin names Receiver output pin names TFT Panel Data Signals Color Bits Signals 24 bit DS90C2501 DS90CF388 18 bit 24 bit Port 1 Primary the first active RGB pixel LSB RO E2 D4 R16 ROO RI E2 D5 R17 RO1 R2 E2 D6 R10 ROO RO2 R3 E2 D7 R11 RO1 RO3 R4 E2 D8 R12 RO2 RO4 R5 E2 D9 R13 RO3 RO5 R6 E2 D10 R14 RO4 RO6 MSB R7 E2 D11 R15 RO5 RO7 LSB Go E1 D8 G16 GOO GI E1 D9 G17 GO1 G2 E1 D10 G10 GOO GO2 G3 E1 D11 G11 GO1 GO3 G4 E2 DO G12 GO2 GO4 G5 E2 D1 G13 GO3 GO5 G6 E2 D2 G14 GO4 GO6 MSB G7 E2 D3 G15 GO5 GO7 LSB BO E1 DO B16 BOO B1 E1 D1 B17 BO1 B2 E1 D2 B10 BOO BO2 B3 E1 D3 B11 BO1 BO3 B4 E1 D4 B12 BO2 BO4 B5 E1 D5 B13 BO3 BO5 B6 E1 D6 B14 BO4 BO6 MSB B7 E1 D7 B15 BO5 BO7 Port 2 Secondary the second active RGB pixel LSB RO E4 D4 R26 REO RI E4 D5 R27 REI R2 E4 D6 R20 REO RE2 R3 E4 D7 R21 REI RE3 R4 E4 D8 R22 RE2 RE4 R5 E4 D9 R23 RE3 RES R6 E4 D10 R24 RE4 RE6 MSB R7 E4 D11 R25 RES RE7 LSB GO E3 D8 G26 GEO G1 E3 D9 G27 GE1 G2 E3 D10 G20 GEO GE2 G3 E3 D11 G21 GE1 GE3 G4 E4 DO G22 GE2 GE4 G5 E4 D1 G23 GE3 GE5 G6 E4 D2 G24 GE4 GE6 MSB G7 E4 D3 G25 GE5 GE7 LSB BO E3 DO B26 BEO B1 E3 D1 B27 BE1 B2 E3 D2 B20 BEO BE2 www national com 28 LVDS Interface Continued TABLE 7 Non Conventional Data mapping for one 12 bit two data per clock single pixel
12. 1 E2 D17 R27 R1 R2 E2 D18 R20 RO R2 R3 E2 D19 R21 R1 R3 R4 E2 D20 R22 R2 R4 R5 E2 D21 R23 R3 R5 R6 E2 D22 R24 R4 R6 MSB R7 E2 D23 R25 R5 R7 LSB GO E1 D20 G26 GO GI E1 D21 G27 G1 G2 E1 D22 G20 GO G2 G3 E1 D23 G21 GI G3 G4 E2 D12 G22 G2 G4 G5 E2 D13 G23 G3 G5 G6 E2 D14 G24 G4 G6 MSB G7 E2 D15 G25 G5 G7 LSB BO E1 D12 B26 BO B1 E1 D13 B27 B1 B2 E1 D14 B20 BO B2 www national com 30 LVDS Interface continued TABLE 8 Non Conventional Data Mapping for two 12 bit two data per clock dual pixel in to dual pixel out application DUAL Vec Porti A0 A3 and Port2 A4 A7 are active BAL Gnd Continued VGA TFT Data Transmitter input pin names Receiver output pin names TFT Panel Data Signals Color Bits Signals B21 B1 B3 B4 E1 D16 B22 B2 B4 B5 E1 D17 B23 B3 B5 B6 E1 D18 B24 B4 B6 MSB B7 E1 D19 B25 B5 B7 31 www national com L0Sz906SC DS90C2501 Note 12 Note 13 Note 14 Note 15 Note 16 Note 17 Note 18 LVDS Interface Continued moon FT AA CLK1 CLKINP NSX SN DSEL 1 single ended clock CLK1 CLKINP Ad ey RETA CLKO CLKINM IE Ne dEi CLK1 CLKINP AVAV Viv DSEL 1 single ended clock CLK1 CLKINP ERES VAL ima E ae i DI vv vw Primary Edge E1 E2 E3 E4 DSEL 0 differential clock DSEL 0 differential clock 20004533 FIGURE 14 How Data is Latched in the DS90C2501 The lower half of the pixel is latched by the primary clock edge E1 E3 and
13. B7 E1 D7 B15 B5 B7 Port 2 Secondary the second active RGB pixel R26 RO R27 R1 R20 RO R2 R21 R1 R3 R22 R2 R4 R23 R3 R5 R24 R4 R6 R25 R5 R7 G26 GO G27 GI G20 GO G2 G21 GI G3 G22 G2 G4 G23 G3 G5 G24 G4 G6 G25 G5 G7 B26 BO B27 B1 B20 BO B2 www national com L0ST906SC DS90C2501 LVDS Interface Continued TABLE 5 Conventional Data Mapping for two 12 bit two data per clock dual pixel in to dual pixel out application DUAL Vcc Porti A0 A3 and Port2 A4 A7 are active BAL Gnd Continued VGA TFT Data Transmitter input pin names Receiver output pin names TFT Panel Data Signals Color Bits Signals B3 E1 D15 B21 B1 B3 B4 E1 D16 B22 B2 B4 B5 E1 D17 B23 B3 B5 B6 E1 D18 B24 B4 B6 MSB B7 E1 D19 B25 B5 B7 www national com 26 LVDS Interface continued TABLE 6 Non Conventional Data mapping for one 12 bit two data per clock single pixel in to single pixel out application DUAL Gnd only Porti AO A3 are active BAL Gnd VGA TFT Data Signals Color Transmitter input pin names Receiver output pin names TFT Panel Data Signals 18 bit DS90C2501 DS90CF388 i 24 bit 27 www national com L0Sz906SC DS90C2501 LVDS Interface Continued TABLE 7 Non Conventional Data mapping for one 12 bit two data per clock single pixel in to dual pixel out application DUAL
14. Communication Interface Description There are two register sets on DS90C2501 One set is for controlling the input and output blocks as shown below and one set is for controlling the scaler which is not shown on this datasheet Both register sets are accessible by the host system through the Two Wire Serial Communication Inter face The DS90C2501 operates as a slave on the Serial Bus so the SCL line is an input no clock is generated by the DS90C2501 and the SDA line is bi directional DS90C2501 has a 7 bit slave address The address bits are controlled by the state of the address select pins A2 A1 and AO and are set by connecting these pins to ground for a LOW 0 to Vec8V pin for a HIGH 1 Therefore the complete slave address is AG A5 A4 A3 A2 A1 AO MSB LSB and is selected as follows Address Select Pin State DS90C2501 Serial Bus Slave Address A6 A3 are hardwired to 0111 A6 A0 binary 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 The DS90C2501 latches the state of the address select pins during the first read or write on the Serial Bus Changing the state of the address select pins after the first read or write to any device on the Serial Bus will not change the slave address of the DS90C2501 Communicating with the DS90C2501 Control Registers All registers are predefined as read only or read and write The Serial Interface will a
15. Default Value 13h Access Method Read Only Bit 7 0 Description Vendor ID High Byte Register Name DEV_IDL Address Offset 02h Default Value 26h Access Method Read Only Bit Description 7 0 Device ID Low Byte Register Name DEV_IDH Address Offset O3h Default Value 67h Access Method R W Bit Description Device ID High Byte Register Name DEVICE REVISION Address Offset 04h Default Value Oth Access Method R W Bit Description 7 0 Device Revision Value Register Name RESERVED Address Offset O5h Default Value A5h Access Method Read Only Bit Description 7 0 Reserved Register Name FRQ_LOW Address Offset O6h Default Value 19h Access Method Read Only Bit 7 0 Description Minimum LVDS Output Frequency 25 MHz Register Name FRQ_HIGH Address Offset 07h Default Value See Description Access Method Read Only Description Maximum LVDS Output Frequency If DUAL GND or Vec value is A2h 162 MHz If DUAL Voc value is 55h 85 MHz www national com 18 Host Control Register Descriptions continued Register Name CFG1 Address Offset O8h Default Value 39h Access Method R W Bit 0 1 2 Description Soft Power Down 0 Power Down 1 Normal Operation Reserved BPASS 1 bypass 0 non bypass This field is valid only when DUAL pin is OV or VeV 6 Note When image scaling is no
16. E4 only apply when DUAL pin 1 2 Vcc Above figure only valid when R_FDE bit Vcc DE signal from GUI is set to be active HIGH DO to D11 are clocked at the crossing point of CLKOUT and CLKOUT when differential clock input is applied This applies to D12 to D23 when DUAL pin Vcc Single ended clock is not recommended for operation above 65MHz by GMCH vendor TABLE 9 12 bit two data per clock input application data mapping with GMCH PO P1 P2 en BO 6 RO 2 B1 6 D Bos RO 1 B1 5 E Bora RO 0 B1 4 BO 3 Go 7 B1 3 G1 7 B2 3 G2 7 D2 BO 2 GO 6 B1 2 G1 6 B2 2 G2 6 DI BO 1 Go 5 B1 1 G1 5 B2 1 G2 5 DO BO 0 Gola B1 0 G1 4 B2 0 G2 4 Color notation R RED G GREEN B BLUE Bit significance within a color 7 0 MSB LSB www national com 32 LVDS Interface Continued CLK1 2 Differential AO Al A2 AS A4 AS A6 A7 Current Cycle FIGURE 15 24bit 48bit Conventional Data Inputs Mapped to LVDS Outputs 20004535 BAL Gnd DUAL Gnd for AO to A3 first pixel DUAL Vec for AO to A7 first pixel and second pixel 33 www national com L0Sz906SC DS90C2501 LVDS Interface Continued CLK1 2 Differential AO Al A2 A3 A4 AS A6 A7 Current Cycle FIGURE 16
17. Email ap support nsc com National Semiconductor Japan Customer Support Center Fax 81 3 5639 7507 Email jpn feedback E nsc com Deuisch Tel English Tel 49 0 69 9508 6208 44 0 870 24 0 2171 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications Fran ais Tel 33 0 1 41 91 8790 11 sve jiajuj Aejdsia safi 104 dojess Ul ING YUM 19 WISUEIL LOSZOO6SA DS90C2501 Transmitter with built in scaler for LVDS Display Interface LDI www national com Tel 81 3 5639 7560 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications
18. HLT 20004512 FIGURE 3 DS90C2501 Transmitter LVDS Output Load and Transition Times TxCLK IN TCIT 20004514 FIGURE 4 DS90C2501 Transmitter Input Clock Transition Time TCIP TCIH CLKINP TCIL 20004555 FIGURE 5 DS90C2501 Transmitter Input Clock High Low Times CLKINP ad TSTC e THTC Dj TSTC Dt THTC gt All Data High Low from E1 and E2 E1 E2 20004554 FIGURE 6 Setup Hold Times Vperz 0 900V EDGE Gnd DUAL Vec BAL Gnd 9 www national com L0Sz906SC DS90C2501 AC Timing Diagrams continues POWER DOWN I 2 25V H I V I ce Le TPLLS gt 1 I 3 0V I I TxCLK IN i iau FIGURE 7 DS90C2501 Transmitter Phase Lock Loop Set Time 20004519 POWER DOWN 1 5V N I I I I I I TPDD o ul I TXOUT TRI STATE I 20004521 FIGURE 8 Transmitter Power Down Delay aF CLKINP Lag TPDL gt All Data from E1 and E2 E E2 ckm an a CLKIP AOM A7M All Data from E1 and E2 AOP A7P 20004553 FIGURE 9 Transmitter Input to Output Lantency www national com 10 AC Timing Diagrams continued Ideal Strobe Position RxIN or RxIN 1 4V RxIN or RxIN Tpposn min max Tpposn 1 20004525 C Setup and Hold Time Internal data sampling window defined by Rspos receiver input strobe position min and max Tppos
19. O 0 bs90c25010 0 O National Semiconductor DS90C2501 Transmitter with built in scaler for LVDS Display Interface LDI General Description The DS90C2501 is a highly integrated scaling IC with LVDS transmitter with a scaled resolution up to SXGA for single pixel input The DS90C2501 is a video controller hub de signed to be compatible with Graphic Memory Controller Hub GMCH The input interface can be single or dual DVO port 12 pin per port The high quality cubic zoom engine scales the input graphics into the desired optimal output resolution up to 1400x1050 resolution Advanced video digi tal signal processing provides gamma correction and dith ering for the display output A two wire serial interface is used to communicate with the host system The dual high speed LVDS channels supports single pixel in single pixel out single pixel in dual pixel out and dual pixel in dual pixel out transmission modes The DS90C2501 complies to Open LDI standard and can be paired up with DS90CF388 re ceiver or FPD8531x FPD8731x series integrated timing con troller or FPDLink LVDS receivers such as DS90CF364 DS90CF384A DS90CF384 DS90CF384A The LVDS output is similar to DS90C387 and DS90C387R Thus this trans mitter can be paired up with DS90CF388 receiver of 112MHz LDI chipset or FPD Link Receivers in non DC Bal ance mode operation which provides GUI LCD panel mother board vendors a wide choice of inter operation with LVDS based
20. TFT panels This chip is an ideal solution to solve EMI and cable size problems for high resolution flat panel applications It pro vides a reliable industry standard interface based on LVDS technology that delivers the bandwidth needed for high resolution panels while maximizing bit times and keeping clock rates low to reduce EMI and shielding requirements For more details please refer to the Applications Informa tion section of this datasheet October 2003 Features m Complies with Open LDI and GMCH DVO specification for digital display interfaces m 25 to 65 MHz clock in single pixel in to single pixel out operation m 50 to 130 MHz clock in single pixel in to dual pixel out operation m Support 24bit 48bit color TFT LCD with Conventional and Non Conventional Color Mappings m Support 16bit 32bit color TFT LCD m Single pixel transmitter inputs support single pixel GUI interface m Up scaling panel fitting supports VGA to SXGA output in single pixel input mode at 640x480 60Hz 800x600060Hz 1024x768 60Hz 1280x1024 60Hz 1400x1050 60Hz m Independent horizontal and vertical scaling m Support dithering available for 6 bit color only programmable smoothing and anti aliasing filter m Programmable digital sharpness edge enhancement and contrast control via gamma correction m Allow 2 at 200KHz spread spectrum clocking rejects cycle to cycle jitter 20 of input data bit time m Programmable LCD panel po
21. VDS color mapping Tie to GND for 18 bit 36 bit LCD Tie to GND to select conventional color mapping for 24 bit 48 bit LCD Tie to Logic 1 to select non conventional color mapping for 24 bit 48 bit LCD AO A1 A2 115 116 117 I LVTTL 2 5 These are input pins to select the 2 wire Serial Communication Slave Device Address Lower Bits EDGE 36 PANEL INTERFACE AOP A1P A2P A3P AOM A1M A2M A3M A4P A5P A6P A7P 55 53 51 47 56 54 52 48 45 43 41 39 I LVTTL 2 5 O LVDS O LVDS O LVDS Selects primary clock edge E1 Tie to Logic 1 to select Rising edge for E1 Tie to ground to select Falling edge for E1 Positive LVDS differential data output When DUAL pin GND input to DO D11 will be coming out of AOP to A3P For 6 bit color application no connect for channel ASP When DUAL pin V the first pixel going in DO D11 will be coming out of AOP to ASP and the second pixel going in DO D11 will come out of A4P to A7P For 6 bit color application no connect for channels A3P and A7P When DUAL pin Vec the first pixel going in DO D11 will be coming out of AOP to ASP the second pixel going in D12 D23 will be coming out of A4P to A7P For 6 bit color application no connect for channels A3P and A7P Negative LVDS differential data output When DUAL pin GND input to DO D11 will be coming out of AOM to A3M For 6 bit color application no connect for
22. Voltage CMOS TTL Output Voltage LVDS Driver Output Voltage LVDS Output Short Circuit Duration Junction Temperature Storage Temperature 0 3V to 2 8V 0 3V to 3 6V 0 3V to Vocav 0 3V to Ve 0 3V 0 3V to Voc 0 3V Continuous 150 C 65 C to 150 C Typical Package Power Dissipation Capacity 70 C and Max Voc 128 CSP Package DS90C2501 Maximum Operating Case Temperature 97 C measured at top center of package ESD Rating DS90C2501 HBM 1 5kQ 100pF EIAJ 092 200pF 1 8W gt 2kV gt 250 V Recommended Operating Conditions Min Nom Max Units L0Sz906SCA Lead Temperature All Supply Voltage except 2 250 2 5 2 750 V Soldering 4 sec 260 C Vccav Vecav Supply Voltage 3 0 33 3 6 V Operating Free Air Temperature TA O 25 70 C Supply Noise Voltage Vec 100 MVpp up to 33Mhz DC Characteristics Over recommended operating supply and temperature ranges unless othervvise specified Symbol Parameter Conditions Min Typ Max Units LVCMOS LVTTL DC SPECIFICATIONS All input pins when operate in LVTTL level except DUAL pin Note On IDO ID1 pins have typical 30K ohm internal pull down and ID2 and ID3 pins have typical 3K ohm internal pull down Ver Input Clamp Voltage lop 18 mA 0 9 1 5 V lin Input Current Vin 0 4V or Voc 1 8 15 LA Vin GND 15 0 pA LVCMOS LVTTL DC SPECIFICATIONS for DUAL pin pin35 Vim DUAL High Level Input Voltage
23. ault See RFDE register field for more information HSYNC I LVTTL Low Display Horizontal Sync input control signal Swing VSYNC I LVTTL Low Display Vertical Sync input control signal Swing CLKINP I LVTTL Low Positive differential pixel clock input A differential clock is recommended for Swing applications 65 MHz or higher Differential CLKINM 11 I LVTTL Low Minus differential pixel clock input A differential clock is recommended for Swing applications 65 MHz or higher Differential HOST INTERFACE RESETN 61 I LVTTL 2 5 Active low RESET signal Asserting RESETN will reset all internal logic and clear the Host Interface registers S2CCLK I LVTTL3V This is the clock line for the two wire serial communication interface Normally a pull up resistor is required in the system S2CDAT VO LVTTL3V This is the data line for two wire serial communication interface A Pull up resistor is normally required in the system MSEN O LVTTL 2 5 Interrupt signal This is an open drain output a pull up resistor is required Please refer to MDI RSEN TSEL and MSEL register fields in Register Field Definitions for more information This signal requires support from host software PD 99 I LVTTL 2 5 Power Down Signal A logic 0 will place the device in power down mode per Table 1 below When maximum power savings is desired the PD pin or soft power down bit Reg 08h bit 0 should be used to power down the DS90C2501 LVDS outputs of the device wi
24. channel A3M When DUAL pin V the first pixel going in DO D11 will be coming out of AOM to ASM and the second pixel going in DO D11 will come out of A4M to A7M For 6 bit color application no connect for channels A3M and A7M When DUAL pin Vcc the first pixel going in DO D11 will be coming out of AOM to A3M the second pixel going in D12 D23 will be coming out of A4M to A7M For 6 bit color application no connect for channels A3M and A7M Positive LVDS differential data output for second pixel When DUAL pin GND input to DO D11 will be coming out of AOP to A3P For 6 bit color application no connect for channel ASP When DUAL pin 2V the first pixel going in DO D11 will be coming out of AOP to ASP and the second pixel going in DO D11 will come out of A4P to A7P For 6 bit color application no connect for channels A3P and A7P When DUAL pin Vec the first pixel going in DO D11 will be coming out of AOP to ASP the second pixel going in D12 D23 will be coming out of A4P to A7P For 6 bit color application no connect for channels A3P and A7P 13 www national com L0GC0 06SA DS90C2501 DS90C2501 Pin Description Continued Pin Name Pin No VO Type Description OPTION SELECTION A4M A5M 46 44 O LVDS Negative LVDS differential data output for second pixel A6M A7M 42 40 When DUAL pin GND input to DO D11 will be coming out of AOM to A3M For 6 bit color application no connect f
25. d The master must generate a Start and send the 7 bit slave address plus a O first and wait for acknowledge from DS90C2501 When DS90C2501 acknowledges the 1st ACK that the master is calling the master then sends the data register address byte and waits for acknowledge from the slave When the slave acknowledges the 2nd ACk the master repeats the Start by sending the 7 bit slave address plus a 1 indicating that READ operation is in progress and waits for acknowledge from DS90C2501 After the slave responds the 3rd ACK the slave sends the Start Bus Activity Slave Master SDA Line S A A A 0 Bus Activity A DS90C2501 E Register mg Address dq Address gt TT Datta __ gt data to the bus and waits for acknowledge from the master When the master acknowledges the 4th ACK and gener ates a Stop this completes the READ If the 4th ACK is received from the master and no Stop follows it the slave will keep sending the data of next register until Stop is received from the master If the 4th ACK is not received from the master the slave will terminate the Serial Bus communication and giving the bus control back to the master Stop RO DP RO DP 20004531 FIGURE 13 Byte Write The master must generate a Start and send the 7 bit slave address plus a O and wait for acknowledge from DS90C2501 When DS90C2501 acknowledges the 1st ACK that t
26. ed below specifications apply for Vcc3V pin 3 3V load capacitance on output lines 80 pF Load ca pacitance on output lines can be up to 400pF provided that external pull up is on board The following parameters are the tim ing relationship between SCL and SDA signals related to the DS90C2501 Symbol Parameter Max Units ty SCL Clock Period nm us t Data in Set Up Time to SCL High ns ta Data Out Stable after SCL Low ns ty SDA Low Set Up Time to SCL Low Start Condition 100 ns ts SDA High Hold Time after SCL High Stop Condition 100 ns Note 1 Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed They are not meant to imply that the device should be operated at these limits The tables of Electrical Characteristics specify conditions for device operation Note 2 Typical values are given for Vec 2 5V and Vccay 3 3V at Ta 25 C Note 3 Current into device pins is defined as positive Current out of device pins is defined as negative Voltages are referenced to ground unless otherwise specified except Vop and AVop Note 4 The limits are based on bench characterization of the device s jitter response over the power supply voltage range Output clock jitter is measured with a cycle to cycle jitter of 20 data input bit time applied to the input clock signal while data inputs are switching see figures 11 and 12 This parameter is used when calculatin
27. el out application using the DS90C2501 with DS90CF364 or DS90CF364A or DS90CF366 the DUAL pin must be set to Voc In this mode outputs AO to A7 and CLK1 CLK2 are enabled Do note that scaler will be shut down in this configuration Board Layout and Thermal Considerations for the DS90C2501 Note The thermal information listed in this document is based on preliminary simulation results and subject to change The thermal enhancement features of the CSP chip scale package require special considerations and guidelines to be observed to insure optimal thermal performance in applica tions were the cooling method is free air convection The CSP128 package has a 5X5 matrix of thermal pads designed to efficiently conduct heat from the device to the plane of the printed circuit board The package requires this thermal connection to increase the effective surface area of the package to maintain safe operating die temperatures The vias of the thermal pads should be connected to the board s ground plane having a minimum effective area of 2000 mm For more complex system thermal design situations it is recommended that system level thermal analysis tools be utilized to insure the maximum junction temperature is not exceeded The graph in Figure 24 shows the expected junction tem perature for a given plane area under varying ambient tem perature conditions Figure 25 shows the recommended PCB footprint for the DS90C2501 The foll
28. g system margin as described in AN 1059 Note 5 Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs This margin takes into account transmitter output pulse positions min and max and the receiver input setup and hold time internal data sampling window RSPOS This margin allows for LVDS interconnect skew inter symbol interference both dependent on type length of cable and clock jitter RSKM 2 cable skew type length source clock jitter cycle to cycle Note 6 From V 1 25V of CLKINP to Vpiffr OV of CLK1P when EDGE pin Gnd DUAL pin Gnd or Vcc or Vcc BAL pin Gnd Note 7 Guaranteed by Design AC Timing Diagrams FIGURE 1 Alternate High Low Test Pattern in 12 bit Input Mode Note 8 20004532 www national com L0Sz906SC DS90C2501 AC Timing Diagrams continues Signal Pattern Device Pin Name EDGE 0 20004551 FIGURE 2 16 Grayscale Test Pattern in 12 bit Input Mode Note 9 Note 8 The Alternate High Low test pattern produces a maximum toggling of digital circuits LVDS I O and CMOS TTL I O Note 9 The 16 grayscale test pattern tests device power consumption for a typical LCD display pattern The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display www national com 8 AC Timing Diagrams continued TXOUT U TXOUT 80 Differential 20 L
29. he active video starting and ending positions Such information can be provided to the host through two wire serial communication Interface to help determine the input mode Display Synchronization The DS90C2501 synchronizes the display timing with input graphics timing so that no external frame buffer is needed There are three operation modes Free run mode No synchronization Output timing is gener ated from external 14 318MHz reference clock Line lock mode the display Hsync is synchronized with the input line rate Frame lock mode the display Vsync is synchronized with the input frame rate In free run mode the display timing is decided by the values programmed into the various timing registers In line lock mode the display line rate is a function of the selected input clock forcing the output frame rate to be locked to input frame rate Timing management is more complicated The frame lock mode is used more often The output pixel clock and Hsync are generated from the external 14 318MHz ref erence clock and the embedded PLL but the Vsync is refreshed at the input frame rate Gamma Look up Table LUT The DS90C2501 provides an 8 bit look up table LUT for each input color channel in case gamma correction is needed The LUT is user programmable to provide an arbi trary transfer function The transmitter is offered with programmable edge data strobes for convenient interface with a variety of graphics controller
30. he master is calling the master then sends the data register address byte and waits for acknowledge from the slave When the slave acknowledges the 2nd ACK the master sends the data byte and wait for acknowledge from the slave When the slave acknowledges the 3rd ACK the master generates a Stop This completes the WRITE If the master doesn t generate the Stop the master can keep sending data to location of the next register address Register Address 1 and waits for acknowledge from the Host Control Register Descriptions VND_IDL 00h 05h Read Only Register Name Address Offset Default Value Access Method slave If the slave acknowledges the master can send data to the next register address Register Address 2 If the slave doesn t acknowledges the master will have the control of the bus and can generate a Stop to end the WRIT E operation During the process if the master attempts to send data to Read Only registers the slave will not acknowledge and return the bus control back to the master A complete programming guide is available for the DS90C2501 to OEM customers This can be obtained by contacting your local National Semiconductor sales representative 17 www national com L0ST906SC DS90C2501 Host Control Register Descriptions continued Bit Description 7 0 Vendor ID Low Byte Register Name VND_IDH Address Offset 01h
31. input pin names Receiver output pin names TFT Panel Data 24 bit DS90CF388 18 bit 24 bit se o ew omw o R2 RO RO R2 R3 R1 R1 R3 R4 R2 R2 R4 R5 R3 R3 R5 R6 R4 4 R6 mse P7 sse a ew oe 60 G_ Emo G17 Gi G2 GO GO G2 G3 G1 G1 G3 G4 G2 G2 G4 G5 G3 G3 G5 G6 G4 4 G6 vse 67 iss 60 ewo 86 80 B2 BO BO B2 B3 B1 B1 B3 B4 B2 B2 B4 B5 B3 B3 B5 B6 B4 B4 B6 www national com 22 LVDS Interface Continued TABLE 4 Conventional Data mapping for one 12 bit two data per clock single pixel in to dual pixel out application DUAL 1 2Vcc Porti A0 A3 and Port2 A4 A7 are active BAL Gnd VGA TFT Data Transmitter input pin names Receiver output pin names TFT Panel Data DS90CF388 e 24b Port 1 Primary the first active RGB pixel RE ROO RI R17 RO1 R2 R10 ROO RO2 R3 R11 RO1 RO3 R4 R12 RO2 RO4 R5 R13 RO3 RO5 Fe R14 RO4 RO6 R15 ROS RO7 G16 600 G1 G17 GO1 G2 G10 GOO GO2 G3 G11 GO1 GO3 G4 G12 GO2 GO4 G5 G13 GO3 GO5 Gra coa 606 Gis cos Go7 iss Bo bo B16 B00 BI B17 BO1 B2 B10 BOO BO2 B3 B11 BO1 BO3 B4 B12 BO2 BO4 B5 B13 BO3 BO5 CO f e B14 BO4 806 MSB B7 E1 D7 B15 BO5 BO7 Port 2 Secondary the second active RGB pixel R26 REO R27 RE1 R20 REO RE2 R21 RE1 RE3 R22 RE2 RE4 R23 RE3 RE5 R24 RE4 RE6 R25 RE5 RE7 G26 GEO G27 GE1 G20 GEO GE2
32. ll be in TRI STATE Scaling engine will be powered down and retain all register values PLL will be powered down All data input pads will be powered down Vp_r circuit is powered down The two wire serial communication interface remains active and all register contents will be retained All GPIO pins will be disabled tri state if programmed as an output ENAVDD ENABKL PWM VSTALL and HIRQ pins remain active and can be accessed through the two wire serial communication interface CLOCK REFCLK1 18 I LVTTL3V Reference clock A 3V 14 318 MHz clock is required for internal control and timing This clock must be stable when the DS90C2501 is powered up www national com DS90C2501 Pin Description continued Pin Name Pin No VO Type Description OPTION SELECTION BAL DUAL COLOR 97 35 34 I LVTTL 2 5 I LVTTL 2 5 I LVTTL 2 5 Tie this pin to GND LVTTL level input Input GND for single pixel in to single pixel out mode LVDS output channels AO to A3 are enabled A4 to A7 are CLK2 are disable Input Voc for dual pixel in to dual pixel out mode LVDS output channel AO to A7 CLK1 and CLK2 are enable Use a 10K typ pull up resistor Input VeV c for single pixel in to dual pixel out mode LVDS output channel AO to A7 CLK1 and CLK2 are enabled See register CFG1 08h BPASS field for more information See Figure 11 for example interface circuit LVTTL level input to select RGB to L
33. lways attempt to detect if a LCD panel monitor is connected A Write to the DS90C2501 will always include the slave address byte data register address byte a data byte A Read from the DS90C2501 can take place either of two ways 1 If the location latched in the data register addresses is correct then the read can simply consist of a slave address byte followed by retrieving the data byte 2 Ifthe data register address needs to be set then a slave address byte data register address will be sent first then the master will repeat start send the slave address byte and receive data byte to accomplish a read The data byte has the most significant bit first At the end of a read the DS90C2501 can accept either Acknowledge or No Acknowledge from the Master No Acknowledge is typi cally used as a signal for the slave that the Master has read its last byte Serial Bus Protocol The DS90C2501 slave state machine does not require an internal clock and supports only byte read and write Page mode is not supported The 7 bit binary address is 0111A A Ao where AsA Ao are pin programmable and A6 A3 are hardwired internally to 0111 www national com Serial Bus Protocol continued Bus Activity Master 3 Slave Register 4 Address P 4 Address Ab SDA Line Bus Activity A DS90C2501 E A c K Slave amp Address gt ROD Stop Start 20004530 FIGURE 12 Byte Rea
34. nformation LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification CSP 9 111C2 and the Banned Substances and Materials of Interest Specification CSP 9 111S2 and contain no Banned Substances as defined in CSP 9 111S2 National Semiconductor Americas Customer Support Center Email new feedback E nsc com Tel 1 800 272 9959 National Semiconductor Europe Customer Support Center Fax 49 0 180 530 85 86 Email europe supportQ nsc com National Semiconductor Asia Pacific Customer Support Center
35. nly Bit Description o 3 Contains state of input data bits 23 16 Register Name PANEL Address Offset OCh Default Value See Description Access Method R W Bit Description 0 3 System defined Panel ID values set on IDO 3 pins Read Only 4 7 System defined Panel ID field which can be written read from host www national com 20 Host Control Register Descriptions continued Register Name DEBUG_A Address Offset ODh Default Value Access Method Mixed See Description Depends on pin state Bit Description 1 0 DUAL 1 0 State of DUAL pin Read Only 00 SISO 01 SIDO 11 DIDO 2 PLLOCK Read Only 3 Reserved Read Only 7 4 Reserved R W Register Name RESERVED Address Offset OEh OFh Default Value 00h Access Method R W Bit Description 7 0 Reserved LVDS Interface TABLE 2 LVDS data bit naming convention Description Red Green X B Blue Odd First Pixel Even Second Pixel LVDS bit number not VGA controller LSB to MSB 21 www national com L0Sz906SC DS90C2501 LVDS Interface Continued TABLE 3 Conventional Data mapping for one 12 bit two data per clock single pixel in to single pixel out application DUAL Gnd only Porti AO A3 are active BAL Gnd VGA TFT Data Signals Color Transmitter
36. or channel A3M When DUAL pin VeV c the first pixel going in DO D11 will be coming out of AOM to A3M and the second pixel going in DO D11 will come out of A4M to A7M For 6 bit color application no connect for channels A3M and A7M When DUAL pin Vec the first pixel going in DO D11 will be coming out of AOM to A3M the second pixel going in D12 D23 will be coming out of A4M to A7M For 6 bit color application no connect for channels A3M and A7M CLK1P 49 O LVDS Positive LVDS differential clock output CLK1M 50 O LVDS Negative LVDS differential clock output CLK2P 37 O LVDS Additional positive LVDS differential clock output pin Identical to CLK1P No connect if not used CLK2M O LVDS Additional negative LVDS differential clock output pin Identical to CLK1M No connect if not used IDO ID1 1D2 I LVTTL 2 5 These four pins are used to select one out of 16 pre determined LCD display ID3 timing information The values are from 0 to 15 This function requires support from VBIOS or display driver Tie these pins to GND when not in use Tie these four pins ID3 ID2 ID1 IDO to High or Low for selecting LCD panel IDO is the LSB and ID3 is the MSB For example 1000 will select the 9th LCD panel A 4 bit register field 3 0 will be used to store the selected value for the host to read See PANEL field for more information ENAVDD O LVTTL 2 5 Output to control LCD panel power under software control Typically this output is used with a p
37. ower switch such as a FET circuit to control LCD panel Vec Note 11 ENABKL O LVTTL 2 5 Output to control LCD panel back light power under software control MISCELLANEOUS TEST Typically this output is used to control the enable on a backlight inverter Note 11 GPIO1 64 63 62 I O LVTTL 3V General purpose inputs or outputs referenced to GND GPIO2 When the device is powered up this pin defaults to an input GPIO3 When the scaler is in the power down state these signals are tri state if programmed as outputs Note 11 CLK_INV I LVTTL 2 5 This pin is used to invert the polarity of the incoming pixel CLK CLKINP CLKINM A logic 0 Normal Logic 1 Invert RES2 I LVTTL 2 5 This pin is used in production testing and should be tied to GND in normal operation RES3 113 I LVTTL 2 5 This pin is used in production testing and should be tied to GND in normal operation RES4 I LVTTL 2 5 This pin is used in production testing and should be tied to GND in normal operation PWM O LVTTL 3V This signal was provided for legacy support and is no longer required This pin should be left open in normal operation VSTALL O LVTTL 3V This signal was provided for legacy support and is no longer required This pin should be left open in normal operation HIRQ 65 O LVTTL 3V This signal was provided for legacy support and is no longer required This pin should be left open in normal operation www national com
38. owing assump tions were used e Board Thickness 1 6mm e Board Area 7742 sq mm e Copper Plane 1 oz e Number of layers 4 e Signal Trace Length 25 4mm e Maximum Junction Temperature 150 C e Package 6ja 31 7 C W Natural Convection e The example does not take heating effects from adjacent system components into consideration e Pd max 1 8W scaler on SXGA to SXGA scaling single in dual output port mode Vpp2 5 10 Vpp3 3 10 max process variation As a final design verification the temperature at the top center of the case Tcase should not exceed 97 C Junction Temperature vs Plane Area 180 0 160 0 140 0 120 0 100 0 80 0 60 0 40 0 JUNCTION TEMPERATURE Ty 20 0 0 0 0 2000 4000 6000 8000 GROUND PLANE AREA MM2 20004570 FIGURE 24 Junction Temperature vs Ground Plane Area www national com Applications Information Continued 1 00 mm TYP Pn 1 0 OQ000000O00G000000 QUUUUOOUOO0UUU000U 0 254 mm diameter TYP via plated around wall at 16 location 1 00 mm TYP Pin 20 Wiring Side 20004571 FIGURE 25 Recommended Land Pattern Component Side 1 and Wiring Side 2 of Board with Thermal Pads Connected to Gro
39. r with PLLVcc SPLLGND 86 88 90 PWR Ground returns for scaler PLL circuitry PLLVec 92 94 PVVR 2 5V power supply pins for Tx PLL circuitry It is not recommended to share this power with SPLLVce PLLGND 91 93 95 PWR Ground returns for Tx PLL circuitry LVDSVec 105 109 PWR Power supply pins for LVDS output drivers LVDSGND 104 108 PWR Ground return pins for LVDS output drivers LVDSVec3V 101 103 PWR 3V power supply pins for LVDS output drivers 107 111 During power up stage voltage readings on these pins must be higher than 2 5V pins LVDSGND3V 102 106 PWR Ground return pins for 3V LVDS outputs 110 112 Note 11 When device power is applied it is possible for these outputs to switch to a logic 1 momentarily as the 3 3V is rising and before 2 5V reaches at least 0 8V During this brief period the pad control logic could be non deterministic RESETN will have no effect It is recommended these outputs are gated externally if the system design requires them to remain in the inactive logic O state during power on 15 www national com L0Sz906SC DS90C2501 DS90C2501 Pin Description Continued TABLE 1 scaler is powered down under these conditions scaler is On scaler is OFF PD pin H L DUAL pin Lor Voc Lor VeV c or VCC provided that PD bit is 1 and BYPASS bit is 0 No input clock is NO YES detected PD bit issued by 1 0 host BYPASS bit 0 1 issued by host Two Wire Serial
40. rom CLK1P rising edge Vec 0 49 0 49 Note 7 TPPOS2 Transmitter Output Pulse Position for Bit2 f 65 MHz DUAL pin 2 7 TCIP 2 7 TCIP 2 7 TCIP ns from CLK1P rising edge Note 7 Voc 0 49 0 49 TPPOS3 Transmitter Output Pulse Position for Bit3 f 65 MHz DUAL pin 3 7 TCIP 3 7 TCIP 3 7 TCIP ns from CLK1P rising edge Note 7 Voc 0 49 0 49 TPPOS4 Transmitter Output Pulse Position for Bit4 f 65 MHz DUAL pin 4 7 TCIP 4 7 TCIP 4 7 TCIP ns from CLK1P rising edge Note 7 Vec 0 49 0 49 TPPOS5 Transmitter Output Pulse Position for Bit5 f 65 MHz DUAL pin 5 7 TCIP 5 7 TCIP 5 7 TCIP ns from CLK1P rising edge Note 7 Voc 0 49 0 49 TPPOS6 Transmitter Output Pulse Position for Bit f 65 MHz DUAL pin 6 7 TCIP 6 7 TCIP 6 7 TCIP ns from CLK1P rising edge Note 7 Voc 0 49 0 49 TSTC DxIN Setup to CLKINP Figure 6 Note 7 0 8 ns THTC DxIN Hold to CLKINP Figure 6 Note 7 0 8 ns TJCC Transmitter Jitter Cycle to cycle Note 4 f 85 MHz DUAL pin 114 ps Gnd f 54 MHz DUAL pin 114 ps Voc TPLLS Transmitter Phase Lock Loop Set Figure 7 Note 7 10 ms TPDD Transmitter Powerdown Delay Figure 8 Note 7 100 ns Transmitter Input to Output Latency for f 170 MHz Note 6 1 5 TCIP ns single in to dual out mode Figure 9 4 1 www national com Two Wire Serial Communication Interface Switching Characteristics Unless otherwise not
41. s The transmitter can be programmed for rising edge strobe or falling edge strobe through a dedicated pin A rising edge transmitter will inter operate with a falling edge receiver without any translation logic Output Timing Control The DS90C2501 output timing is fully programmable through two wire serial communication Interface for different panel requirements When 6 bit color LCD is used dithering FRC can be turned on via two wire serial communication pro gramming interface The least two LSB of each color are default to be logic low all the time When 8 bit color LCD is used dithering FRC is not needed and can be turned off via two wire serial communication programming interface See DS90C2501 guide for further information on program ming these features 37 www national com L0GC0 06SA DS90C2501 Scaler Information Continued Pixels Scan Lines O Horizontal Sync Horizontal Back Porch Vertical Sync Vertical Back Porch Border Addressable Video Vertical Front Porch Horizontal Front Porch Video Syne Her H V Active Video Back Top Addressable Left E Porch Video Border Bottom Right Border Blan Active Video Data Enable H V Porch Data Enable 20004566 Back FIGURE 20 Input Timing of DS90C2501 scaler 2 of 2 20004567 www national com 38 Scaler
42. s mode outputs AO to A3 and CLK1 are enabled and outputs A4 to A7 and CLK2 are disabled which reduces power dissipation Features Description 2 Programmable Primary Edge E1 The transmitter is latching data on both the rising and falling edges of clock signal coming in on CLKINP pin The EDGE pin can be used to program to select the rising edge of CLKINP as the primary edge E1 or to have the falling edge of CLKINP as the primary edge E1 However the logic state of the EDGE pin must agree with the GUI to generate the correct display TABLE 10 Connection for SISO Operation From DS90C2501 RGB data signal connection DO DVOxDATAO D1 DVOxDATA1 D2 DVOxDATA2 D3 DVOXDATA3 DA DVOXDATA4 D5 DVOxDATAS D6 DVOxDATA6 D7 DVOxDATA7 D8 DVOXDATA8 D9 DVOXDATA9 D10 DVOXDATA10 D11 DVOxDATA11 D12 to D23 GND CLKINP DVOxCLKOUT1 CLKINM DVOxCLKOUTO DE DVOxBLANK IDO HSYNG VSYNC connection for other pins DUAL GND EDGE GND BAL GND AO Pull Up Pull Down Based on Device Address Al Pull Up Pull Down Based on Device Address A2 Pull Up Pull Down Based on Device Address Pull Up Pull Down Based on Panel ID ID1 Pull Up Pull Down Based on Panel ID ID2 Pull Up Pull Down Based on Panel ID ID3 Pull Up Pull Down Based on Panel ID RES1 GND RES2 GND RES3 GND RESI TSTI TST2 TST3 GND S2Cclk I2CCLK S2Cdat I2CDATA REFCLK 3V 14 31818MHz COLOR GND 4
43. t required power savings can be achieved in bypass mode DSEL 0 Input clock is differential recommended for clocks above 65 MHz 1 input clock is single ended HEN HSYNC enable 0 HSYNC is transmitted as a fixed low 1 HSYNC is same as input VEN VSYNC enable 0 VSYNC is transmitted as a fixed low 1 VSYNC is same as input 7 6 Reserved 19 www national com L0ST906SCA DS90C2501 Host Control Register Descriptions continued Register Name CFG2 Address Offset 09h Default Value 95h Access Method R W Bit Description 0 MDI read only 1 Reserved 2 RSEN read only Receiver Sense 0 LVDS receiver connected to transmitter output 1 No receiver connected Note this function is valid only with DC coupled systems 3 TSEL Interrupt generation O Interrupt bit MDI is generated by monitoring RSEN fixed valve 4 6 MSEL R W Selects source for MSEL output pin 000 MSEN disabled 001 Output the MDI bit interrupt 010 Output the RSEN bit receiver detect 011 111 Reserved 7 VLOW read only 1 Vpezr Set for low swing 0 Vpezr set for LVTTL Register Name CFG3 Address Offset OAh Default Value 81H Access Method R W Bit Description 0 R_FDE Input DE strobe Polarity Select 0 DE active Low 1 DE active High 3 1 Reserved 7 4 Reserved Register Name CFG Address Offset OBh Default Value See Description Access Method Read O
44. und Plane of PCB 45 www national com L0Sz906SC DS90C2501 Pin Diagram x a o o N n gt M a z o CLKINP jo CLKINM DS90C2501 SLB128B pej e E a o a a z o z z o o La S A I n v n a E E o o co N a a a a a ES GPIO2 EM GPIO3 ES ID3 EN AO Ea ID2 N o q o 0 w o o ure N gt N o 101 vj vele GND Ea BAL Ka RES3 ES IDO LVDSGND3V LVDSVe 3V LVDSGND3V LVDSVcq LVDSGND LVDSVe 3V LVDSGND3V LVDSVec LVDSGND LVDSVog3V LVDSGND3V LVDSVe 3V RES4 DUAL EI EDGE EI 20004564 www national com 46 Physical Dimensions inches millimeters unless otherwise noted 7 ci t DDDODDODODDO pt 1 TYP 128X 0 3 000000000000 128X 0 45 gas q 124X 0 5 B e 6 9 9 9 09 BSe0d00 E o000 4 TYP 25X D0 4 RECOMMENDED LAND PATTERN 1 1 RATIO WITH PACKAGE SOLDER PADS DIMENSIONS ARE IN MILLIMETERS IT TYP 128X 0 45 PAD 140 1 PIN 4 INDEX AREA i 0 36 10 06 1 es 0 510 1 57 56 AX 0 4940 1 PIN 1 IDENT L TYP a 25x 60 4 85 00 2X 0 510 1 O OO GNU N OUR A ROIO ROIO IONI 1040 1 ch Ama 64x JE 0 08 C 4x 2X 20 Ilo Je 128X 0 3 0 05 ES SLB128B Rev B Dimensions show in millimeters Order Number DS90C2501SLB NS Package Number SLB128B Refer to Application Note AN1125 for more i
45. wer sequencing m Support low voltage swing signal level 1V to 1 8V 2 5V and 3 3V LVTTL level on CLKINP CLKINM DO to D23 DE HSYNC and VSYNC pins m Support 2 5V 3 3V LVTTL level on configuration pins m Support 3 3V LVTTL level on GPIO pins m Available in 10mm x 10mm x 1mm 128pin thermally enhanced CSP package E Two wire serial communication interface is active during normal as well as power down mode and support data rates up to 400KHz m TIA EIA 644 Open LDI DVO compliance TRI STATE is a registered trademark of National Semiconductor Corporation DVO is a registered trademark of Intel Corporation AGP or 4x AGP is a registered trademark of Intel Corporation 2003 National Semiconductor Corporation DS200045 www national com 17 sve jHiajuj Aejdsia safi 104 49 e9S Ul ING YUM JayIWSUeIL LOSZOO6SA DS90C2501 Block Diagram 14 318 MHz Ref Clock Port 1 Primary Port 2 Secondary Clock Control Host F GPIO DVO Port 1 F Scalar Timing Control Configuration Test 170 Control Pins Control I ering l Port 1 Port 2 Panel ID Panel Power Control 20004552 www national com Absolute Maximum Ratings note 1 If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage Vec Supply Voltage Vecav CMOS TTL Input
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National DS90C2501 handbook