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National COP820CJ/COP822CJ/COP823CJ handbook

1. v de Oz df usn 184 194 vioOdi VX WX 64025 1 664001 8c dr zl de 4420 0020 4420 0020 4 alz a Y 1 a x d usn 91 184 YX WX 2 0 25 124001 ez dr l de 3410 0010 4410 0010 4 a a Y 1 2 d 8L dP usn 01 184 Oans voans 25 140 ZSua 19140 97 0 vi dP 3400 0000 4400 0000 4 ao al l YINI ZL df usr 0 3 841 40 184 Yoav voav 0 0 25 18004001 16 St df 0 L e S 9 1 8 6 v a 3 d sua 22 http www national com Instruction Execution Time Most instructions are single byte with immediate address ing mode instruction taking two bytes Most single instructions take one cycle time to execute Skipped instructions require x number of cycles to be skipped where x equals the number of bytes in the skipped instruction opcode See the BYTES and CYCLES per INSTRUCTION table for details Bytes and Cycles per Instruction The following table shows the number of bytes and cycles for each instruction in the format of byte cycle Arithmetic Instructions Bytes Cycles B Direct Immed ADD 1 1 3 4 2 2 ADC 1 1 3 4 2 2 SUBC 1 1 3 4 2 2 AND 1 1 3 4 2 2 OR 1 1 3 4 2 2 XOR 1 1 3 4 2 2 IFEQ 1 1 3 4 2 2
2. Instr HC Flag C Flag ADC Depends on Operands Depends on Operands SUBC Depends on Operands Depends on Operands SETC Set Set RESET C Set Set RRC Depends on Operands Depends on Operands CNTRL2 REGISTER ADDRESS 00CC Bit 7 Bit 0 MC3 R W MC2 R W MC1 R W CMPEN CMPRD R W R O CMPOE R W WDUDF R O unused MC3 MC2 MC1 CMPEN CMPRD CMPOE WDUDF Modulator Timer Control Bit Modulator Timer Control Bit Modulator Timer Control Bit Comparator Enable Bit Comparator Read Bit Comparator Output Enable Bit WATCHDOG Timer Underflow Bit Read Only WDREG REGISTER ADDRESS 00CD WDREN WATCHDOG Reset Enable Bit Write Once Only Bit 7 Bit 0 UNUSED WDREN 19 http www national com Memory Map All RAM ports and registers except A and PC are mapped into data memory address space TABLE IX Memory Map Address Contents 00to2F On chip RAM bytes 48 bytes 30to7F Unused RAM Address Space Reads as All Ones 80to BF Expansion Space for On Chip EERAM Reads Undefined Data CO to C7 Reserved C8 MIWU Edge Select Register Reg WKEDG C9 MIWU Enable Register Reg WKEN CA MIWU Pending Register Reg WKPND CB Reserved cc Control2 Register CNTRL2 CD WATCHDOG Register WDREG CE WATCHDOG Counter WDCNT CF Modulator Reload MODRL DO Port L Data Register D1 Port L Configuration Regist
3. Tl 16 BIT TIMER TL DD 11208 25 FIGURE 10 Timer Capture Mode Block Diagram TIMER PWM APPLICATION Figure 11 shows how a minimal component D A converter can be built out of the Timer Register pair in the Auto Re load mode The timer is placed in the Timer with auto re load mode and the TIO pin is selected as the timer output At the outset the TIO pin is set high the timer T1 holds the on time and the register R1 holds the signal off time Setting TRUN bit starts the timer which counts down at the instruc tion cycle rate The underflow toggles the TIO output and copies the off time into the timer which continues to run By alternately loading in the on time and the off time at each successive interrupt a PWM frequency can be easily gener ated Ton Tort 2 c m SIMPLE D A 7 CONVERTER USING 5 THE TIMER TO s GENERATE A PWM OUTPUT TL DD 11208 26 FIGURE 11 Timer Application Watchdog The device has an on board 8 bit WATCHDOG timer The timer contains an 8 bit READ WRITE down counter clocked by an 8 bit prescaler Under software control the timer can be dedicated for the WATCHDOG or used as a general pur pose counter Figure 12 shows the WATCHDOG timer block diagram MODE 1 WATCHDOG TIMER The WATCHDOG is designed to detect user programs get ting stuck in infinite loops resulting in loss of program con trol or runaway programs The WATCHDOG can be en abled or disabled only once after the d
4. 0 COPS LZOCJM NIFT QN vationat Semiconductor COP820CJ COP822CJ COP823CJ 8 Bit Microcontroller with Multi Input Wake Up and Brown Out Detector General Description The COP820CJ is a member of the COP8 8 bit Microcon troller family It is a fully static Microcontroller fabricated using double metal silicon gate microCMOS technology This low cost Microcontroller is a complete microcomputer containing all system timing interrupt logic ROM RAM and 1 necessary to implement dedicated control functions in variety of applications Features include an 8 bit memory mapped architecture MICROWIRE serial I O a 16 bit timer counter with capture register a multi sourced inter rupt Comparator WATCHDOG Timer Modulator Timer Brown out protection and Multi Input Wakeup Each 1 pin has software selectable options to adapt the device to the specific application The device operates over a voltage range of 2 5V to 6 0V High throughput is achieved with an efficient regular instruction set operating at a 1 ws in struction rate Key Features W Multi Input Wake Up on the 8 bit Port L W Brown out detector W Analog comparator W Modulator timer High speed PWM for IR transmission 16 bit multi function timer supporting PWM mode External event counter mode Input capture mode W 1024 bytes of ROM m 64 bytes of RAM 1 O Features m Memory mapped 1 September 1996 W Software selectable 1
5. IFGT 1 1 3 4 2 2 IFBNE 1 1 DRSZ 1 3 SBIT 1 1 3 4 RBIT 1 1 3 4 IFBIT 1 1 3 4 Memory Transfer Instructions Bytes Cycles Register Register Indirect Indirect Direct Immed Auto Incr amp Decr B IX B B X X 1 1 1 3 2 3 1 2 1 3 LD A 1 1 1 3 2 3 2 2 1 2 1 3 LD 1 1 IFB 16 LD B Imm 2 3 gt 15 LD Mem Imm 3 3 2 2 LD Reg Imm 2 3 gt Memory location addressed by B or X or directly Instructions Using A amp C Instructions Bytes Cycles CLRA 1 1 INCA 1 1 DECA 1 1 LAID 1 3 DCORA 1 1 RRCA 1 1 SWAPA 1 1 SC 1 1 RC 1 1 IFC 1 1 IFNC 1 1 Transfer of Control Instructions Instructions Bytes Cycles JMPL 3 4 JMP 2 3 JP 1 3 JSRL 3 5 JSR 2 5 JID 1 3 RET 1 5 RETSK 1 5 RETI 1 5 INTR 1 7 NOP 1 1 23 http www national com Bytes and Cycles per Instruction continued The following table shows the instructions assigned to un used opcodes This table is for information only The opera tions performed are subject to change without notice Do not use these opcodes OPTION 2 BROWN OUT 1 Enable Brown Out Detection 2 Disable Brown Out Detection OPTION 3 BONDING 1 28 DIP osa Instruction bi Instruction 2 20 DIP SO prode proce 3 16 SO 60 NOP AQ NOP 28 pin SO 61 NOP AF LD A B 62 NOP B1 HC Development Support 63 NOP B4 NOP 67 NOP B5 NOP SUMMAR
6. IMMEDIATE The instruction contains an 8 bit immediate field as the op erand SHORT IMMEDIATE This addressing mode issued with the LD instruction where the immediate is less than 16 The instruction con tains a 4 bit immediate field as the operand INDIRECT This addressing mode is used with the LAID instruction The contents of the accumulator are used as a partial address lower 8 bits of PC for accessing a data operand from the program memory TRANSFER OF CONTROL ADDRESSING MODES RELATIVE This mode is used for the JP instruction with the instruction field being added to the program counter to produce the next instruction address JP has a range from 31 to 32 to allow a one byte relative jump JP 1 is implemented by a NOP instruction There are no blocks or pages when using JP since all 15 bits of the PC are used ABSOLUTE This mode is used with the JMP and JSR instructions with the instruction field of 12 bits replacing the lower 12 bits of the program counter PC This allows jumping to any loca tion in the current 4k program memory segment ABSOLUTE LONG This mode is used with the JMPL and JSRL instructions with the instruction field of 15 bits replacing the entire 15 bits of the program counter PC This allows jumping to any loca tion in the entire 32k program memory space INDIRECT This mode is used with the JID instruction The contents of the accumulator are used as a partial address lower 8
7. L2 CMPIN4 7 L2 CMPIN gals 13 TL DD 11208 5 TL DD 11208 4 Top View View Order Number COPCJ823 XXX WM TL DD 11208 3 Order Number COPCJ822 XXX N or Top View COPCJ822 XXX WM Order Number COPCJ820 XXX N or COPCJ820 XXX WM FIGURE 3 Connection Diagrams http www national com 4 Typical Performance Characteristics Dynamic lpp vs Vcc Crystal Clock Option 1MHz 0 35 40 45 50 55 60 Vec V Ports L G Weak Pull Up Source Current 120 pup 3 V n 77 V Ports 14 17 Sink Current lo mA 0 0 5 1 0 1 5 20 25 3 0 3 5 40 45 V mA lop mA HA Brown Out Voltage V 0 55 o ROO OO Halt lpp vs Vcc Brown Out Disabled 2025 0 35 40 45 50 55 60 Yoo V Ports L G Push Pull Source Current 9 Brown Out Voltage vs Temperature Temperature C 4 lo mA lo Halt lpp vs Vcc Brown Out Enabled 50 45 40 35 30 25 20 15 40 42 44 46 48 5 0 5 2 54 5 6 58
8. 6 3480 0080 4480 0080 ale al e 1 8 L df 82 usn gSOdN8dl VO3d vai 830zsua 18 84001 0 0 00 44 00 0 1816 alz a a x LE de Z2 usr VOANGsI 8 801 185 YONI di vai vaozsua Le dn 9 3460 0060 4460 0060 a gll 4 4 OL 9 de usn 6dN8dl 9807 Lids 630 ZSua 15 640011 22 9 4480 0080 4480 0080 Slo 810 1 x 6 d Sc usr 8SJN8dl 24 val dON 8 0 ZSHC 840 07 6 2 3340 0040 4420 0020 1814 8 v l usn 2 184 Y HO 430 26 240 01 amp dn 3490 0090 4490 0090 al 9 a Y 1 a x L df df usn 9d3N8d 6 vHOOG 184 HOX VX VX 940258 940 G1 SZ df 6 3480 0080 4480 0080 1818 a Y l 9 d 2c dr usr S3N84l 8 C1 VdvMS 1841 830 25 S40 C1 92 01 A4v0 00r0 4490 0080 a a Y l S d let dr usn 184 Gav 40 ZSUG 40 01 4 3480 0060 4480 0060 al v 1 8
9. 6 0 Yoo 09 Ports L G Push Pull Sink Current 18 ae 16 oT Voc 6 0V 4 20 02 0 05 10 15 20 25 30 35 VoL V Port D Sink Current 45 mm 35 a ec 4 30 4 5 20 4 te 15 74 19 J Voc 2 5V BER 814 0 0 05 10 15 20 25 3 0 3 5 4 0 4 5 Vo V TL DD 11208 28 http www national com COP820CJ Pin Assignment Port Typ ALT 16 20 Funct Pin Pin Pin LO MIWU CMPOUT 5 7 11 L1 MIWU CMPIN 6 8 12 L2 MIWU CMPIN 7 9 13 L3 MIWU 8 10 14 L4 MIWU 9 11 15 L5 MIWU 10 12 16 L6 MIWU 11 13 17 L7 MIWU MODOUT 12 14 18 GO INTR 17 25 G1 18 26 92 19 27 TIO 15 20 28 G4 O SO 1 1 G5 O SK 16 2 2 G6 5 1 3 3 G7 CKO 2 4 4 10 7 H 8 12 9 I3 10 DO 19 D1 20 D2 21 D3 22 4 6 6 GND 13 15 23 CKI 3 5 5 RESET 14 16 24 Pin Description Vcc and GND are the power supply pins is the clock input This can come from an external source a R C generated oscillator or a crystal in conjunc tion with CKO See Oscillator description RESET is the master reset input See Reset description PORT 1 is a 4 bit Hi Z input port PORT L is an 8 bit I O port There are two registers associated with the L port a data register and a configurati
10. 623 8860 Call Asia 886 2 764 0215 Fax 886 2 756 6403 ICE 800 624 8949 44 1226 767404 Technology 919 430 7915 Fax 0 1226 370 434 MetaLink 800 638 2423 49 80 9156 96 0 852 737 1800 602 926 0797 Fax 49 80 9123 86 Fax 602 693 0681 Systems 408 263 6667 41 1 9450300 886 2 917 3005 General Fax 886 2 911 1283 Needhams 916 924 8037 Fax 916 924 8065 27 http www national com Development Support continued SINGLE CHIP OTP EMULATOR SUPPORT The COP8 family is supported by single chip emula tors For detailed information refer to the emulator specific datasheet and the emulator selection table below OTP Emulator Ordering Information Device Number Glock Package Emulates Option COP87L22CJN 1N Crystal 20 DIP COP822CJ COP87L22CJN 2N External 20 DIP COP822CJ COP87L22CJN 3N R C 20 DIP COP822CJ COP87L22CJM 1N Crystal 20 SO COP822CJ COP87L22CJM 2N External 20 SO COP822CJ COP87L22CJM 3N R C 20 SO COP822CJ COP87L20CJN 1N Crystal 28 DIP COP820CJ COP87L20CJN 2N External 28 DIP COP820CJ COP87L20CJN 3N R C 28 DIP COP820CJ COP87L20CJM 1N Crystal 28 SO COP820CJ COP87L20CJM 2N External 28 SO COP820CJ COP87L20CJM 3N R C 28 SO COP820CJ INDUSTRY WIDE OTP EPROM PROGRAMMING SUPPORT Programming support in addition to the MetaLink develop ment tools is provided by a full range of independent ap proved vendors to meet the needs f
11. OOEE The Timer and MICROWIRE control register contains the following bits SL1 and SLO Select the MICROWIRE clock divide by 00 2 01 4 1x 8 IEDG External interrupt edge polarity select MSEL Selects G5 and G4 as MICROWIRE signals SK and SO respectively TRUN Used to start and stop the timer counter 1 run O stop TC1 Timer T1 Mode Control Bit TC2 Timer T1 Mode Control Bit Timer T1 Mode Control Bit Bit 7 Bit 0 TC1 TC2 TC3 TRUN MSEL IEDG SL1 510 PSW REGISTER ADDRESS 00 The PSW register contains the following select bits GIE Global interrupt enable enables interrupts ENI External interrupt enable BUSY MICROWIRE busy shifting flag PND External interrupt pending ENTI Timer T1 interrupt enable TPND Timer T1 interrupt pending timer Underflow or capture edge Carry Flip Flop HC Half Carry Flip Flop Bit 7 Bit 0 HC C TPND ENTI IPND BUSY ENI GIE The Half Carry bit is also effected by all the instructions that effect the Carry flag The flag values depend upon the in struction For example after executing the ADC instruction the values of the Carry and the Half Carry flag depend upon the operands involved However instructions like SET C and RESET C will set and clear both the carry flags Table XIII lists the instructions that effect the HC and the C flags TABLE XIII Instructions Effecting HC and C Flags
12. bits of PC for accessing a location in the program memory The contents of this program memory location serves as a par tial address lower 8 bits of PC for the jump to the next instruction http www national com 20 Instruction Set REGISTER AND SYMBOL DEFINITIONS Symbols B Memory indirectly addressed by B register Registers Hen A 8 bit Accumulator register X Memory indirectly addressed by X register B 8 bit Address register Mem Direct address memory or B 8 bit Address register Meml Direct address memory or B or Immediate data Imm 8 bit Immediate data Reg Register memory addresses FO to FF Includes B X and SP Bit Bit number 0 to 7 Loaded with with SP 8 bit Stack pointer register PC 15 bit Program counter register PU upper 7 bits of PC PL lower 8 bits of PC C 1 bit of PSW register for carry HC Half Carry GIE 1 bit of PSW register for global interrupt enable Instruction Set ADD add A lt A ADC add with carry A lt A C C lt Carry HC Half Carry SUBC subtract with carry A lt A C Carry HC lt Half Carry AND Logical AND A Aand OR Logical OR A lt Memli XOR Logical Exclusive OR A IFEQ IF equal Compare A and Meml Do next if A IFGT IF greater than Compare A and Meml Do next if A gt IF
13. controlled oscillator Table 1 shows the component values required for various standard crystal values R C OSCILLATOR By selecting CKI as a single pin oscillator CKI can make a R C oscillator CKO is available as a general purpose input and or HALT control Table Il shows variation in the oscilla tor frequencies as functions of the component R and C values Ju EXTERNAL CLOCK RESTART TL DD 11208 7 FIGURE 5 Clock Oscillator Configurations TABLE I Crystal Oscillator Configuration R1 R2 C1 c2 CKI Freq bons MQ pF pF MHz 0 1 30 30 36 10 Voc 5V 0 1 30 30 36 4 Voc 5V 5 6 1 100 100 156 0 455 Voc 5V TABLE Il RC Oscillator Configuration Part To Part Variation ae cal 2 D eaae 3 3 82 2 2 to 2 7 3 7 to 4 6 Voc 5V 5 6 100 1 1t01 3 7 4 to 9 0 Voc 5V 6 8 100 0 9 to 1 1 8 8 to 10 8 Voc 5V http www national com Functional Description continued Halt Mode The device is a fully static device The device enters the HALT mode by writing a one to the G7 bit of the G data register Once in the HALT mode the internal circuitry does not receive any clock signal and is therefore frozen in the exact state it was in when halted In this mode the chip will only draw leakage current output current and DC current due to the Brown Out circuit if Brown Out is enabled The device supports four different m
14. entering special modes Also keep the external loading on D2 to less than 1000 pF Functional Description The internal architecture is shown in the block diagram Data paths are illustrated in simplified form to depict how the various logic elements communicate with each other in implementing the instruction set of the device ALU and CPU Registers The ALU can do an 8 bit addition subtraction logical or shift operations in one cycle time There are five CPU regis ters A is the 8 bit Accumulator register PC the 15 bit Program Counter register PU is the upper 7 bits of the program counter PC PL is the lower 8 bits of the program counter PC B is the 8 bit address register and can be auto incre mented or decremented X is the 8 bit alternate address register and can be auto incremented or decremented SP is the 8 bit stack pointer which points to the subrou tine stack in RAM B X and SP registers are mapped into the on chip RAM The B and X registers are used to address the on chip RAM The SP register is used to address the stack in RAM during subroutine calls and returns The SP must be preset by soft ware upon initialization Memory The memory is separated into two memory spaces program and data PROGRAM MEMORY Program memory consists of 1024 x 8 ROM These bytes of ROM may be instructions or constant data The memory is addressed by the 15 bit program counter PC ROM can be indirectly read by the L
15. its register R1 are each organized as two 8 bit read write registers Control bits in the register CNTRL allow the timer to be started and stopped under software control The timer register pair can be operated in one of three possible modes Table V details various timer operating modes and their requisite control settings MODE 1 TIMER WITH AUTO LOAD REGISTER In this mode of operation the timer T1 counts down at the instruction cycle rate Upon underflow the value in the regis ter R1 gets automatically reloaded into the timer which con tinues to count down The timer underflow can be pro grammed to interrupt the microcontroller A bit in the control register CNTRL enables the TIO G3 pin to toggle upon timer underflows This allows the generation of square wave outputs or pulse width modulated outputs under software control Figure 8 MODE 2 EXTERNAL COUNTER In this mode the timer T1 becomes a 16 bit external event counter The counter counts down upon an edge on the TIO pin Control bits in the register CNTRL program the counter to decrement either on a positive edge or on a negative edge Upon underflow the contents of the register R1 are automatically copied into the counter The underflow can also be programmed to generate an interrupt Figure 9 INTERNAL DATA BUS R1 16 BIT AUTO TIMER UNDERFLOW RELOAD REC INTERRUPT TIO OUTPUT T1 16 BIT TIMER COUNTER TL DD 11208 24 FIGURE 8 Time
16. reset takes priority over Brown Out Reset and will deactivate the 256 tc cycles delay if in progress The Brown Out reset takes priority over the WATCHDOG reset The following actions occur as a result of Brown Out reset Port L TRI STATE Port G TRI STATE Port D HIGH PC CLEARED RAM Contents RANDOM B X SP UNKNOWN PSW CNTRL1 CNTRL2 and WDREG Registers CLEARED Multi Input Wakeup Registers WKEDG WKEN CLEARED WKPND UNKNOWN Data and Configuration Registers for L amp G CLEARED WATCHDOG Timer Prescalar Counter each loaded with FF Unknown data after coming out of the HALT through Brown Out Reset with any Clock Timer T1 and Accumulator Port L TRI STATE option Port G TRI STATE Note The development system will detect the BROWN OUT RESET exter Port D HIGH low Development System PC CLEARED Brown Out Detection Ram Contents UNCHANGED An on board detection circuit monitors the operating voltage B X SP UNCHANGED Vcc and compares it with the minimum operating voltage PSW CNTRL1 and CNTRL2 except WDUDF Bit Registers CLEARED Multi Input Wakeup Registers WKEDG WKEN CLEARED WKPND UNKNOWN Data and Configuration Registers for L amp G CLEARED WATCHDOG Timer Prescalar Counter each loaded with BROWN OUT RESET The on board Brown Out protection circuit resets the device when the operating voltage Vcc is lower
17. than the Brown Out voltage The device is held in reset when Vcc stays below the Brown Out Voltage The device will remain in specified The Brown Out circuit is designed to reset the device if the operating voltage is below the Brown Out volt age between 1 8V to 4 2V at 40 C to 85 C The Mini mum operating voltage for the device is 2 5V with Brown Out disabled but with BROWN OUT enabled the device is guaranteed to operate properly down to minimum Brown Out voltage Max frequency 4 MHz For temperature range of 0 C to 70 C the Brown Out voltage is expected to be between 1 9V to 3 9V The circuit can be enabled or dis abled by Brown Out mask option If the device is intended to operate at lower Vcc lower than Brown Out voltage VBO max the Brown Out circuit should be disabled by the mask option The Brown Out circuit may be used as a power up reset provided the power supply rise time is slower than 50 us OV to 6 0V Note Brown Out Circuit is active in HALT mode with the Brown Out mask option selected http www national com Functional Description continued Oscillator Circuits EXTERNAL OSCILLATOR CKI can be driven by an external clock signal provided it meets the specified duty cycle rise and fall times and input levels CKO is available as a general purpose input G7 and or Halt control CRYSTAL OSCILLATOR By selecting CKO as a clock output CKI and CKO can be connected to create a crystal
18. 1 0 lt i JID Jump indirect PL lt ROM PU A RET Return from subroutine SP 2 PL lt SP PU lt SP 1 RETSK Return and Skip SP 2 PL lt SP PU lt SP 1 Skip next instruction RETI Return from Interrupt SP 2 PL lt SP PU SP 1 GIE lt 1 INTR Generate an interrupt SP PL SP 1 lt PU SP 2 PC OFF NOP No operation PC lt PC 1 21 http www national com Bits 3 0 OPCODE LIST 0 ees epoodo pesnun ue SI uoneoo 81 S 1 3440 0040 4440 0040 84 gl x 4 9L df ZE df usr 40 0801 86 1138 340 ZSUC 19 44001 91 0 3430 0030 4430 0030 a 9 a 9 181 x SL df IE d usn lias 138 vai aaozsua 34007 Zi df 4440 0000 4410 0000 Ss al s PIN vl df 0 df usn z 8dl 85 1 WaT Just G40ZSud 16404001 4490 0000 4400 0090 gv a 4 l L df 62 dr usn X 930 25 o30G1
19. 2 5V Vcc lt 4 5 500 ns tHold 4 5V lt Vcc lt 6 0V 60 ns 2 5V lt Voc lt 4 5 150 ns Output Propagation Delay Rp 2 2k CL 100 pF tppo SO SK 4 5V Voc lt 6 0V 0 7 ps 2 5V lt Vcc lt 4 5 1 75 ps All Others 4 5V lt Vcc lt 6 0V 1 ps 2 5V Voc lt 4 5V 5 ps Input Pulse Width Interrupt Input High Time 1 tc Interrupt Input Low Time 1 tc Timer Input High Time 1 tc Timer Input Low Time 1 tc MICROWIRE Setup Time t ws 20 ns MICROWIRE Hold Time t wg 56 ns MICROWIRE Output 220 ns Propagation Delay t pp Reset Pulse Width 1 0 ps Note 5 Parameter characterized but not production tested http www national com AC Electrical Characteristics continued FIGURE 2 MICROWIRE PLUS Timing TL DD 11208 2 Comparator DC and AC Characteristics v lt voc lt ev 40 lt lt 85 C Note 1 Parameters Conditions Min Type Max Units Input Offset Voltage 0 4V lt Vin lt Voc 1 5V 10 25 mV Input Common Mode Voltage Range 0 4 Vcc 1 5 V Voltage Gain V V DC Supply Current when enabled Voc 6 0V 250 pA Response Time TBD mV Step 1 is TBD mV Overdrive 100 pF Load Note 1 For comparator output current characteristics see L Port specs Connection Diagrams 64 50 65 5 66 si 1 96 51 7 4 2 07 Veo 4 L0 CMPOUT 5 LO CMPOUT L1 CMPIN 6 L1 CHPIN
20. 700 5400 457 0 os 0058 1 270 0 381 2 540 0 254 0 457 0 076 3 175 3 683 1 025 0 015 15 88 E N28B REV E 28 Lead Molded Dual In Line Package N Order Number COPCJ820 XXX N NS Package Number N28B LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or Systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 N National Semiconductor National Semiconductor Europe Fax Email 49 0 180 530 85 86 europe supporte nsc com Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tel 1 800 272 9959 Deutsch Tel 49 0 180 530 85 85 Tsimshatsui Kowloon Fax 1 800 737 7018 English Tel 49 0 180 532 78 32 Ho
21. AID instruction for table lookup DATA MEMORY The data memory address space includes on chip RAM I O and registers Data memory is addressed directly by the in struction or indirectly through B X and SP registers The device has 64 bytes of RAM Sixteen bytes of RAM are mapped as registers these can be loaded immediately decremented and tested Three specific registers X B and SP are mapped into this space the other registers are avail able for general usage Any bit of data memory can be directly set reset or tested All I O and registers except A and PC are memory mapped therefore I O bits and register bits can be directly and individually set reset and tested except the write once only bit WDREN WATCHDOG Reset Enable and the un used and read only bits in CNTRL2 and WDREG registers Note RAM contents are undefined upon power up Reset EXTERNAL RESET The RESET input pin when pulled low initializes the micro controller The user must insure that the RESET pin is held low until Vcc is within the specified voltage range and the clock is stabilized An R C circuit with a delay 5x greater than the power supply rise time is recommended Figure 4 The device immediately goes into reset state when the RESET input goes low When the RESET pin goes high the device comes out of reset state synchronously The device will be running within two instruction cycles of the RESET pin going high The following actions occ
22. BNE IF B not equal Do next if lower 4 bits of B Imm DRSZ Decrement Reg skip if zero Reg lt Reg 1 skip if Reg goes to 0 SBIT Set bit 1 to bit Mem bit 0 to 7 immediate RBIT Reset bit O to bit Mem IFBIT f bit If bit Mem is true do next instr X Exchange A with memory A Mem LDA Load A with memory A LD mem Load Direct memory Immed Mem Imm LD Reg Load Register memory Immed Reg Imm X Exchange A with memory B lt lt 1 X Exchange A with memory X lt gt X X 1 LDA Load A with memory B A B lt B 1 LDA Load A with memory X A X X lt 1 LDM Load Memory Immediate B lt Imm B lt B 1 CLRA Clear A A lt 0 INCA ncrement A 1 DECA Decrement A lt A 1 LAID Load A indirect from ROM A ROM PU A DCORA DECIMAL CORRECT A A BCD correction follows ADC SUBC RRCA ROTATE A RIGHT THRU C C 7 0 SWAPA Swap nibbles of A A7 A4 lt A3 A0 SC SetC C lt 1 1 RC Reset C lt 0 lt 0 If C If C is true do next instruction IFNC If not C If C is not true do next instruction JMPL Jump absolute long PC lt ii ii 15 bits 0 to 32k JMP Jump absolute PC11 0 i i 12bits JP Jump relative short PC r ris 31 to 32 not 1 JSRL Jump subroutine long SP lt PL SP 1 PU SP 2 PC lt ii JSR Jump subroutine SP lt PL SP 1 PU SP 2 PC1
23. CKI inverter on the chip ensures that the WATCHDOG timer is clocked only when the oscillator has a sufficiently large amplitude to meet the Schmitt trigger specs This Schmitt trigger is not part of the oscillator closed loop The start up timeout from the WATCHDOG timer enables the clock sig nals to be routed to the rest of the chip The delay is not activated when the device comes out of HALT mode through RESET pin Also if the clock option is either RC or External clock the delay is not used but the WATCHDOG Prescaler Counter contents are changed The Develop ment System will not emulate the 256tc delay The RESET pin or Brown Out will cause the device to reset and start executing from address X 0000 A low to high tran sition on the G7 pin if single pin oscillator is used or Multi Input Wakeup will cause the device to start executing from the address following the HALT instruction When RESET pin is used to exit the device from the HALT mode and the two pin crystal resonator CKI CKO clock option is selected the contents of the Accumulator and the Timer T1 are undetermined following the reset All other information except the WATCHDOG Prescaler Counter contents is retained until continuing If the device comes out of the HALT mode through Brown Out reset the contents of data registers and RAM are unknown following the reset All information except the WATCHDOG Prescaler Counter contents is retained if the device exits the HALT m
24. GIE bit high inside the interrupt subroutine allows nested interrupts EXTERNAL INT PIN TIMER UNDERFLOW SOFTWARE INTERRUPT The software interrupt does not reset the GIE bit This means that the controller can be interrupted by other inter rupt sources while servicing the software interrupt INTERRUPT PROCESSING The interrupt once acknowledged pushes the program counter PC onto the stack and the stack pointer SP is decremented twice The Global Interrupt Enable GIE bit is reset to disable further interrupts The microcontroller then vectors to the address OOFFH and resumes execution from that address This process takes 7 cycles to complete At the end of the interrupt subroutine any of the following three instructions return the processor back to the main pro gram RET RETSK or RETI Either one of the three instruc tions will pop the stack into the program counter PC The stack pointer is then incremented twice The RETI instruc tion additionally sets the GIE bit to re enable further inter rupts Any of the three instructions can be used to return from a hardware interrupt subroutine The RETSK instruction should be used when returning from a software interrupt subroutine to avoid entering an infinite loop Note There is always the possibility of an interrupt occurring during an in struction which is attempting to reset the GIE bit or any other interrupt enable bit If this occurs when a single cycle inst
25. OFTWARE TL DD 11208 16 http www national com Modulator Timer continued INTERNAL DATA BUS 0 CNTRL2 REGISTER L7 PIN L7 DATA LATCH MODRL AUTO RELOAD MC3 MC2 MC1 REGISTER 8 BIT 0 1 te CLK DOWN COUNTER 8 BIT NN START STOP 4 1 41 1 258 tc MAX TL DD 11208 17 TL DD 11208 18 FIGURE 14 Mode 2a 50 Duty Cycle Output INTERNAL DATA BUS n 6 5 0 MODRL AUTO RELOAD MC3 MC2 MC1 CNTRL2 REGISTER 8 BIT z 1 ROS REGISTER CLK UNDERFLOW TIMER T1 UNDERFLOW DOWN COUNTER 8 BIT START STOP TL DD 11208 19 TIMER T1 8 BIT COUNTER UNDERFLOW UNDERFLOW ce Iris 256 t MAX CONTROLLED BY T1 FIGURE 15 Mode 2b Variable Duty Cycle Output TL DD 11208 20 http www national com 16 Comparator The device has one differential comparator Ports 10 12 are used for the comparator The output of the comparator is brought out to a pin Port L has the following assignments LO Comparator output L1 Comparator negative input L2 Comparator positive input THE COMPARATOR STATUS CONTROL BITS These bits reside in the CNTRL2 Register Address CMPEN Enables comparator 1 enable CMPRD Reads comparator output internally CMPEN 1 CMPOE X CMPOE Enables comparator output to pin LO 1 enable CMPEN bit must be set to en able this function If CMPEN 0 LO will be 0 The Comparator Select Control bit
26. PS ALL LEADS 0 0160 0 0500 0402127 TYP ALL LEADS M16B REV 16 Lead Molded Package S O M Order Number COPCJ823 XXX WM NS Package Number M16B 0 496 0 512 12 598 13 005 20 19 18 17 16 15 4 13 1211 A 0 394 0 419 10 008 10 643 30 TYP LEAD NO 1 IDENT Y 2 10 0 010 0 254 0 000 0 028 0 093 0 104 45 2 362 2 642 0 254 0 737 0 004 0 012 0 102 0 305 8 MAX TYP ALL LEADS 0 004 Ed 2 9 009 0 013 ATA 7358 B 0 102 0 016 0 050 0 356 gt EE ESN 0 229 0 330j ALL LEAD TIPS 0 406 1 270 Me ALL LEADS TYP ALL LEADS 20 Lead Surface Mount Package M Order Number COPCJ822 XXX WM NS Package Number M20B ine aM PLANE 0 050 0 014 0 020 0 014 0 020 1 270 0 356 0 508 0 008 0 203 MaB iRev F http www national com 30 Physical Dimensions inches millimeters unless otherwise noted Continued 0 300 7 60 0 291 7 40 0 420 10 65 0 393 10 00 0 030 0 75 x459 0 009 0 25 0 713 18 10 mH 0 696 17 70 zx 0 013 0 32 ieee 0 009 0 23 0 105 2 65 0 092 2 35 89 12112 0 012 0 30 0 003 0 10 0 050 1 27 0 020 0 49 BSC 0 013 0 35 0 050 1 27 dno 0 015 0 40 28 Lead Molded Package S O M Order Number COPCJ820 X
27. Wide Web Browser ftp nscmicro nsc com National Semiconductor on the WorldWide Web See us on the WorldWide Web at http www national com CUSTOMER RESPONSE CENTER Complete product information and technical support is avail able from National s customer response centers CANADA U S Tel 800 272 9959 email support tevm2 nsc com EUROPE email europe support nsc com Deutsch Tel 49 0 180 530 85 85 English Tel 49 0 180 532 78 32 Frangais Tel 49 0 180 532 93 58 Italiano Tel 49 0 180 534 16 80 JAPAN Tel 81 043 299 2309 S E ASIA Beijing Tel 86 10 6856 8601 Shanghai Tel 86 21 6415 4092 Hong Kong Tel 852 2737 1600 Korea Tel 82 2 3771 6909 Malaysia Tel 60 4 644 9061 Singapore Tel 65 255 2226 Taiwan Tel 886 2 521 3288 AUSTRALIA Tel 61 3 9558 9999 INDIA Tel 91 80 559 9467 http www national com 29 http www national com Physical Dimensions inches millimeters unless otherwise noted 0 5977 0 4133 10 10 10 50 LEAD NO 1 IDENTIFICATION 0 5940 0 4190 10 00 10 65 0 0158 0 0200 0 010 0 550 0 508 0 25 a cO 0 010 0 029 0 0091 0 0125 0 0926 0 1043 __ A Serene je o 23032 ALL LEADS 25972 65 0 0040 0 0118 4 0 1 0 3 i SEATING Dus mm p ALL LEAD TI
28. XX WM NS Package Number M28B 1 013 1 040 0 092 X 0 030 25 73 28 42 2 337 X 0 0 032 0 2 337 X 0 762 21 5 8 0 005 MAX DP 0 813 0 127 RAD 0 260 0 005 6 604 0 127 PIN NO 1 pui PIN NO 1 IDENT Jun m OPTION 1 MIN 0 300 0 320 pesos 1 620 8 128 0 060 NOM 0 040 OPTION 2 0 130 0 005 15524 4 4 AX 1307 01231 a Es se 0 127 0 145 0 200 3 683 5 080 0 009 0 015 90 0 004 10228 0301 223 0 381 0 020 ce 0 100 0 010 al m 0 125 0 140 0 508 aoso 20 0 060 0 005 2 540 50 554 0 018 0 003 3 175 3 556 0325 m 11 524 0 127 127 0 457 0 076 1016 ass 71016 OPTION 2 N20A REV G 20 Lead Molded Dual In Line Package N Order Number COPCJ822 XXX N NS Package Number N20A 31 http www national com with Multi Input Wake Up and Brown Out Detector COP820CJ COP822CJ COP823CJ 8 Bit Microcontroller Physical Dimensions inches millimeters unless otherwise noted Continued 0 510 0 005 12 95 0 127 1 393 1420 85 38 36 07 0 030 yay 0 600 0 620 0 145 0 210 00 0 762 15 24 15 75 3 683 5 334 1 270 1 125 0 165 8175 4 191 0 020 us 508 M e 5 0 009 0 015 us 86 94 TYP 0 229 0 381 0 580 0 050 0 015 0 018 0 003 0 125 0 145 13 0 100 0 010 473 gt 1 2
29. Y 8C RET B7 XA X iceMASTERTM IM COP8 400 Full feature in circuit em 99 NOP B9 NOP ulation for all products A full set of COP8 Basic OF LD B i BF LDA X and Feature Family device and package specific probes are available gin e COP8 Debug Module Moderate cost in circuit emulation and development programming unit e COP8 Evaluation and Programming Unit EPU Option List COP8780 low cost in circuit simulation and develop The mask programmable options are listed below The op ment programming unit tions are programmed at the same time as the ROM pattern Assembler COP8 DEV IBMA A DOS installable cross to provide the user with hardware flexibility to a variety of oscillation and packaging configuration OPTION 1 CKI INPUT 1 Crystal CKI IO CKO for crystal configuration 2 External CKI IO CKO available as G7 input 3 R C CKI IO CKO available as G7 input development Assembler Linker Librarian and Utility Software Development Tool Kit C Compiler COP8C A DOS installable cross develop ment Software Tool Kit OTP EPROM Programmer Support Covering needs from engineering prototype pilot production to full pro duction environments http www national com 24 Development Support continued IceMASTER IM IN CIRCUIT EMULATION Instruction by instruction memory register changes dis The iceMASTER IM COP8 400 is a full feature PC based played on source window WEE in sin
30. abled Tn 9d y INPUT LEVELS Reset CKI Logic High 0 8 Vcc V Logic Low 0 2 Vcc V All Other Inputs Logic High 0 7 Vcc V Logic Low 0 2 Vcc V Hi Z Input Leakage Voc 6 0V 2 2 pA Input Pullup Current Voc 6 0V Vin OV 40 250 pA L and G Port Hysteresis Note 5 0 35 Voc V Output Current Levels D Outputs Source Voc 4 5V 3 8V 0 4 mA Voc 2 5V 1 8V 0 2 mA Sink Voc 4 5V VoL 1 0V 10 mA Voc 2 5V 0 4V 2 mA L4 L7 Output Sink Voc 4 5V VoL 2 5V 15 mA All Others Source Weak Pull up Mode Voc 4 5V 3 2V 10 110 pA Voc 2 5V 1 8V 2 5 33 pA Source Push pull Mode Voc 4 5V 3 8V 0 4 mA Voc 2 5V 1 8V 0 2 mA Sink Push pull Mode Voc 4 5V VoL 0 4V 1 6 mA Voc 2 5V VoL 0 4V 0 7 mA TRI STATE Leakage 2 0 2 0 pA Allowable Sink Source Current Per Pin D Outputs 15 mA L4 L7 Sink 20 mA All Others 3 mA http www national com 2 DC Electrical Characteristics 40 c lt lt 85 unless otherwise specified Continued Parameter Conditions Min Typ Max Units Maximum Input Current Room Temperature 100 mA without Latchup Note 4 RAM Retention Voltage V 500 ns Rise and 20 v Fall Time Min Input Capacitance 7 pF Load Capacitance on D2 1000 pF Note 1 Rate of voltage change must be less than 10 V mS Note 2 Supply current is m
31. akeup continued INTERNAL DATA BUS STOP START WAKEUP NT CKT L7 WKEDG WKPND CHIP CLOCK TL DD 11208 21 FIGURE 16 Multi Input Wakeup Logic INTERRUPTS The device has a sophisticated interrupt structure to allow easy interface to the real world There are three possible interrupt sources as shown below A maskable interrupt on external GO input positive or nega tive edge sensitive under software control A maskable interrupt on timer carry or timer capture A non maskable software error interrupt on opcode zero INTERRUPT CONTROL The GIE global interrupt enable bit enables the interrupt function This is used in conjunction with ENI and ENTI to select one or both of the interrupt sources This bit is reset when interrupt is acknowledged ENI and ENTI bits select external and timer interrupts re spectively Thus the user can select either or both sources to interrupt the microcontroller when GIE is enabled IEDG selects the external interrupt edge 0 rising edge 1 falling edge The user can get an interrupt on both rising and falling edges by toggling the state of IEDG bit after each interrupt IPND and TPND bits signal which interrupt is pending After an interrupt is acknowledged the user can check these two bits to determine which interrupt is pending This permits the interrupts to be prioritized under software The pending flags have to be cleared by the user Setting the
32. counter with the desired number of counts 256 max and sets MC1 to start the counter The modulator autoreload register is loaded with n 1 to get n pulses CKI or tc pulses are routed to the modulator output L7 until the counter underflows Figure 13 Upon under flow the hardware resets MC1 and stops the counter The L7 pin goes low and stays low until the counter is restarted by the user program The user program has the responsibili ty to timeout the low time Unless the number of counts is changed the user program does not have to load the coun ter each time the counter is started The counter can simply be started by setting the MC1 bit Setting MC1 by software will load the counter with the value of the autoreload regis ter The software can reset MC1 to stop the counter MODE 2 PWM TIMER The counter can also be used as a PWM Timer In this mode an 8 bit register is used to serve as an autoreload register MODRL a 50 Duty Cycle When 1 is 1 and MC2 MC3 are 0 a 50 duty cycle free running signal is generated on the L7 output pin Figure 14 The L7 pin must be configured as an output pin In this mode the 8 bit counter is clocked by tC Setting the MC1 control bit by software loads the counter with the value of the autoreload register and starts the counter The counter underflow toggles the L7 output pin The 50 duty cycle signal will be continuously generated until MC1 is reset by the user program b Variab
33. dletstencopora of in circuit emulation tool developed and marketed by Meta Single base unit and debugger software reconfigurable to Link Corporation to support the whole COP8 family of prod support the entire COP8 family only the probe personali ucts National is a resale vendor for these products ty needs to change Debugger software is processor cus tomized and reconfigured from a master model file Processor specific symbolic display of registers and bit level assignments configured from master model file See Figure 18 for configuration The iceMASTER IM COP8 400 with its device specific COP8 Probe provides a rich feature set for developing test DAMES ing and maintaining product Halt Idle mode notification Real time in circuit emulation full 2 4V 5 5V operation On Line HELP customized to specific processor using range full DC 10 MHz clock Chip options are program master model file mable or jumper selectable Includes a copy of COP8 DEV IBMA assembler and link Direct connection to application board by package com er SDK patible socket or surface assembly IM Order Information Full 32 kbytes of loadable programming space that over Base Unit lays replaces the on chip ROM or EPROM On chip RAM and 1 blocks are used directly or recreated on IM COP8 400 1 iceMASTER Base Unit 110V the probe as necessary Power Supply Full 4k frame synchronous trace memory Address in IM COP8 400 2
34. dress locations are allocated for this port one for data register 00D3 one for configuration reg ister 0005 and one for the input pins 00D6 Since G6 and G7 are Hi Z input only pins any attempt by the user to configure them as outputs by writing a one to the configura tion register will be disregarded Reading the G6 and G7 configuration bits will return zeros Note that the device will be placed in the Halt mode by writing a 1 to the G7 data bit Six pins of Port G have alternate features GO INTR an external interrupt G3 TIO timer counter input output G4 SO MICROWIRE serial data output G5 SK MICROWIRE clock 170 G6 SI MICROWIRE serial data input G7 CKO crystal oscillator output selected by mask option or HALT restart input general purpose input if clock option is R C or external clock http www national com Pin Description Continued Pins G1 and G2 currently do not have any alternate func tions The selection of alternate Port G functions are done through registers PSW OOEF to enable external interrupt and CNTRL1 OOEE to select TIO and MICROWIRE operations PORT D is a four bit output port that is preset when RESET goes low One data memory address location is allocated for the data register OODC Note Care must be exercised with the D2 pin operation At RESET the external loads on this pin must ensure that the output voltages stay above 0 8 Vcc to prevent the chip from
35. easured after running 2000 cycles with a square wave CKI input CKO open inputs at rails and outputs open Note 3 The HALT mode will stop CKI from oscillating in the RC and crystal configurations HALT test conditions L and GO G5 ports configured as outputs and set high The D port set to zero All inputs tied to Vcc The comparator and the Brown Out circuits are disabled Note 4 Pins G6 and RESET are designed with a high voltage input network These pins allow input voltages greater than Vcc and the pins will have sink current to Vcc when biased at voltages greater than Vcc the pins do not have source current when biased at a voltage below Vcc The effective resistance to Vcc is 7500 typical These two pins will not latch up The voltage at the pins must be limited to less than 14V AC Electrical Characteristics 4 c lt lt 85 C unless otherwise specified Parameter Conditions Min Typ Max Units Instruction Cycle Time tc Crystal Resonator 4 5V Voc lt 6 0V 1 DC ps 2 5V lt Voc lt 4 5V 2 5 DC ps R C Oscillator 4 5V lt Voc lt 6 0V 3 DC ps 2 5V Vcc lt 4 5V 7 5 DC ps Vcc Rise Time when Using Brown Out Voc OV to 6V 50 ps Frequency at Brown Out Reset 4 MHz CKI Frequency For Modular Output 4 MHz CKI Clock Duty Cycle Note 5 fr Max 40 60 Rise Time Note 5 fr 10 MHz ext Clock 12 ns Fall Time Note 5 fr 10 MHz ext Clock 8 ns Inputs tsetup 4 5V Voc lt 6 0V 200 ns
36. ection to external supply supported Requires Vpp level adjust ment per the family programming specification correct level is provided on an on screen pop down display On line HELP customized to specific processor using master model file Includes a copy of COP8 DEV IBMA assembler and link er SDK DM Order Information Debug Module Unit COP8 DM 840CJ Cable Adapters DM COP8 20D 20 DIP DM COP8 28D 28 DIP Adapters for SO Package MHW SOIC16 16SO MHW SOIC20 20 SO MHW SOIC28 28 SO TL DD 11208 31 FIGURE 19 COP8 DM Environment http www national com 26 Development Support continued COP8 ASSEMBLER LINKER SOFTWARE DEVELOPMENT TOOL KIT National Semiconductor offers a relocatable COP8 macro cross assembler linker librarian and utility software devel opment tool kit Features are summarized as follows Basic and Feature Family instruction set by device type Nested macro capability Extensive set of assembler directives Supported on PC DOS platform Generates National standard COFF output files Integrated Linker and Librarian Integrated utilities to generate ROM code file outputs DUMPCOFF utility This product is integrated as a part of MetaLink tools as a development kit fully supported by the MetaLink debugger It may be ordered separately or it is bundled with the Meta Link products at no additional cost Order Information Assemble
37. er D2 Port L Input Pins Read Only D3 Reserved for Port L D4 Port G Data Register D5 Port G Configuration Register D6 Port G Input Pins Read Only D7 Port Input Pins Read Only D8toDB Reserved for Port C DC Port D Data Register DD to DF Reserved for Port D EOto EF On Chip Functions and Registers EOto E7 Reserved for Future Parts E8 Reserved E9 MICROWIRE Shift Register EA Timer Lower Byte EB Timer Upper Byte EC Timer1 Autoreload Register Lower Byte ED Timer1 Autoreload Register Upper Byte EE CNTRL1 Control Register EF PSW Register FO to FF On Chip RAM Mapped as Registers FC X Register FD SP Register FE B Register Reading other unused memory locations will return unde fined data Addressing Modes There are ten addressing modes six for operand address ing and four for transfer of control OPERAND ADDRESSING MODES REGISTER INDIRECT This is the normal addressing mode for the chip The op erand is the data memory addressed by the B or X pointer REGISTER INDIRECT WITH AUTO POST INCREMENT OR DECREMENT This addressing mode is used with the LD and X instruc tions The operand is the data memory addressed by the B or X pointer This is a register indirect mode that automati cally post increments or post decrements the B or X pointer after executing the instruction DIRECT The instruction contains an 8 bit address field that directly points to the data memory for the operand
38. ethods of exiting the HALT mode The first method is with a low to high transition on the CKO G7 pin This method precludes the use of the crystal clock configuration since CKO is a dedicated out put It may be used either with an RC clock configuration or an external clock configuration The second method of exit ing the HALT mode is with the multi Input Wakeup feature on the L port The third method of exiting the HALT mode is by pulling the RESET input low The fourth method is with the operating voltage going below Brown Out voltage if Brown Out is enabled by mask option If the two pin crystal resonator oscillator is being used and Multi Input Wakeup or Brown Out causes the device to exit the HALT mode the WAKEUP signal does not allow the chip to start running immediately since crystal oscillators have a delayed start up time to reach full amplitude and freugency stability The WATCHDOG timer consisting of an 8 bit prescaler followed by an 8 bit counter is used to gen erate a fixed delay of 256tc to ensure that the oscillator has indeed stabilized before allowing instruction execution In this case upon detecting a valid WAKEUP signal only the oscillator circuitry is enabled The WATCHDOG Counter and Prescaler are each loaded with a value of FF Hex The WATCHDOG prescaler is clocked with the tc instruction cy cle The tc clock is derived by dividing the oscillator clock down by a factor of 10 The Schmitt trigger following the
39. evice is reset as a result of brown out reset or external reset On power up the WATCHDOG is disabled The WATCHDOG is enabled by writing a 1 to WDREN bit resides in WDREG register Once enabled the user program should write periodically into the 8 bit counter before the counter underflows The 8 bit counter WDCNT is memory mapped at address OCE Hex The counter is loaded with n 1 to get n counts The counter underflow resets the device but does not disable the WATCHDOG Loading the 8 bit counter initializes the prescaler with FF Hex and starts the prescaler counter Prescaler and counter are stopped upon counter underflow Prescaler and counter are each loaded with FF Hex when the device goes into the HALT mode The prescaler is used for crystal resonator start up when the device exits the HALT mode through Multi Input Wakeup In this case the prescaler counter contents are changed MODE 2 TIMER In this mode the prescaler counter is used as a timer by keeping the WDREN WATCHDOG reset enable bit at 0 The counter underflow sets the WDUDF underflow bit and the underflow does not reset the device Loading the 8 bit counter load n 1 for n counts sets the WDTEN bit WATCHDOG Timer Enable to 1 loads the prescaler with FF and starts the timer The counter underflow stops the timer The WDTEN bit serves as a start bit for the WATCHDOG timer This bit is set when the 8 bit counter is loaded by the user program The load cou
40. g the MICROWIRE PLUS interface with an external shift clock is called the Slave mode of operation The CNTRL register is used to configure and control the MICROWIRE PLUS mode To use the MICROWIRE PLUS the MSEL bit in the CNTRL register is set to one The SK clock rate is selected by the two bits SLO and SL1 in the CNTRL register Table 11 details the different clock rates that may be selected CHIP SELECT LINES 8 BIT A D CON EEPROM VERTER DO DICLK DO DICLK TABLE III SL1 SLO SK Cycle Time 0 0 21 0 1 4 1 x 8tc where tc is the instruction cycle time MICROWIRE PLUS OPERATION Setting the BUSY bit in the PSW register causes the MI CROWIRE PLUS arrangement to start shifting the data It gets reset when eight data bits have been shifted The user may reset the BUSY bit by software to allow less than 8 bits to shift The device may enter the MICROWIRE PLUS mode either as a Master or as a Slave Figure 7 shows how two device microcontrollers and several peripherals may be interconnected using the MICROWIRE PLUS arrangement Master MICROWIRE PLUS Operation In the MICROWIRE PLUS Master mode of operation the shift clock SK is generated internally by the device The MICROWIRE PLUS Master always initiates all data ex changes Figure 7 The MSEL bit in the CNTRL register must be set to enable the SO and SK functions on the G Port The SO and SK pins must also be selected as outputs by
41. he RESET pin is pulled low while Brown Out occurs Brown Out circuit has detected Brown Out condition the external reset will not occur until the Brown Out condition is removed External reset has priority only if is greater than the Brown Out voltage P 0 w vec t R 5 RESET u P P L GND Y RC gt 5 x Power Supply Rise Time TL DD 11208 6 FIGURE 4 Recommended Reset Circuit WATCHDOG RESET With WATCHDOG enabled the WATCHDOG logic resets the device if the user program does not service the WATCH DOG timer within the selected service window The WATCHDOG reset does not disable the WATCHDOG Upon WATCHDOG reset the WATCHDOG Prescaler Counter are each initialized with FF Hex The following actions occur upon WATCHDOG reset that are different from external reset WDREN WATCHDOG Reset Enable bit UNCHANGED WDUDF WATCHDOG Underflow bit UNCHANGED Additional initialization actions that occur as a result of WATCHDOG reset are as follows RESET as long as Vcc is below the Brown Out Voltage The Device will resume execution if Vcc rises above the Brown Out Voltage If a two pin crystal resonator clock option is selected the Brown Out reset will trigger a 256tc delay This delay allows the oscillator to stabilize before the device ex its the reset state The delay is not used if the clock option is either R C or external clock The contents of data registers and RAM are unknown following a Brown Out reset The external
42. iceMASTER Base Unit 220V struction and 8 unspecified circuit connectable trace Power Supply lines Display can be HLL source e g C source assem bly or mixed iceMASTER Probe A full 64k hardware configurable break trace on trace MHW 840CJ20DWPC 20 DIP off control and pass count increment events MHW 840CJ28DWPC 28 DIP Tool set integrated interactive symbolic debugger sup ports both assembler COFF and C Compiler COD Adapters for SO Packages linked object formats MHW SOIC16 1650 Real time performance profiling analysis selectable MHW SOIC20 20 SO bucket definition Watch windows content updated automatically at each MHW SOIC28 28 SO execution break TL DD 11208 30 FIGURE 18 COP8 iceMASTER Environment 25 http www national com Development Support continued iceMASTER DEBUG MODULE DM The iceMASTER Debug Module is a PC based combination in circuit emulation tool and COP8 based OTP EPROM pro gramming tool developed and marketed by MetaLink Corpo ration to support the whole COP8 family of products Nation al is a resale vendor for these products See Figure 19 for configuration The iceMASTER Debug Module is a moderate cost devel opment tool It has the capability of in circuit emulation for a specific COP8 microcontroller and in addition serves as a programming tool for COP8 OTP and EPROM product fami lies Summary of features is as follows Real time in circui
43. ing flags Since the Reg WKPND is a pending register for the occurrence of selected wakeup conditions the device will not enter the HALT mode if any Wakeup bit is both enabled and pending Setting the G7 data bit under this condition will not allow the device to en ter the HALT mode Consequently the user has the respon sibility of clearing the pending flags before attempting to enter the HALT mode If a crystal oscillator is being used the Wakeup signal will not start the chip running immediately since crystal oscilla tors have a finite start up time The WATCHDOG timer pre scaler generates a fixed delay to ensure that the oscillator has indeed stabilized before allowing the device to execute instructions In this case upon detecting a valid Wakeup signal only the oscillator circuitry and the WATCHDOG timer are enabled The WATCHDOG timer prescaler is loaded with a value of FF Hex 256 counts and is clocked from the tc instruction cycle clock The tc clock is derived by dividing down the oscillator clock by a factor of 10 A Schmitt trigger following the CKI on chip inverter ensures that the WATCH DOG timer is clocked only when the oscillator has a suffi ciently large amplitude to meet the Schmitt trigger specs This Schmitt trigger is not part of the oscillator closed loop The startup timeout from the WATCHDOG timer enables the clock signals to be routed to the rest of the chip 17 http www national com Multi Input W
44. ld be as a result of WATCHDOG service WATCHDOG timer dedicated for WATCHDOG function or write to the counter WATCHDOG timer used as a general purpose counter The bit is cleared upon Brown Out reset WATCHDOG reset or external reset The bit is not memory mapped and is transparent to the user program TABLE VI WATCHDOG Control Status HALT WD Counter Parameter Mode Reset Reset Load Note 1 8 Bit Prescaler FF FF FF FF 8 Bit WD Counter FF FF FF User Value WDREN Bit Unchanged Unchanged 0 No Effect WDUDF Bit 0 Unchanged 0 0 WDTEN Signal Unchanged 0 0 1 Note 1 BOR is Brown Out Reset 13 http www national com Functional Description continued CONTROL STATUS BITS WDUDF WATCHDOG Timer Underflow Bit This bit resides in the CNTRL2 Register The bit is set when the WATCHDOG timer underflows The underflow resets the device if the WATCHDOG reset enable bit is set WDREN 1 Otherwise WDUDF can be used as the tim er underflow flag The bit is cleared upon Brown Out reset external reset load to the 8 bit counter or going into the HALT mode It is a read only bit WDREN WD Reset Enable WDREN bit resides in a separate register bit O of WDREG This bit enables the WATCHDOG timer to generate a reset The bit is cleared upon Brown Out reset or external reset The bit under software control can be written to only once once written to the hardware does not allow
45. le Duty Cycle When MC3 0 and MC2 1 a variable duty cycle PWM signal is generated on the L7 output pin The counter is clocked by tC In this mode the 16 bit timer T1 along with the 8 bit down counter are used to generate a variable duty cycle PWM signal The timer T1 underflow sets MC1 which starts the down counter and it also sets L7 high L7 should be configured as an output When the counter underflows the MC1 control bit is reset and the L7 output will go low until the next timer T1 underflow Therefore the width of the output pulse is controlled by the 8 bit counter and the pulse duration is controlled by the 16 bit timer T1 Figure 15 Tim er T1 must be configured in PWM Mode Toggle TIO Out CNTRL1 Bits 7 6 5 101 Table VII shows the different operation modes for the Mod ulator Timer TABLE VII Modulator Timer Modes Control Bits in Operation Mode CNTRL2 00CC L7 Function MC3 MC2 MC1 0 0 0 Normal I O 0 0 1 50 Duty Cycle Mode Clocked by tc 0 1 X Variable Duty Cycle Mode Clocked by tc Using Timer 1 Underflow 1 0 Modulator Mode Clocked by tc 1 1 Modulator Mode Clocked by CKI Note MC1 MC2 and MC3 control bits are cleared upon reset Internal Data Bus MODRL REGISTER CLK CKI OR tg 50 DUTY CYCLE TRIGGERED BY SOFTWARE FIGURE 13 Mode 1 Modulator Block Diagram Output Waveform CNTRL2 REGISTER SOFTWARE TRIGGERED BY S
46. ng Kong Fran ais Tel 49 0 180 532 93 58 Tel 852 2737 1600 http www national com Italiano Tel 49 0 180 534 16 80 Fax 852 2736 9960 National Semiconductor Japan Ltd Tel 81 043 299 2308 Fax 81 043 299 2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications
47. ode through G7 pin or Multi Input Wakeup G7 is the HALT restart pin but it can still be used as an input If the device is not halted G7 can be used as a gener al purpose input If the Brown Out Enable mask option is selected the Brown Out circuit remains active during the HALT mode causing additional current to be drawn Note To allow clock resynchronization it is necessary to program two NOP s immediately after the device comes out of the HALT mode The user must program two NOP s following the enter HALT mode set G7 data bit instruction http www national com 10 Functional Description continued MICROWIRE PLUS MICROWIRE PLUS is a serial synchronous bidirectional communications interface The MICROWIRE PLUS capabil ity enables the device to interface with any of National Semiconductors MICROWIRE peripherals i e A D con verters display drivers EEPROMS etc and with other mi crocontrollers which support the MICROWIRE PLUS inter face It consists of an 8 bit serial shift register SIO with serial data input SI serial data output SO and serial shift clock SK Figure 6 shows the block diagram of the MICRO WIRE PLUS interface TL DD 11208 8 FIGURE 6 MICROWIRE PLUS Block Diagram The shift clock can be selected from either an internal Source or an external source Operating the MICROWIRE PLUS interface with the internal clock source is called the Master mode of operation Operatin
48. on register Therefore each L I O bit can be individually configured under software control as shown below Port L Port L Port L Config Data Setup 0 0 Hi Z Input TRI STATE 1 Input with Weak Pull up 0 Push pull Zero Output 1 Push pull One Output 0 1 1 Three data memory address locations are allocated for this port one each for data register 0000 configuration regis ter 0001 the input pins 0002 Port L has the following alternate features LO MIWU or CMPOUT L1 MIWU or CMPIN L2 MIWU or CMPIN L3 MIWU L4 MIWU high sink current capability L5 MIWU high sink current capability L6 MIWU high sink current capability L7 MIWU or MODOUT high sink current capability The selection of alternate Port L functions is done through registers WKEN 00C9 to enable MIWU and CNTRL2 00CC to enable comparator and modulator All eight L pins have Schmitt Triggers on their inputs PORT G is an 8 bit port with 6 I O pins 00 05 and 2 input pins G6 G7 All eight G pins have Schmitt Triggers on the inputs There are two registers associated with the G port a data register and a configuration register Therefore each G port bit can be individually configured under software control as shown below Port G Port G Port G Config Data Setup 0 0 Hi Z Input TRI STATE 0 Input with Weak Pull up 1 0 Push pull Zero Output 1 1 Push pull One Output Three data memory ad
49. options TRI STATE output push pull output weak pull up input high impedance input High current outputs 8 pins Schmitt trigger inputs on Port G MICROWIRE PLUS serial I O Packages 16 SO with 12 1 0 pins 20 DIP SO with 16 I O pins 28 DIP SO with 24 I O pins CPU Instruction Set Feature W 1 us instruction cycle time W Three multi source vectored interrupts servicing External interrupt with selectable edge Timer interrupt Software interrupt W Versatile and easy to use instruction set m 8 bit Stack Pointer SP stack in RAM W Two 8 bit register indirect data memory pointers B X Fully Static CMOS m Low current drain typically lt 1 uA W Single supply operation 2 5V to 6 0V m Temperature range 40 C to 85 C Development Support W Emulation and OTP devices W Real time emulation and full program debug offered by MetaLink Development System Block Diagram CLOCK HALT RESET MICRO WIRE ILLEGAL COND DETECT CPU REGISTERS FIGURE 1 Block Diagram TRI STATE is a registered trademark of National Semiconductor Corporation COP8 Microcontrollers MICROWIRETM MICROWIRE PLUS and WATCHDOG are trademarks of National Semiconductor Corporation iceMASTER M is a trademark of MetaLink Corporation WATCHDOG 6 L D 8 BITS BITS 4 BITS 14 BITS COMPARATOR INPUT WAKEUP TL DD 11208 1 91996 National Semiconductor Cor
50. poration TL DD11208 RRD B30M106 Printed in U S A http www national com 1 UMOJg pue exea 1nduj niniy J9 043u0250J9IIN 118 8 84 2084 0284 0 COP820CJ COP822CJ COP823CJ Absolute Maximum Ratings If Military Aerospace specified devices are required Total Current out of GND pin sink 80 mA please contact the National Semiconductor Sales Storage Temperature Range 65 C to 150 C Office Distributors for availability and specifications Note Absolute maximum ratings indicate limits beyond Supply Voltage Vcc 7 0V which damage to the device may occur Voltage at any Pin 0 3V to Vcc 0 3V DC and AC electrical specifications are not ensured when Total Current into Vcc pin Source 80 mA operating the device at absolute maximum ratings DC Electrical Characteristics 40 c lt lt 85 C unless otherwise specified Parameter Conditions Min Typ Max Units Operating Voltage Brown Out Disabled 2 5 6 0 V Power Supply Ripple 1 Note 1 Peak to Peak 0 1 Vcc V Supply Current Note 2 10 MHz Voc 6V tc 1 us 6 0 mA CKI 4 MHz Voc 6V tc 2 5 us 3 5 mA CKI 4 MHz Voc 4 0V tc 2 5 us 2 0 mA CKI 1 MHz Voc 4 0V tc 10 us 1 5 mA HALT Current with Brown Out lt Disbled Note 3 Vcc 6V CKI 0 MHz 1 10 pA HALT Current with Brown Out Voc 6V CKI 0 MHz lt 50 110 Enabled Brown Out Trip Level Brown Out En
51. r Counter Auto Reload Mode Block Diagram TABLE V Timer Operating Modes CNTRL Timer Bits Operation Mode T Interrupt Counts 765 On 000 External Counter w Auto Load Reg Timer Underflow TIO Pos Edge 001 External Counter w Auto Load Reg Timer Underflow TIO Neg Edge 010 Not Allowed Not Allowed Not Allowed 011 Not Allowed Not Allowed Not Allowed 100 Timer w Auto Load Reg Timer Underflow tc 101 Timer w Auto Load Reg Toggle TIO Out Timer Underflow tc 110 Timer w Capture Register TIO Pos Edge tc 111 Timer w Capture Register TIO Neg Edge tc TIMER UNDERFLOW INTERRUPT EDGE SELECTOR LOGIC INTERNAL DATA BUS R1 16 BIT AUTO RELOAD REGISTER T1 16 BIT TIMER COUNTER FIGURE 9 Timer in External Event Counter Mode TL DD 11208 29 http www national com 12 Timer Counter continued MODE 3 TIMER WITH CAPTURE REGISTER Timer T1 can be used to precisely measure external fre quencies or events in this mode of operation The timer T1 counts down at the instruction cycle rate Upon the occur rence of a specified edge on the TIO pin the contents of the timer T1 are copied into the register R1 Bits in the control register CNTRL allow the trigger edge to be specified either as a positive edge or as a negative edge In this mode the user can elect to be interrupted on the specified trigger edge Figure 10 INTERNAL DATA BUS INTERRUPT RI 16 BIT CAPTURE REG TIO INPUT
52. r SDK COP8 DEV IBMA Assembler SDK on installable 3 5 PC DOS Floppy Disk Drive format Periodic upgrades and most recent version is available on National s BBS and Internet COP8 C COMPILER A C Compiler is developed and marketed by Byte Craft Lim ited The COP8C compiler is a fully integrated development tool specifically designed to support the compact embed ded configuration of the COP8 family of products Features are summarized as follows ANSI C with some restrictions and extensions that opti mize development for the COP8 embedded application BITS data type extension Register declaration 4 pragma with direct bit level definitions C language support for interrupt routines Expert system rule based code generation and optimiza tion Performs consistency checks against the architectural definitions of the target COP8 device Generates program memory code Supports linking of compiled object or COP8 assembled object formats Global optimization of linked code Symbolic debug load format fully source level supported by the MetaLink debugger Approved List Manufacturer North Europe Asia America BP 800 225 2102 49 8152 4183 852 234 16611 Microsystems 713 688 4600 49 8856 932616 852 2710 8121 Fax 713 688 0920 Data 1 0 800 426 1045 44 0734 440011 Call 206 881 6444 North America Fax 206 882 1043 HI LO 510
53. rder to avoid a pseudo Wakeup condition as a result of the edge change First the associated WKEN bit should be reset followed by the edge select change in WKEDG Next the associated WKPND bit should be cleared followed by the associated WKEN bit being re enabled An example may serve to clarify this procedure Suppose we wish to change the edge select from positive low going high to negative high going low for L port bit 5 where bit 5 has previously been enabled for an input The program would be as follows RBIT 5 WKEN SBIT 5 WKEDG RBIT 5 WKPND SBIT 5 WKEN If the L port bits have been used as outputs and then changed to inputs with Multi Input Wakeup a safety proce dure should also be followed to avoid inherited pseudo wakeup conditions After the selected L port bits have been changed from output to input but before the associated WKEN bits are enabled the associated edge select bits in WKEDG should be set or reset for the desired edge selects followed by the associated WKPND bits being cleared This same procedure should be used following RESET since the L port inputs are left floating as a result of RESET The occurrence of the selected trigger condition for Multi In put Wakeup is latched into a pending register called Reg WKPND The respective bits of the WKPND register will be set on the occurrence of the selected trigger edge on the corresponding Port L pin The user has the responsibility of clearing these pend
54. rom the engineering laboratory to full production AVAILABLE LITERATURE For more information please see the COP8 Basic Family User s Manual Literature Number 620895 COP8 Feature Family User s Manual Literature Number 620897 and Na tional s Family of 8 bit Microcontrollers COP8 Selection Guide Literature Number 630009 DIAL A HELPER SERVICE Dial A Helper is a service provided by the Microcontroller Applications group The Dial A Helper is an Electronic Infor mation System that may be accessed as a Bulletin Board System BBS via data modem as an FTP site on the Inter net via standard FTP client application or as an FTP site on the Internet using a standard Internet browser such as Net scape or Mosaic The Dial A Helper system provides access to an automated information storage and retrieval system The system capa bilities include a MESSAGE SECTION electronic mail when accessed as a BBS for communications to and from the Microcontroller Applications Group and a FILE SEC TION which consists of several file areas where valuable application software and utilities could be found DIAL A HELPER BBS via a Standard Modem Modem CANADA U S 800 NSC MICRO 800 672 6427 EUROPE 49 0 8141 351332 Baud 14 4k Set up Length 8 Bit Parity None Stop Bit 1 Operation 24 Hours 7 Days DIAL A HELPER via FTP ftp nscmicro nsc com user anonymous password username yourhost site domain DIAL A HELPER via a World
55. ruction is being used to reset the interrupt enable bit the interrupt enable bit will be reset but an interrupt may still occur This is because interrupt processing is started at the same time as the interrupt bit is being reset To avoid this scenario the user should always use a two three or four cycle instruction to reset interrupt enable bits DETECTION OF ILLEGAL CONDITIONS The device incorporates a hardware mechanism that allows it to detect illegal conditions which may occur from coding errors noise and brown out voltage drop situations Spe cifically it detects cases of executing out of undefined ROM area and unbalanced tack situations Reading an undefined ROM location returns 00 hexadeci mal as its contents The opcode for a software interrupt is also 00 Thus a program accessing undefined ROM will cause a software interrupt Reading an undefined RAM location returns an FF hexade cimal The subroutine stack on the device grows down for each subroutine call By initializing the stack pointer to the top of RAM the first unbalanced return instruction will cause the stack pointer to address undefined RAM As a result the program will attempt to execute from FFFF hexadecimal which is an undefined ROM location and will trigger a soft ware interrupt TO INTERRUPT LOGIC TL DD 11208 27 FIGURE 17 Interrupt Block Diagram http www national com Control Registers CNTRL1 REGISTER ADDRESS
56. s are cleared on RESET the comparator is disabled To save power the program should also disable the comparator before the device enters the HALT mode The user program must set up LO L1 and L2 ports correctly for comparator Inputs Output L1 and L2 need to be config ured as inputs and LO as output Multi Input Wake Up The Multi Input Wakeup feature is used to return wakeup the device from the HALT mode Figure 16 shows the Multi Input Wakeup logic This feature utilizes the L Port The user selects which par ticular L port bit or combination of L Port bits will cause the device to exit the HALT mode Three 8 bit memory mapped registers Reg WKEN Reg WKEDG and Reg WKPND are used in conjunction with the L port to implement the Multi Input Wakeup feature All three registers Reg WKEN Reg WKPND and Reg WKEDG are read write registers and are cleared at reset except WKPND WKPND is unknown on reset The user can select whether the trigger condition on the selected L Port pin is going to be either a positive edge low to high transition or a negative edge high to low transition This selection is made via the Reg WKEDG which is an 8 bit control register with a bit assigned to each L Port pin Setting the control bit will select the trigger condition to be a negative edge on that particular L Port pin Resetting the bit selects the trigger condition to be a positive edge Changing an edge select entails several steps in o
57. setting appropriate bits in the Port G configuration regis ter Table IV summarizes the bit settings required for Master mode of operation SLAVE MICROWIRE PLUS OPERATION In the MICROWIRE PLUS Slave mode of operation the SK clock is generated by an external source Setting the MSEL bit in the CNTRL register enables the SO and SK functions on the G Port The SK pin must be selected as an input and the SO pin selected as an output pin by appropriately setting up the Port G configuration register Table IV summarizes the settings required to enter the Slave mode of operation DIGITAL DERE cops PLL cel SLAVE TL DD 11208 23 FIGURE 7 MICROWIRE PLUS Application http www national com Functional Description continued The user must set the BUSY flag immediately upon entering the Slave mode This will ensure that all data bits sent by the Master will be shifted properly After eight clock pulses the BUSY flag will be cleared and the sequence may be repeated TABLE IV G4 G5 Confia Gonti G4 G5 G6 Operat nfig on iss rona Fun Fun Fun pereon Bit Bit 1 1 SO Int SK SI MICROWIRE Master 0 1 TRI STATE Int SK SI MICROWIRE Master 1 0 SO Ext SK SI MICROWIRE Slave 0 0 TRI STATE Ext SK SI MICROWIRE Slave Timer Counter The device has a powerful 16 bit timer with an associated 16 bit register enabling it to perform extensive timer func tions The timer T1 and
58. t emulation full operating voltage range operation full DC 10 MHz clock All processor I O pins can be cabled to an application development board with package compatible cable to Socket and surface mount assembly Full 32 kbytes of loadable programming space that over lays replaces the on chip ROM or EPROM On chip RAM and 1 blocks are used directly or recreated as necessary 100 frames of synchronous trace memory The display can be HLL source C source assembly or mixed The most recent history prior to a break is available in the trace memory Configured break points uses INTR instruction which is modestly intrusive Software only supported features are selectable Tool set integrated interactive symbolic debugger sup ports both assembler COFF and C Compiler COD SDK linked object formats Instruction by instruction memory register changes dis played when in single step operation Debugger software is processor customized and recon figured from a master model file Processor specific symbolic display of registers and bit level assignments configured from master model file Halt Idle mode notification Programming menu supports full product line of program mable and EPROM COP8 products Program data is taken directly from the overlay RAM Programming of 44 PLCC and 68 PLCC parts requires external programming adapters Includes wallmount power supply On board Vpp generator from 5V input or conn
59. the bit to be changed during program execution WDREN 1 WATCHDOG reset is enabled WDREN 0 WATCHDOG reset is disabled Table VI shows the impact of Brown Out Reset WATCH DOG Reset and External Reset on the Control Status bits INTERNAL DATA BUS HALT RESTART BROWN OUT WAKE UP WD COUNTER EXTERNAL RESET BROWN OUT RESET TART sTOP PRESET CLOCK PRESET WD COUNTER 8 BIT PRESCALER 256 TL DD 11208 15 FIGURE 12 WATCHDOG Timer Block Diagram http www national com 14 Modulator Timer The Modulator Timer contains an 8 bit counter and an 8 bit autoreload register MODRL address OCF Hex The Modu lator Timer has two modes of operation selected by the control bit MC3 The Modulator Timer Control bits MC1 MC2 and MC3 reside in CNTRL2 Register MODE 1 MODULATOR The Modulator is used to generate high frequency pulses on the modulator output pin L7 The L7 pin should be config ured as an output The number of pulses is determined by the 8 bit down counter Under software control the modula tor input clock can be either or tC The tC clock is de rived by dividing down the oscillator clock by a factor of 10 Three control bits MC1 MC2 and MC3 are used for the Modulator Timer output control When MC2 1 and MC3 1 CKI is used as the modulator input clock When MC2 0 and MC3 1 tC is used as the modulator input clock The user loads the
60. ur upon reset Port L TRI STATE Port G TRI STATE Port D HIGH PC CLEARED RAM Contents RANDOM with Power On Reset UNAFFECTED with external Reset power already applied B X SP Same as RAM PSW CNTRL1 CNTRL2 and WDREG Reg CLEARED Multi Input Wakeup Reg WKEDG WKEN CLEARED WKPND UNKNOWN Data and Configuration Registers for L amp G CLEARED WATCHDOG Timer Prescaler Counter each loaded with FF The device comes out of the HALT mode when the RESET pin is pulled low In this case the user has to ensure that the RESET signal is low long enough to allow the oscillator to restart An internal 256 tc delay is normally used in conjunc tion with the two pin crystal oscillator When the device comes out of the HALT mode through Multi Input Wakeup this delay allows the oscillator to stabilize The following additional actions occur after the device comes out of the HALT mode through the RESET pin If a two pin crystal resonator oscillator is being used RAM Contents UNCHANGED Timer T1 and A Contents UNKNOWN WATCHDOG Timer Prescaler Counter ALTERED http www national com Functional Description continued If the external or RC Clock option is being used RAM Contents UNCHANGED Timer T1 and A Contents UNCHANGED WATCHDOG Timer Prescaler Counter ALTERED The external RESET takes priority over the Brown Out Re set Note If t

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