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national semiconductor ADC121S101/ADC101S101/ADC081S101 1MSPS 12-/10-/8-Bit A/D Converters in SOT-23 LLP handbook

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2. 2005 National Semiconductor Corporation O O ADCOSIS10O1CIMF III National Semiconductor January 2005 ADC121S101 ADC101S101 ADC081S101 1MSPS 12 10 8 Bit A D Converters in SOT 23 amp LLP General Description The ADC121S101 ADC101S101 and ADC081S101 are low power monolithic CMOS 12 10 and 8 bit analog to digital converters that operate at 1 MSPS Each device is based on a successive approximation register architecture with inter nal track and hold The serial interface is compatible with several standards such as SPI QSPI MICROWIRE and many common DSP serial interfaces The ADC121S101 101S101 081S101 uses the supply volt age as a reference This enables the devices to operate with a full scale input range of O to Vpp The conversion rate is determined from the serial clock SCLK speed These con verters offer a shutdown mode which can be used to trade throughput for power consumption The ADC121S101 101S101 081S101 are operated with a single supply that can range from 2 7V to 5 25V Normal power consumption during continuous conversion using a 3V or 5V supply is 2 mW or 10 mW respectively The power down feature which is enabled by a chip select CS pin reduces the power consumption to under 5 uW using a 5V supply All three converters are available in a 6 lead SOT 23 package which provides an extremely small footprint for applications where space is a critical consideration The ADC081S101 is
3. DIGITAL INPUT CHARACTERISTICS Vin input High Vottage UIS ei RR MEE op P 08 V max Wozy O oa iv lin Digital Input Current Vin OV or Vop UA max Gino Jinput Capacitance Note 3 I UZ IA IEE Pp 4 5 mW max UW max uW max E www national com LOLSL8000V LOLSLOLOGV LOLSLCLOGV ADC121S101 ADC101S101 ADC081S101 ADC081 S101 Converter Electrical Characteristics Continued The following specifications apply for Vpp 2 7V to 5 25V fsck 20 MHZ fsampLe 1 MSPS unless otherwise noted Bold face limits apply for T 40 C to 85 C all other limits Ta 25 C unless otherwise noted DIGITAL OUTPUT CHARACTERISTICS lsource 200 pA V Output High Voltage Vpp 0 2 V min VoL Output Low Voltage Isink 200 pA o MA V max TRI STATE Output Capacitance C 2 F max eet Note 3 HO Ge Output Coding _ Straight Natural Binary AC ELECTRICAL CHARACTERISTICS 40 min tu _ TWackHold Acquistion O O T w frare Throughput Rate See Applications Section 1 EZ w awener UZ II s www national com 8 ADC121S101 ADC101S101 ADC081S101 Timing Specifications The following specifications apply for Vpp 2 7V to 5 25V Jese 20 MHz Boldface limits apply for T 40 C to 485 C all other limits Ta 25 C unless otherwise noted Note 11 tcONVERT ff 16 K ter u Minimum GS Pulse with TT zerg BITTORIO d o 20 ns min ns max ns max j TRI STATE Disabled Note 8 i Data Acc
4. Typical Performance Characteristics T 25 C Vbo 3V fsamece 1 MSPS besa 20 MHZ fin 100 kHz unless otherwise stated Continued ADC121S101 SINAD vs Input Frequency 600 kSPS ADC121S101 SINAD vs Input Frequency 1 MSPS 75 0 72 5 m ao B d D Q QO D pa zeza D D ee eee lt lt 70 0 E i TE Z Z 67 5 65 0 INPUT FREQUENCY kHz INPUT FREQUENCY kHz 20110253 20110254 ADC121S101 SNR vs fsck ADC121S101 SINAD vs fsck 75 0 72 5 SINAD dB NI oO SCLK FREQUENCY MHz SCLK FREQUENCY MHz 20110256 20110257 www national com 14 Typical Performance Characteristics T 25 C Vbo 3V fsample 1 MSPS besa 20 MHZ fin 100 kHz unless otherwise stated Continued ADC101S101 DNL 0 50 0 25 EO UO 3 0 00 QO 0 25 0 50 0 256 512 768 1024 OUTPUT CODE 20110270 ADC101S101 Spectral Response 100 kHz Input SINAD 61 9 SNR 61 9 THD 81 0 SFDR 84 4 ENOB 9 987 dBFS 0 100 200 300 400 500 FREQUENCY kHz 20110272 ADC101S101 SINAD vs Tegi SINAD dB SCLK FREQUENCY MHz 20110274 15 INL LSB 0 50 0 25 ADC101S101 INL 0 256 512 768 OUTPUT CODE ADC101S101 SNR vs fscix 5 10 15 GO SCLK FREQUENCY MHz I E A 1024 20110271 20110273 www national com LOLSL800QV LOLSLOLOQGV LOLSLCLOQV ADC121S101 ADC101S101 ADC081S101 Typical Performance Characteristics T 25 C Vbo 3V fsamece 1 MSPS besa 2
5. lt 85 C Distributors for availability and specifications 2 7V to 5 25V Vbp Supply Voltage Supply Voltage Vpp 0 3V to 6 5V Digital Input Pins Voltage Range Voltage on Any Analog Pinto GND 0 3V to Mon 0 3V Note 6 2 7V to 5 25V Voltage on Any Digital Pin to GND 0 3V to 6 5V Input Current at Any Pin Note 5 10 mA Package Thermal Resistance ESD Susceptibilit Human d d 3500V Oya Machine Model 200V Soldering Temperature Infrared 10 seconds 215 C Junction Temperature 150 C 65 C to 150 C Soldering process must comply with National Semiconductor s Reflow Temperature Profile specifications Refer to www national com packaging Note 4 ADC121S101 Converter Electrical Characteristics The following specifications apply for Vpp 2 7V to 5 25V foci 20 MHZ fsampLe 1 MSPS unless otherwise noted Bold face limits apply for Ta 40 C to 85 C all other limits Ta 25 C unless otherwise noted Storage Temperature STATIC CONVERTER CHARACTERISTICS V p 2 7V to 3 6V Resolution with No Missing Codes 40 C lt Ta lt 125 C Pf 1 Bits 40 C lt T lt 85 C INL Integral Non Linearity 1 LSB min Ta 125C A a 1 1 LSB max s e 0 5 1 LSB max 40 C lt Ta lt 85 C DNL Differential Non Linearity E 0 9 LSB min Ta 21257 BOK LSB max VoFF Offset Error 40 C lt T lt 125 C LSB max GE GZ 1250 LSB max SINAD Signal to Noise Plus Distortion Ratio 40 C lt T
6. lt 125 C Grieta dB min 40 C lt Ta lt 85 C 72 5 70 8 dB min Signal to Noise Ratio A 725 708 d Ta 125 C me Em Int dulation Distortion S d ntermodulation Distortion Secon f 103 5 kHz f 113 5 kHz JB Order Terms Int dulation Distortion Third a KA Ua fa 103 5 kHz f 113 5 kHz dB Order Terms 5V Suppl MHz FPBW 3 dB Full Power Bandwidth pply 13V Supply e vw POWER SUPPLY CHARACTERISTICS A 2 7 V min Vop Supply Voltage 40C lt Ta lt 125 C ege V max X 3 www national com LOLSL8000V LOLSLOLOGV LOLSLCLOGV ADC121S101 ADC101S101 ADC081S101 ADC121S101 Converter Electrical Characteristics Continued The following specifications apply for Vpp 2 7V to 5 25V fsck 20 MHZ fsampLe 1 MSPS unless otherwise noted Bold face limits apply for T 40 C to 85 C all other limits Ta 25 C unless otherwise noted Symbol POWER SUPPLY CHARACTERISTICS SCLK On or Off Normal Mode Static SCLK On or Off d ul fsampLe 1 MSPS fsampce 1 MSPS Voo 5v sK Tos oOo Mezu ZE oo Gi dk TO Normal Mode Voo 5V foameue 1MSPS 10 16 Vop 5V SCLK Off 2 5 Power Consumption Shutdown Mode PD 25 Voo 18V SCLK Of Pais lbp Normal Mode Operational l i Shutdown Mode Pp ANALOG INPUT CHARACTERISTICS DIGITAL INPUT CHARACTERISTICS Vin Jinput High Voltage IU fa BR ARO pb dS Heg IU lin Input Current Vin OV or Vpp DIGITAL O
7. also available in a 6 lead LLP package These products are designed for operation over the industrial temperature range of 40 C to 85 C with some parameters specified to 125 C for the ADC121S101 Connection Diagram Features m Variable power management m Packaged in 6 lead SOT 23 ADC081S101 also available in a 6 Lead LLP package Power supply used as reference m Single 2 7V to 5 25V supply operation m SPI QSPI MICROWIRE DSP compatible Key Specifications m Resolution with no Missing Codes 12 10 8 bits m Conversion Rate 1 MSPS m DNL ADC121S101 0 5 0 3 LSB typ m INL ADC121S101 0 4 LSB typ m Power Consumption 3V Supply 2 mW typ 5V Supply 10 mW typ Applications m Automotive Navigation m FA ATM Equipment Portable Systems Medical Instruments Mobile Communications Instrumentation and Control Systems GOO CS ADC1215101 GND 2 ADC101S101 5 SDATA ADC081S101 ViN SCLK MICROWIRE is a trademark of National Semiconductor Corporation TRI STATE is a trademark of National Semiconductor Corporation QSPI and SPI are trademarks of Motorola Inc DS201102 20110201 www national com d11 8 2 LOS U S4 H AUOI A V 4d 8 0L ZL SdSINL LOLSL809AV LOLSLOLOAY LOLSLZLOQAV ADC121S101 ADC101S101 ADC0O815S101 Ordering Information Temperature Description Top Mark Range 40 C to 6 Lead SOT 23 Package X01C 125 C 40 C to 85 C 6 Lead SOT 23 Package X
8. nects the sampling capacitor to ground maintaining the sampled voltage and switch SW2 unbalances the compara tor The control logic then instructs the charge redistribution DAC to add or subtract fixed amounts of charge from the sampling capacitor until the comparator is balanced When the comparator is balanced the digital word supplied to the DAC is the digital representation of the analog input voltage The device moves from hold mode to track mode on the 13th rising edge of SCLK CHARGE REDISTRIBUTION DAC CONTROL LOGIC 20110209 FIGURE 5 ADC121S101 101S101 081S101 in Track Mode SAMPLING CAPACITOR GND CHARGE REDISTRIBUTION CONTROL LOGIC 20110210 FIGURE 6 ADC121S101 101S101 081S101 in Hold Mode 2 0 USING THE ADC121S101 101S101 081S101 Serial interface timing diagrams for the ADC121S101 101S101 081S101 are shown in Figures 1 2 and 3 CS is chip select which initiates conversions on the ADC121S101 101S101 081S101 and frames the serial data transfers SCLK serial clock controls both the conversion process and the timing of serial data SDATA is the serial data out pin where a conversion result is found as a serial data stream Basic operation of the ADC121S101 101S101 081S101 be gins with CS going low which initiates a conversion process and data transfer Subsequent rising and falling edges of SCLK will be labelled with reference to the falling edge of CS for example the th
9. to 111 111 from the ideal Vpee 1 5 LSB for ADC121S101 and ADC101S101 Veer 1 LSB for ADC081S101 after adjusting for offset error INTEGRAL NON LINEARITY INL is a measure of the deviation of each individual code from a line drawn from negative full scale 2 LSB below the first code transition through positive full scale 12 LSB above the last code transition The deviation of any given code from this straight line is measured from the center of that code value INTERMODULATION DISTORTION IMD is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time It is defined as the ratio of the power in the either the two second order or all four third order intermodulation products to the sum of the power in both of the original frequencies IMD is usually expressed in dBFS MISSING CODES are those output codes that will never appear at the ADC outputs The ADC121S101 101S101 0815101 is guaranteed not to have any missing codes www national com OFFSET ERROR is the deviation of the first code transition 000 000 to 000 001 from the ideal i e GND 0 5 LSB for the ADC121S101 and ADC101S101 and GND 1 LSB for the ADC081S101 SIGNAL TO NOISE RATIO SNR is the ratio expressed in dB of the rms value of the input signal to the rms value of the sum of all other spectral components below one half the sampling frequency not including harmonics
10. until after the 10th falling edge of SCLK The ADC121S101 101S101 081S101 will be fully powered up after 16 SCLK cycles 11 0 POWER UP TIMING The ADC121S101 101S101 081S101 typically requires 1 us to power up either after first applying Vpp or after returning to normal mode from shutdown mode This corresponds to one dummy conversion for any SCLK frequency within the specifications in this document After this first dummy con version the ADC121S101 101S101 081S101 will perform conversions properly Note that the touer time must still be included between the first dummy conversion and the sec ond valid conversion www national com 20 12 0 STARTUP MODE When the Vpp supply is first applied the ADC121S101 101S101 081S101 may power up in either of the two modes normal or shutdown As such one dummy conversion should be performed after start up exactly as described in Section 11 0 The part may then be placed into either normal mode or the shutdown mode as described in Sections 8 0 and 9 0 13 0 POWER MANAGEMENT When the ADC121S101 101S101 081S101 is operated con tinuously in normal mode throughput up to 1 MSPS can be achieved The user may trade throughput for power con sumption by simply performing fewer conversions per unit time and putting the ADC121S101 101S101 081S101 into shutdown mode between conversions This method is not advantageous beyond 350 kSPS throughput A plot of maximum power consumption versus t
11. 0 MHZ fin 100 kHz unless otherwise stated Continued DNL LSB ADC081S101 Spectral Response 100 kHz Input dBFS SINAD dB ADC081S101 DNL OUTPUT CODE 20110260 SINAD 49 8 SNR 49 8 THD 70 9 SFDR 68 9 ENOB 7 977 EE PCP eer I O 100 200 300 400 500 FREQUENCY kHz 20110262 ADC081S101 SINAD vs esu tz 52 50 50 00 SCLK FREQUENCY MHz 20110264 www national com ADC081S101 INL 0 125 GO v 0 000 diekin JL 3 D IlI AA 0 125 0 250 OUTPUT CODE 20110261 ADC081S101 SNR vs fsc x 52 50 51 25 0 5 10 15 20 25 SCLK FREQUENCY MHz 20110263 Power Consumption vs Throughput 100 POWER DISSIPATION mW 0 1 0 50 100 150 200 250 300 350 THROUGHPUT KSPS 20110255 Applications Information 1 0 ADC121S101 101S101 081S101 OPERATION The ADC121S101 101S101 081S101 are successive approximation analog to digital converters designed around a Charge redistribution digital to analog converter Simplified schematics of the ADC121S101 101S101 081S101 in both track and hold operation are shown in Figures 4 and 5 respectively In Figure 4 the device is in track mode switch SW1 connects the sampling capacitor to the input and SW2 balances the comparator inputs The device is in this state until CS is brought low at which point the device moves to hold mode VIN SAMPLING CAPACITOR sw1 GND Vopi2 Figure 5 shows the device in hold mode switch SW1 con
12. 02C 40 C to 85 C 6 Lead SOT 23 Package X03C 40 C to 6 Lead SOT 23 Package Tape amp Reel X01C 125 C TI gre Evaluation Board 80828 Evaluation Board 8028 Evaluation Board Pin Descriptions Pin No Symbol Description ANALOG I O 3 ViN Analog input This signal can range from OV to Vpp DIGITAL I O Digital clock input The range of frequencies for this input is 10 kHz to 20 MHz with 4 SCLK guaranteed performance at 20 MHZ This clock directly controls the conversion and readout processes 5 Digital data output The output words are clocked out of this pin by the SCLK pin 6 Chip select A conversion process begins on the falling edge of CS POWER SUPPLY Positive supply pin These pins should be connected to a quiet 2 7V to 5 25V source and bypassed to GND with 0 1 uF and 1 uF monolithic capacitors located within 1 cm of the 1 V GO power pin The ADC121S101 101S101 081S101 uses this power supply as a reference so it should be thoroughly bypassed 2 GND The ground return for the supply Block Diagram SUCCESSIVE Vin APPROXIMATION ADC ADC121S101 SOIR ADC101S101 EE a ADC081S101 cs LOGIC 20110218 www national com 2 Absolute Maximum Ratings Notes 1 2 If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Operating Ratings note 2 Operating Temperature Range ADC121S101 ADC101S101 amp ADC081S101 E abea a Ee 40 C lt T
13. 953 R 004 MIN TYP 0 1 R 004 MIN TYP 0 1 040 oa i ZO 02 00607 015 TYP 0 15219 038 4 lt 0025 j E e 3 0 05 dre 025 TYP E Gian 0 8 T YP dna 10 21 c A BO 014 022 TYP 0 36 0 55 CONTROLLING DIMENSION IS INCH VALUES IN ARE MILLIMETERS MFO6A Rev B 6 Lead SOT 23 Order Number ADC121S101CIMF ADC121S101CIMFX ADC101S101CIMF ADC101S101CIMFX ADC081S101CIMF or ADC081S101CIMFX NS Package Number MFO6A DIMENSIONS ARE IN MILLIMETERS DIMENSIONS IN FOR REFERENCE ONLY dead 6X 0 6 ezez oe A E ry E 6X de GO 4K 0 65 i RECOMMENDED LAND PATTERN Sei 1 240 1 PIN 1 INDEX AREA 45 X0 25 e 0 2 MAA E E ta d d d dete d He BA 6X 0 40 1 6X 0 250 Gk 010 cle Be c ax DZ gg SDBOGA Rev A 6 Lead LLP Order Number ADC081S101CISD or ADC081S101CISDX NS Package Number SDBO6A www national com 22 Notes National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications For the most current product information visit us at www national com LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR COR
14. A TRI STATE 3 leading zero bits 10 data bits 2 trailing zeroes 20110203 FIGURE 3 ADC101S101 Serial Interface Timing Diagram 11 www national com LOLSL800QV LOLSLOLOQGV LOLSLCLOQV ADC121S101 ADC101S101 ADC081S101 Timing Diagrams continued Hold Track CS tCONVERT rr 1 a SCLK 15 ef AZAK ji tQuieT ty p A TRI STATE SDATA 3 leading zero bits 8 data bits 4 trailing zeroes 20110204 FIGURE 4 ADC081S101 Serial Interface Timing Diagram www national com 12 Typical Performance Characteristics T 25 C Voo 3V bearraz 1 MSPS Lesa 20 MHz fin 100 kHz unless otherwise stated ADC121S101 ADC121 101 DNL 1 0 DNL LSB o O 0 1024 2048 3072 4096 OUTPUT CODE 20110206 ADC121S101 Spectral Response 100 kHz Input SNR 73 3 dB SINAD 72 7 dB THD 82 0 dB SFDR 85 1 dB dBFS O 100 200 300 400 500 FREQUENCY kHz 20110207 ADC121S101 THD vs Input Frequency 600 kSPS KE d Pe 10 100 INPUT FREQUENCY kHz DRE Se THD dB 20110251 13 ADC121S101 INL 1 0 0 5 INL LSB o O 0 1024 2048 3072 4096 OUTPUT CODE 20110205 ADC121S101 THD vs Source Impedance THD dB 10 100 1k 10k SOURCE IMPEDANCE Q 20110250 ADC121S101 THD vs Input Frequency 1 MSPS bi f PND Baka SIE THD dB LL INPUT FREQUENCY kHz 20110252 www national com LOLSL800QV LOLSLOLOQGV LOLSLCLOQV ADC121S101 ADC101S101 ADC081S101
15. Electrical Characteristics The following specifications apply for Men 2 7V to 5 25V fsck 20 MHZ fsampLe 1 MSPS unless otherwise noted Bold face limits apply for T 40 C to 85 C all other limits Ta 25 C unless otherwise noted STATIC CONVERTER CHARACTERISTICS NL zeatzen ITZ ez LSB me ONC Differential Nana TT ez LSB ma Vo Geze ITa Tea USS re max max DYNAMIC CONVERTER CHARACTERISTICS SINAD _ Signal to Noise Plus Distortion Ratio fiy 100 kHz dB min SNR Signal to Noise Ratio fin 100 kHz 497 dB THD Total Harmonic Distortion fin 100 kHz d 65 dB max SFDR Spurious Free Dynamic Range fin 100 kHz 69 Se dB min Intermodulation Distortion Second gdko fa 103 5 kHz f 113 5 kHz dB IMD Order Terms Intermodulation Distortion Third See eee ean fa 103 5 kHz f 113 5 kHz dB Order Terms 5V Suppl 11 MHz E eee SV Supply AI POWER SUPPLY CHARACTERISTICS 2 7 V min Vop Supply Voltage 5 25 Wma 2 A I HA SCLK On or Off Vop 4 75V to 5 25V SOT 23 Normal Mode Operational Ge barez 1 MSPS Shutdown Mode Vop 5V SCLK On 0 E Voo 5V fsampe 1 Gan 2 ZZ mA mA max mA max AZ 26 IS ie P a maw BRUTO Power Consumption Normal Mode MSPS a mW max Operational Cas BE B ZL 1 JU 10 Vop 3V SAMPLE 1 MSPS 2 ower Consumption utaown WiO0de j Vop 3V SCLK Off ANALOG INPUT CHARACTERISTICS Vu Input Range 00 Ve
16. PORATION As used herein 1 Life support devices or systems are devices or systems 2 A critical component is any component of a life support which a are intended for surgical implant into the body or device or system whose failure to perform can be reasonably b support or sustain life and whose failure to perform when expected to cause the failure of the life Support device or properly used in accordance with instructions for use system or to affect its safety or effectiveness provided in the labeling can be reasonably expected to result in a significant injury to the user BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification CSP 9 111C2 and the Banned Substances and Materials of Interest Specification CSP 9 111S2 and contain no Banned Substances as defined in CSP 9 111S2 d11 8 2 LOS U S4 H AUOI A V UG 8 OL Zb SdSINL LOLSL800GV LOLSLOLOGV LOLSLZLOGV National Semiconductor National Semiconductor National Semiconductor National Semiconductor Americas Customer Europe Customer Support Center Asia Pacific Customer Japan Customer Support Center Support Center Fax 49 0 180 530 85 86 Support Center Fax 81 3 5639 7507 Email new feedback nsc com Email europe support nsc com Email ap support nsc com Email jon feedback nsc com Tel 1 800 272 9959 Deutsch Tel 49 0 69 9508 6208 Tel 81 3 5639 7560
17. UTPUT CHARACTERISTICS E a EO Cour TRISTATE Output Capacitance o oa Output Coding o AC ELECTRICAL CHARACTERISTICS leria Clock Frequency i Clock Frequency i Track Hold Acquisition Time Track Hold Acquisition Time Time RATE Throughput Rate See Serial Interface Section e Aperture Delay n dn a e Jai e www national com 4 Units V min V max UA max pF max Straight Natural Binary MHz max min max ns max MSPS max ns ps ADC101S101 Converter Electrical Characteristics The following specifications apply for Vpp 2 7V to 5 25V foci 20 MHZ fsampLe 1 MSPS unless otherwise noted Bold face limits apply for T 40 C to 85 C all other limits Ta 25 C unless otherwise noted STATIC CONVERTER CHARACTERISTICS INL 0 3 LSB max max max DYNAMIC CONVERTER CHARACTERISTICS THD JB max SFOR aB min Intermodulation Distortion Second ee fa 103 5 kHz f 113 5 kHz 78 dB IMD Order Terms Intermodulation Distortion Third aan fa 103 5 kHz f 113 5 kHz 78 dB Order Terms 5V Suppl 11 MHz BR EE EUSK EE TST POWER SUPPLY CHARACTERISTICS V Supply Voltage Se MU do EE 9 5 25 max lt Normal Mode Static SCLK On or Off Vbp 4 75V to 5 25V lop os oo 2 0 mA max fsampLe 1 MSPS Normal Mode Operational fsampLe 1 MSPS Vbp 5V SCLK Off 0 5 A max BO DD 05 pA max Voo 5V SCLK On o mam
18. al application of the ADC121S101 101S101 081S101 is shown in Figure 8 The combined analog and digital supplies are provided in this example by the National LP2950 low dropout voltage regulator available in a variety of fixed and adjustable output voltages The supply is by passed with a capacitor network located close to the device The three wire interface is also shown connected to a micro processor or DSP 5 0 ANALOG INPUTS An equivalent circuit for the ADC121S101 101S101 0815101 input channel is shown in Figure 9 The diodes D1 and D2 provide ESD protection for the analog inputs At no time should an analog input exceed Vpp 300 mV or GND 300 mV as these ESD diodes will begin conducting current into the substrate and affect ADC operation The capacitor C1 in Figure 9 typically has a value of 4 pF and is mainly due to pin capacitance The resistor R1 repre sents the on resistance of the multiplexer and track hold switch and is typically 100 ohms The capacitor C2 is the ADC121S101 101S101 081S101 sampling capacitor and is typically 26 pF The sampling nature of the analog input causes input current pulses that result in voltage spikes at the input The ADC121S101 101S101 081S101 will deliver best perfor mance when driven by a low impedance source to eliminate distortion caused by the charging of the sampling capaci tance In applications where dynamic performance is critical the input might need to be driven with a low ou
19. continued If CS goes low before the rising edge of SCLK an additional fourth zero bit may be captured by the next falling edge of SCLK 3 0 ADC121S101 101S101 081S101 TRANSFER FUNCTION The output format of the ADC121S101 101S101 081S101 is straight binary Code transitions occur midway between suc 111 111 111 110 111 000 ADC CODE 011 111 oy 0 5LSB 000 010 000 001 000 000 gt gt cessive integer LSB values The LSB widths for the ADC121S101 is Vbp 4096 for the ADC101S101 the LSB width is Vpp 1024 for the ADC081S101 the LSB width is Men 256 The ideal transfer characteristic for the ADC121S101 and ADC101S101 is shown in Figure 6 while the ideal transfer characteristic for the ADCO81S101 is shown in Figure 7 1 LSB Vpp 4096 ADC 1215101 1 LSB Vpp 1024 ADC 1018101 Vpp 1 5 LSB ANALOG INPUT 20110211 FIGURE 7 ADC121S101 101S101 Ideal Transfer Characteristic 111 111 111 110 111 000 ADC CODE ov 1LSB 011 111 eo 000 010 000 001 000 000 __ e 1 LSB Vpp 256 ADC0818101 Vpp 1 LSB ANALOG INPUT 20110212 FIGURE 8 ADC081S101 Ideal Transfer Characteristic www national com 18 Applications Information Continued 4 0 SAMPLE CIRCUIT LP2950 VDD DSP MICROCONTROLLER MICROPROCESSOR ADC121S101 ADC1015101 ADCO815101 GND 20110213 FIGURE 9 Sample Circuit A typic
20. ess Time after SCLK Falling Von 42 7t0436 Edgetnote 9 Voo 4475104525 ns max 0 4 x ns min egik 0 4 x ns min egik Vop 42 7 to 43 6 7 ns min E SCLK to Data Valid Hold Time 2D A l Vpp 4 75 to 5 25 E ns min ns max F SCLK Falling Edge to SDATA High ns min ii Impedance Note 10 ns max ns min i Power Up Time from Full i POWER UP Power Down H Note 1 Absolute maximum ratings are limiting values to be applied individually and beyond which the serviceability of the circuit may be impaired Functional operability under any of these conditions is not implied Exposure to maximum ratings for extended periods may affect device reliability Note 2 All voltages are measured with respect to GND OV unless otherwise specified Note 3 Specification limit guaranteed by design Note 4 See the section titled Surface Mount found in a current National Semiconductor Linear Databook for other methods of soldering suface mount devices Note 5 Except power supply pins Note 6 Independent of supply voltage Note 7 Minimum Quiet Time Required Between Bus Relinquish and Start of Next Conversion Note 8 Measured with the load circuit shown above and defined as the time taken by the output to cross 1 0V Note 9 Measured with the load circuit shown above and defined as the time taken by the output to cross 1 0V or 2 0V Note 10 tg is derived from the time taken by the outputs to change by 0 5V wi
21. hroughput is shown in Figure 12 below To calculate the power consump tion for a given throughput remember that each time the part exits shutdown mode and enters normal mode one dummy conversion is required Generally the user will put the part into normal mode execute one dummy conversion followed by one valid conversion and then put the part back into shutdown mode When this is done the fraction of time Applications Information Continued spent in normal mode may be calculated by multiplying the throughput in samples per second by 2 us the time taken to perform one dummy and one valid conversion The power consumption can then be found by multiplying the fraction of time spent in normal mode by the normal mode power consumption figure The power dissipated while the part is in shutdown mode is negligible 21 For example to calculate the power consumption at 300 KSPS with Vpp 5V begin by calculating the fraction of time spent in normal mode 300 000 samples second 2 us 0 6 or 60 The power consumption at 300 kSPS is then 60 of 17 5 mW the maximum power consumption at Vpp 5V or 10 5 mW www national com LOLSL8000V LOLSLOLOGVW LOLSLCLOGV ADC121S101 ADC101S101 ADC081S101 Physical DIMENSIONS inches millimeters unless otherwise noted 115 003 PKG SYMM 2 92 40 07 063 4 003 1 6 0 07 112 006 2 84 40 15 Ahhh SMG MMA ALAS TIA 6 aaa dt 4x 10375 RECOMMENDED LAND PATTERN 0
22. ird falling edge of SCLK shall refer to the third falling edge of SCLK after CS goes low At the fall of CS the SDATA pin comes out of TRI STATE and the converter moves from track mode to hold mode The input signal is sampled and held for conversion on the falling edge of CS The converter moves from hold mode to track 17 mode on the 13th rising edge of SCLK see Figure 1 2 or 3 The SDATA pin will be placed back into TRI STATE after the 16th falling edge of SCLK or at the rising edge of CS whichever occurs first After a conversion is completed the quiet time Laur Must be satisfied before bringing CS low again to begin another conversion Sixteen SCLK cycles are required to read a complete sample from the ADC121S101 101S101 081S101 The sample bits including any leading or trailing zeroes are clocked out on falling edges of SCLK and are intended to be clocked in by a receiver on subsequent falling edges of SCLK The ADC121S101 101S101 081S101 will produce three leading zero bits on SDATA followed by twelve ten or eight data bits most significant first After the data bits the ADC101S101 will clock out two trailing zeros and the ADC081S101 will clock out four trailing zeros The ADC121S101 will not clock out any trailing zeros the least significant data bit will be valid on the 16th falling edge of SCLK www national com LOLSL8000V LOLSLOLOGVW LOLSLCLOGV ADC121S101 ADC101S101 ADC081S101 Applications Information
23. or dc SIGNAL TO NOISE PLUS DISTORTION S N D or SINAD Is the ratio expressed in dB of the rms value of the input signal to the rms value of all of the other spectral compo nents below half the clock frequency including harmonics but excluding dc SPURIOUS FREE DYNAMIC RANGE SFDR is the differ ence expressed in dB between the rms values of the input signal and the peak spurious signal where a spurious signal is any signal present in the output spectrum that is not present at the input TOTAL HARMONIC DISTORTION THD is the ratio ex pressed in dBc of the rms total of the first five harmonic levels at the output to the level of the fundamental at the output THD is calculated as THD 20 Duo where Af is the RMS power of the fundamental output frequency and Af through Af are the RMS power in the first 5 harmonic frequencies TOTAL UNADJUSTED ERROR is the worst deviation found from the ideal transfer function As such it is a comprehen sive specification which includes full scale error linearity error and offset error Timing Diagrams TO OUTPUT PIN 20110208 FIGURE 1 Timing Test Circuit Hold Track CS ICONVERT t SCLK 7 14 A A A 15 16 ji buz tg SDATA E GO GO ZO JA ZZ ZA ZE ZN eu 3 leading zero bits 12 data bits 20110202 FIGURE 2 ADC121S101 Serial Interface Timing Diagram Hold Track CS ICONVERT 1 SCLK A 14 A A UNEA Al 15 16 ji tQuieT ty e e 7 e l
24. put for power consumption When the ADC121S101 101S101 081S101 is in shutdown mode all of the analog circuitry is turned off To enter shutdown mode a conversion must be interrupted by bringing CS back high anytime between the second and MI SCLK d SDATA tenth falling edges of SCLK as shown in Figure 10 Once CS has been brought high in this manner the device will enter shutdown mode the current conversion will be aborted and SDATA will enter TRI STATE If CS is brought high before the second falling edge of SCLK the device will not change mode this is to avoid accidentally changing mode as a result of noise on the CS line d TRI STATE 20110216 FIGURE 11 Entering Shutdown Mode 10 0 EXITING SHUTDOWN MODE THE PART BEGINS THE PART IS FULLY POWERED SDATA INVALID DATA VALID DATA 20110217 FIGURE 12 Entering Normal Mode To exit shutdown mode bring CS back low Upon bringing CS low the ADC121S101 101S101 081S101 will begin pow ering up Power up typically takes 1 us This microsecond of power up delay results in the first conversion result being unusable The second conversion performed after power up however is valid as shown in Figure 11 If CS is brought back high before the 10th falling edge of SCLK the device will return to shutdown mode This is done to avoid accidentally entering normal mode as a result of noise on the CS line To exit shutdown mode and remain in normal mode CS must be kept low
25. th the loading circuit shown above The measured number is then adjusted to remove the effects of charging or discharging the 25pF capacitor This means tg is the true bus relinquish time independent of the bus loading Note 11 All input signals are specified as t tt 5 ns 10 to 90 Vpp and timed from 1 6V 9 www national com LOLSL8000V LOLSLOLOGVW LOLSLCLOGV ADC121S101 ADC101S101 ADC081S101 Specification Definitions APERTURE DELAY is the time after the falling edge of CS to when the input signal is acquired or held for conversion APERTURE JITTER APERTURE UNCERTAINTY is the variation in aperture delay from sample to sample Aperture jitter manifests itself as noise in the output DIFFERENTIAL NON LINEARITY DNL is the measure of the maximum deviation from the ideal step size of 1 LSB DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period The speci fication here refers to the SCLK EFFECTIVE NUMBER OF BITS ENOB or EFFECTIVE BITS is another method of specifying Signal to Noise and Distortion or SINAD ENOB is defined as SINAD 1 76 6 02 and says that the converter is equivalent to a perfect ADC of this ENOB number of bits FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input GAIN ERROR is the deviation of the last code transition 111 110
26. tput impedance amplifier In addition when using the ADC121S101 101S101 081S101 to sample AC signals a band pass or low pass filter will reduce harmonics and noise and thus improve THD and SNR 19 VIN CONVERSION PHASE SWITCH OPEN TRACK PHASE SWITCH CLOSED 20110214 FIGURE 10 Equivalent Input Circuit 6 0 DIGITAL INPUTS AND OUTPUTS The ADC121S101 101S101 081S101 digital inputs SCLK and CS are not limited by the same absolute maximum ratings as the analog inputs The digital input pins are in stead limited to 6 5V with respect to GND regardless of Vbp the supply voltage This allows the ADC121S101 101S101 081S101 to be interfaced with a wide range of logic levels independent of the supply voltage Note that even though the digital inputs are tolerant of up to 6 5V above GND the digital outputs are only capable of driving Vpp out In addition the digital input pins are not prone to latch up SCLK and CS may be asserted before Vbp Without any risk 7 0 MODES OF OPERATION The ADC121S101 101S101 081S101 has two possible modes of operation normal mode and shutdown mode The ADC121S101 101S101 081S101 enters normal mode and a conversion process is begun when CS is pulled low The device will enter shutdown mode if CS is pulled high before the tenth falling edge of SCLK after CS is pulled low or will stay in normal mode if CS remains low Once in shutdown mode the device will stay there until CS is brought lo
27. w again By varying the ratio of time spent in the normal and shutdown modes a system may trade off throughput for power consumption 8 0 NORMAL MODE The best possible throughput is obtained by leaving the ADC121S101 101S101 081S101 in normal mode at all times so there are no power up delays To keep the device in normal mode continuously CS must be kept low until after the 10th falling edge of SCLK after the start of a conversion remember that a conversion is initiated by bringing CS low If CS is brought high after the 10th falling edge but before the 16th falling edge the device will remain in normal mode but the current conversion will be aborted and SDATA will return to TRI STATE truncating the output word Sixteen SCLK cycles are required to read all of a conversion word from the device After sixteen SCLK cycles have elapsed CS may be idled either high or low until the next conversion If CS is idled low it must be brought high again before the start of the next conversion which begins when CS is again brought low After sixteen SCLK cycles SDATA returns to TRI STATE Another conversion may be started after toyer has elapsed by bringing CS low again www national com LOLSL8000V LOLSLOLOGVW LOLSLCLOGV ADC121S101 ADC101S101 ADC081S101 Applications Information continued 9 0 SHUTDOWN MODE Shutdown mode is appropriate for applications that either do not sample continuously or are willing to trade through
28. y Power Consumption Normal Mode Vop 5V fsampLe 1 MSPS 10 16 mW max n Operational Vbo 3V fsampLe 1 MSPS SI 45 mW max j Men 5V SCLK Off 2 5 W max Power Consumption Shutdown Mode PD AA foo EZ Nen 3V SCLK Off 15 pW max ANALOG INPUT CHARACTERISTICS ViN Input Range I V UA max Cina Input Capacitance Note 3 DIGITAL INPUT CHARACTERISTICS Vin Input High Voltage Vil Input Low Voltage DD I Vo t8V0 ru lin Input Current Vin OV or Vop 10 nA nA Ca CE ee ee ee ee ee F DIGITAL OUTPUT CHARACTERISTICS lsource 200 pA V High Vol OH BEER aaga Vop 2 7V to 5 25V 5 www national com LOLSL8000V LOLSLOLOGVW LOLSLCLOGV ADC121S101 ADC101S101 ADC081S101 ADC101S101 Converter Electrical Characteristics Continued The following specifications apply for Vpp 2 7V to 5 25V fsck 20 MHZ fsampLe 1 MSPS unless otherwise noted Bold face limits apply for T 40 C to 85 C all other limits Ty 25 C unless otherwise noted DIGITAL OUTPUT CHARACTERISTICS Output Low Voltage Isink 200 pA Oaa V max TRI TRI STATE Leakage Current TRI STATE Leakage Current Current SEI UA max ba SK Output Capacitance C E max I aei B Straight Natural Binary AC ELECTRICAL CHARACTERISTICS lz 60 Yo mi DC SCLK Duty Cycle min max tty MSPS RATE Throughput Rate See Serial Interface Section a mae tap www national com 6 ADC081S101 Converter

national semiconductor ADC121S101/ADC101S101/ADC081S101 1MSPS 12-/10-/8-Bit A/D Converters in SOT-23 LLP handbook

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