National Semiconductor ADC08161 500 ns A/D Converter with S/H Function 2.5V Bandgap Reference handbook
Contents
1. 6 ADC08161 2 5V Bandgap Reference General Description Using a patented multi step A D conversion technique the 8 bit ADC08161 CMOS A D converter offers 500 ns conver sion time internal sample and hold S H a 2 5V bandgap reference and dissipates only 100 mW of power The ADC08161 performs an 8 bit conversion with a 2 bit voltage estimator that generates the 2 MSBs and two low resolution 3 bit flashes that generate the 6 LBSs Input signals are tracked and held by the input sampling cir cuitry eliminating the need for an external sample and hold The ADCO08161 can perform accurate conversions of full scale input signals at frequencies from DC to typically more than 300 kHz full power bandwidth without the need of an external sample and hold S H For ease of interface to microprocessors this part has been designed to appear as a memory location or I O port without the need for external interfacing logic National Semiconductor 500 ns A D Converter with S H Function and June 1999 Key Specifications m Resolution 8 Bits m Conversion time tcony 560 ns max WR RD Mode m Full power bandwidth 300 kHz typ m Throughput rate 1 5 MHz min m Power dissipation 100 mW max Total unadjusted error 1 LSB 1 LSB max Features m No external clock required m Analog input voltage range from GND to V m 2 5V bandgap reference Applications Mobile telecommunications Hard disk drives2. Access Time Delay from C 10 pF 45 ns Falling Edge of RD C 100 pF 50 110 ns max to Output Valid Mode Pin to V tap lt tint Figure 2 tacce Access Time Delay from C 10 pF 25 ns Falling Edge of RD C 100 pF 30 55 ns max to Output Valid tap gt tium Figures 3 5 tm toy TRI STATE Control C 10 pF Delay from Rising Edge Figures 1 2 3 4 5 30 60 ns max of RD to HI Z State NTL Delay from Rising Edge of Mode Pin V 50 pF 520 690 ns max WR to Falling Edge of INT Figures 3 4 NTH Delay from Rising Edge of 50 pF 50 95 ns max RD to Rising Edge of INT Figures 1 2 3 5 NTH Delay from Rising Edge of 50 pF Figure 4 45 95 ns max WR to Rising Edge of INT taby Delay from CS to RDY Mode Pin OV 50 pF 25 45 ns max 3 Figure 1 lip Delay from INT 3 100 pF 0 15 ns max to Output Valid Figure 4 ini Delay from RD to INT Mode Pin V tap lt tir 60 115 ns max Figure 2 tn Time between End of RD Figures 1 2 3 4 5 50 50 ns min and Start of New Conversion 1555 CS Setup Time Figures 1 2 3 4 5 0 0 CS Hold Time Figures 1 2 3 4 5 0 0 ns max DC Electrical Characteristics The following specifications apply for V 5V unless otherwise specified Boldface limits apply for T4 Ty Tmn to all other limits T4 Ty 2
3. Instrumentation High speed data acquisition systems Block Diagram VREF VREF 3 Bit Flash A D Converter 2 5V Bandgap Reference VREFOUT TRI STATE is a registered trademark of National Semiconductor Corporation OFL DB7 MSB DB6 DB5 DB4 DB3 DB2 DBI DBO LSB Output Latch and Tri State Buffers DS011149 1 1999 National Semiconductor Corporation DS011149 www national com debpueg Ac z pue H S Q V SU 006 L919020V Connection Diagram Wide Body Small Outline Package 1 20 v 2 9 7 Vrerout 3 4 17 087 5 6 6 15 085 7 4 04 8 9 2F7 Vrer 10 DS011149 14 See NS Package Number M20B Ordering Information Industrial 40 C lt lt 85 Package ADC08161CIWM M20B Pin Description Vin DBO DB7 WR RDY MODE This is the analog input The input range is GND 50 mV lt Vinpyt 50 mV TRI STATE data outputs bit 0 LSB through bit 7 MSB WR RD Mode Logic high applied to MODE pin WR With CS low the conversion is started on the rising edge of WR The digi tal result will be strobed into the output latch at the end of conversion Figures 2 3 4 RD Mode Logic low applied to MODE pin RDY This is an open drain output no in ternal pull up device RDY will go low af ter the falling e
4. REFERENCE VOLTAGE V DS011149 25 www national com Supply Current vs Temperature 16 T V z5 5V E z a E 5 5 gt 10 2 a amp 5 6 100 50 0 50 100 150 TEMPERATURE C DS011149 26 Output Current vs Temperature 40 30 sink 20 20 OUTPUT CURRENT mA o 30 1 SOURCE 40 100 50 0 50 100 150 TEMPERATURE C DS011149 29 Typical Performance Characteristics Continued Reference Output Voltage vs Temperature 2 515 v 5V Veerour Pin 2 510 REFOUT 2 505 2 500 2 495 2 490 2 485 100 50 0 50 100 150 TEMPERATURE C DS011149 27 Logic Threshold vs Temperature 1 5 1 4 kn 5 0 2 5 8 12 fees 1 1 1 0 100 0 50 100 150 TEMPERATURE C DS011149 28 www national com 10 Application Information Vrer PE 4 gt lt oll 6 22 15 16 p oy 1 1 ac log lt 2 8 a 11 16 4 amp a a 1 8 o amp 9 16 a S 8 256 lt 7 16 a 7 256 6 256 8 a 5 256 3 3 16 4 256 I 1 256 4 VREF DAC OUTPUT H H ape O DB7 O DB5 HA m E TRI STATE o pag 2 OUTPUT lt lt BUFFER 0 E us DB1 H Me
5. The following specifications apply for V 5V unless otherwise specified Boldface limits apply for to Tmax all other limits TA Ty 25 C Symbol Parameter Conditions Typical Limits Units Note 7 Note 8 Limit VaErFouT Internal Reference Output Voltage 2 5 2 0 V max Internal Reference Temperature 40 ppm C Coefficient AVner Al Internal Reference Load Sourcing 0 lt lt 10 mA 0 01 0 1 mA Regulation Line Regulation 4 75 V lt 5 25V 0 5 6 0 mV max Isc Short Circuit Current Vrev OV 35 mA max AVree At Long Term Stability 200 ppm kHr Start Up Time V OV5V 220 UF 40 ms Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not apply when operating the device beyond its specified operating ratings Operating Ratings indicate conditions for which the device is functional but do not guarantee performance limits For guaranteed specifications and test conditions see the Electrical Characteristics The guaranteed specifications apply only for the test conditions listed Some per formance characteristics may degrade when the device is not operated under the listed test conditions www national com Bandgap Reference Electrical Characteristics continued Note 2 All voltages are measured with respect to the GND pin unless otherwise specified Note
6. 8 256 and 2 8 of and con nects them to the eight flash comparators The first flash conversion is now performed producing the five MSBs of data The remaining three LSBs are generated next using the same eight comparators that were used for the first flash conversion As determined by the results of the MSB flash a voltage from the MSB Ladder equivalent to the magnitude of the five MSBs is subtracted from the analog input voltage as the upper switch is moved from position one to position two The resulting remainder voltage is applied to the eight flash comparators and with the lower switch in position two com pared with the eight tap points from the LSB Ladder By using the same eight comparators for both flash conver sions the number of comparators needed by the multi step converter is significantly reduced when compared to stan dard half flash techniques Voltage Estimator errors as large as 1 16 of Vage 16 LSBs will be corrected since the flash comparators are connected to ladder voltages that extend beyond the range specified by the Voltage Estimator For example if 7 16 Vaer lt Vin lt 9 16 Vref the Voltage Estimator s comparators tied to the tap points below 9 16 Ver will output 1 5 000111 This is decoded by the estimator decoder to 10 The eight flash comparators will be placed at the MSB Ladder tap points be tween 36 Vp_er and 56 Vper The overlap of 1 16 Veer on each side of the Voltage Estimator s span
7. HA DS011149 17 FIGURE 6 Block Diagram of the ADC08161 Multi Step Flash Architecture 1 0 FUNCTIONAL DESCRIPTION The ADC08161 performs an 8 bit analog to digital conver sion using a multi step flash technique The first flash gener ates the five most significant bits MSBs and the second flash generates the three least significant bits LSBs Figure 6 shows the major functional blocks of the ADC08161 multi step flash converter It consists of an over encoded 212 58 Voltage Estimator an internal DAC with two different voltage spans a 3 bit half flash converter and a comparator multiplexer The resistor string near the center of the block diagram in Figure 6 forms the internal main DAC Each of the eight re sistors at the bottom of the string is equal to 1 256 of the total string resistance These resistors form the LSB Ladder and have a voltage drop of 1 256 of the total reference voltage Vngr Vrer_ across them The remaining resistors make up the MSB Ladder They are made up of eight groups of four resistors connected in series Each MSB Ladder section has 14 of the total reference voltage across it Within a given MSB Ladder section each of the MSB resistors has 8 256 or 142 of the total reference voltage across it Tap points are found between all of the resistors in both the MSB and LSB Ladders Through the Comparator Multiplexer these tap points can be connected in groups of eight to the eight com parators shown
8. Total unadjusted error includes offset full scale and linearity errors Note 10 Two on chip diodes are tied to each analog input and are reversed biased during normal operation One is connected to V and the other is connected to GND They will become forward biased and conduct when an analog input voltage is equal to or greater than one diode drop above V or below GND Therefore caution should be exercised when testing with V 4 5V Analog inputs with magnitudes equal to 5V can cause an input diode to conduct especially at elevated tem peratures This can create conversion errors for analog signals near full scale The specification allows 50 mV forward bias on either diode e g the output code will be correct as long as the analog input signal does not exceed the supply voltage by more than 50 mV Exceeding this range on an unselected channel will corrupt the reading of a selected channel An absolute analog input signal voltage range of OV lt lt 5V can be achieved by ensuring that the minimum supply voltage ap plied to V is 4 950V over temperature variations initial tolerance and loading Note 11 Off channel leakage current is measured on the on channel selection www national com 6 TRI STATE Test Circuit and Waveforms DATA ADC08161 OUTPUT SKA 08011492 DATA OUTPUT DS011149 3 cs 5 RD WITH EXTERNAL PULL UP RDY INT DBO DB7 tia CL 10 pF V 0H 902 DATA O
9. at the right of Figure 6 This function pro vides the necessary reference voltages to the comparators during each flash conversion The six comparators seven resistor string estimator DAC and Estimator Decoder at the left of Figure 6 form the Volt age Estimator The estimator DAC connected between Vrer and _ generates the reference voltages for the six Voltage Estimator comparators These comparators per form a very low resolution A D conversion to obtain an esti mate of the input voltage This estimate is then used to con trol the Comparator Multiplexer connecting the appropriate MSB Ladder section to the eight flash comparators Only 14 comparators six in the Voltage Estimator and eight in the flash converter are needed to achieve the full eight bit reso lution instead of 32 comparators that would be needed by traditional half flash methods A conversion begins with the Voltage Estimator comparing the analog input signal against the six tap voltages on the es timator DAC The estimator decoder then selects one of the groups of tap points along the MSB Ladder These eight tap points are then connected to the eight flash comparators For example if the analog input signal applied to Vi is be www national com Application Information Continued tween 0 and 3 16 of Veer Veer Vrer_ the esti mator decoder instructs the comparator multiplexer to select the eight tap points between
10. must be capable of sinking 5 mA DS011149 19 DS011149 21 Note Bypass capacitors consist of a 0 1 ceramic in parallel with a 10 uF bead tantalum unless otherwise specified FIGURE 8 Analog Input Options MT O ADC08161 DB1 DS011149 22 FIGURE 9 Typical Connection Note the multiple bypass capacitors on the reference and power supply pins Vrer_ should be bypassed to analog ground using multiple capacitors if it is not grounded See Section 7 0 LAYOUT GROUNDS and BYPASSING Vi is shown with an optional input protection network www national com 14 Physical Dimensions inches millimeters unless otherwise noted 0 496 0 512 12 598 13 005 20 19 18 17 16 15 14 13 12 11 i 0 394 0 419 10 008 10 643 307 LEADNO 1 1 IDENT Y Pd 2 3 4 8 8 7 8 9 10 0 010 0 254 0 291 0 299 7 391 7 595 0010 0028 0 093 0 104 0 254 0 737 9 2 362 2 642 0 004 0 012 8 MAX TYP 0 004 0 012 ALL LEADS 0 102 0 305 Hy tr trj E iud SEATING ET 5 4 PLANE 0 004 0 014 0 009 0 013 uds peleke 0102 0 016 0 050 0356 gt _ 0 050 gt 0 014 0 020 0 229 0 330 ALL LEAD TIPS 0406 1270 1270 0 356 0 508 ALL LEADS TYP ALL LEADS TYP 0 008 0 203 M20B iREV F Wide Body Small Outline Order Number ADC08
11. 161CIWM NS Package Number M20B LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life www national com Systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user N National Semiconductor Europe National Semiconductor Corporation Americas Tel 1 800 272 9959 Fax 1 800 737 7018 Email support nsc com Fax 49 0 1 80 530 85 86 Email europe support nsc com Deutsch Tel 49 0 1 80 530 85 85 English Tel 49 0 1 80 532 78 32 Fran ais Tel 49 0 1 80 532 93 58 Italiano Tel 49 0 1 80 534 16 80 support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Japan Ltd Tel 81 3 5639 7560 Fax 81 3 5639 7507 National Semiconductor Asia Pacific Customer Response Group Tel 65 2544466 Fax 65 2504466 Email sea support nsc com Nati
12. 3 When the input voltage at any pin exceeds the power supply voltage Viy lt GND or Viy gt V the absolute value of the current at that pin should be limited to 5 mA or less The 20 mA package input current specification limits the number of pins that can exceed the power supply boundaries with a 5 mA current limit to four Note 4 The power dissipation of this device under normal operation should never exceed 875 mW Quiescent Power Dissipation TTL Loads on the digital outputs Caution should be taken not to exceed absolute maximum power rating when the device is operating in a severe fault condition e g when any input or output ex ceeds the power supply The maximum power dissipation must be derated at elevated temperatures and is dictated by T juAx maximum junction temperature 0A package junction to ambient thermal resistance and TA ambient temperature The maximum allowable power dissipation at any temperature is PDmax Tymax T4 0jA or the number given in the Absolute Maximum Ratings whichever is lower For this device Tjyjax 105 C and 85 C W Note 5 See AN 450 Surface Mounting Methods and Their Effect on Product Reliability for other methods of soldering surface mount devices Note 6 Human body model 100 pF discharged through a 1 5 kQ resistor Note 7 Typicals are at 25 C and represent most likely parametric norm Note 8 Limits are guaranteed to National s AOQL Average Output Quality Level Note 9
13. 5 C ia Typical Limit Units Symbol Parameter Conditions Note 7 Note 8 Limit Vin Logic 1 Input Voltage V 255V CS WR RD 0 A1 A2 Pins 2 0 V min Mode Pin 3 5 www national com 4 DC Electrical Characteristics continued The following specifications apply for V 5V unless otherwise specified Boldface limits apply for T4 Ty Tm to Tmax all other limits Ty 25 C Symbol Parameter Conditions Nin Nota 5j Limit Vu Logic 0 Input Voltage Vt 4 5V CS WR RD 0 A1 A2 Pins 0 8 V max Mode Pin 1 5 li Logic 1 Input Current Va 5V CS RD AQ A A2 Pins 0 005 1 WR Pin 0 1 3 pA max Mode Pin 50 200 lu Logic 0 Input Current V 20V CS RD WR A1 A2 Mode Pins 0 005 2 Logic 1 Output Voltage Vt 4 75V lour 360 pA 2 4 min DBO DB7 OFL INT lour 10 pA 4 5 V min DBO DB7 OFL INT VoL Logic 0 Output Voltage Vt 4 75V lour 1 6 mA 0 4 V max DBO DB7 OFL INT RDY lo TRI STATE Output Current 5 0V 0 1 3 pA max DB0 DB7 RDY Vour OV 0 1 3 max DB0 DB7 RDY lsounce Output Source Current Vout OV 26 6 mA min DBO DB7 OFL INT Isink Output Sink Current Vout 5V 24 7 mA min DBO DB7 OFL INT RDY lc Supply Current CS WR RD 0 11 5 20 mA max Cour Logic Output Capacitance 5 pF Cin Logic Input Capacitance 5 pF Bandgap Reference Electrical Characteristics
14. ASSING In order to ensure fast accurate conversions from the ADC08161 it is necessary to use appropriate circuit board layout techniques Ideally the analog to digital converter s ground reference should be low impedance and free of noise from other parts of the system Digital circuits can produce a great deal of noise on their ground returns and therefore should have their own separate ground lines Best perfor mance is obtained using separate ground planes should be provided for the digital and analog parts of the system The analog inputs should be isolated from noisy signal traces to avoid having spurious signals couple to the input Any external component e g an input filter capacitor con nected across the inputs should be returned to a very clean ground point Incorrectly grounding the ADC08161 may re sult in reduced conversion accuracy The V supply pin Vage and Vper if not grounded should be bypassed with a parallel combination of a 0 1 F ceramic capacitor and a 10 F tantalum capacitor placed as close as possible to the pins using short circuit board traces See Figures 8 9 DS011149 18 FIGURE 7 ADC08161 Equivalent Input Circuit Model www national com Application Information continued Internal Reference 2 5V Full Scale Power Supply as Reference Input Not Referred to GND Standard Application VREFOUT VREF VREF DS011149 20 Signal source driving Viy
15. Current Note 3 Converter Characteristics The following specifications apply for RD Mode V 5V Vrer 5V and Veger GND unless otherwise specified Bold face limits apply for TA Ty Tm to Tmax all other limits Ta T 25 C 0 3V to Vt 0 3V 0 3V to V 0 3V Power Dissipation Note 4 Lead Temperature Note 5 Vapor Phase 60 sec Infrared 15 sec 6 Storage Temperature 5 mA ESD Susceptibility Note 6 20 mA Temperature Range ADC08161CIWM Supply Voltage v 65 C to 150 C Operating Ratings notes 1 2 Tmn lt Ta lt Tmax 40 C lt TA lt 85 C 875 mW 215 C 220 750V 4 5V to 5 5V Symbol Parameter Conditions Typical Limits Units Note 7 Note 8 Limit INL Integral Non Linearity 5V 1 LSB max TUE Total Unadjusted Error Note 9 Vrer 5V t1 LSB max INL Integral Non Linearity Vrer 2 5V t1 LSB max TUE Total Unadjusted Error Vrer 2 5V 1 LSB max Missing Codes Vrer 5V 0 Bits max Veer 2 5V 0 Bits max Reference Input Resistance 700 500 Q min 700 1250 Q max VREF Positive Reference Input Voltage Vner V min vt V max VREF Negative Reference GND V min Input Voltage VREF V max Vin Analog Note 10 GND 0 1 V min Input Voltage V 0 1 On Channel Input Current On Channel Input 5V Off Channel Input OV 0 4 20 max Note 11 On Chan
16. UTPUTS GND DS011149 4 t 10 ns ton CL 10 pF t r 90 RD 50 GND 10 toy V DATA OUTPUTS T 107 OL 05011149 5 tr 10 ns 05011149 6 FIGURE 1 RD Mode Mode Pin is Low www national com DBO DB7 DBO DB7 tess H tap gt TRI STATE Test Circuit and Waveforms continued E Ue fon DS011149 7 FIGURE 2 WR RD Mode with tap lt Mode Pin is High gt tin tou DS011149 8 FIGURE 3 WR RD Mode with tap gt tint Mode Pin is High www national com TRI STATE Test Circuit and Waveforms continuea cs DBO DB7 FIGURE 4 WR RD Mode Reduced Interface System Connection with CS RD 0 Mode Pin is High DATA VALID DBO DB7 FIGURE 5 RD Mode Pipeline Operation trow must be between 200 ns and 400 ns Mode Pin is Low Typical Performance Characteristics tero VS Temperature 800 750 w 700 650 600 550 100 50 0 50 100 150 AMBIENT TEMPERATURE C DS011149 23 Linearity Error vs Reference Voltage LINEARITY ERROR LSB 0 6 0 5 0 4 v 5V 25 1 2 3 4 5 REFERENCE VOLTAGE V DS011149 24 DS011149 9 Offset Error vs Reference Voltage 0 5 0 4 OFFSET ERROR LSB DS011149 10 1 2 3 4 5
17. by connecting Vaer_ to a voltage that is equal to this minimum voltage By reducing Vrer Vree Vrers Vrer_ to less than 5V the sensitivity of the converter can be increased i e if Vaer 2 5V then 1 LSB 9 8 mV The reference arrangement also facilitates ratiometric opera tion and in may cases the power supply can be used for transducer power as well as the Vaer source Ratiometric operation is achieved by connecting Vaer_ to GND and con necting Vage and a transducer s power supply input to V The ADC08161s accuracy degrades when Vrer Vrer_ is less than 2 0V The voltage at Vrer_ sets the input level that produces a digital output of all zeroes Through Vn is not itself differen www national com Application Information continued tial the reference design affords nearly differential input ca pability for some measurement applications Figure 7 shows one possible differential configuration It should be noted that while the two Vgge inputs are fully differential the digital output will be zero for any analog input voltage if Vacr_ gt Vngr 4 0 ANALOG INPUT AND SOURCE IMPEDANCE The ADC08161 s analog input circuitry includes an analog switch with an on resistance of 70Q and a 1 4 pF capacitor Figure 7 The switch is closed during the A D s input signal acquisition time while WR is low when using the WR RD Mode A small transient current flows into the input pin each time the switch clo
18. dge of CS and returns high at the end of conversion Mode Mode RD or WR RD selection input This pin is pulled to a logic low through an internal 50 pA current sink when left unconnected RD Mode is selected if the MODE pin is left unconnected or externally forced low A complete conversion is accomplished by pulling RD low until output data appears WR RD Mode is selected when a high is applied to the MODE pin A conversion starts with the WR signal s rising edge and then using RD to access the data WR RD Mode logic high on the MODE pin This is the active low Read input With a logic low applied to the CS pin the TRI STATE data outputs DBO0 DB7 will be activated when RD goes low Figures 2 3 4 GND VREF VREF 9 Vngrour RD Mode logic low on the MODE pin With CS low a conversion starts on the falling edge of RD Output data appears on DBO DB7 at the end of conversion Figures 1 5 This is an active low output that indicates that a conversion is complete and the data is in the output latch INT is reset by the rising edge of RD This is the power supply ground pin The ground pin should be connected to a clean ground reference point These are the reference voltage inputs They may be placed at any voltage be tween GND 50 mV and V 50 mV but Veer must be greater than Vper Ideally an input voltage equal to Vage produces an output code of 0 and an input voltage gr
19. eater than 1 5 LSB produces an output code of 255 For the ADC08161 an input voltage that exceeds V by more than 100 mV or is be low GND by more than 100 mV will create conversion errors This is the active low Chip Select input A logic low signal applied to this input pin en ables the RD and WR inputs Internally the CS signal is ORed with RD and WR signals Overflow Output If the analog input is higher than Vref OFL will be low at the end of conversion It can be used when cascading two ADC08161s to achieve higher resolution 9 bits This output is al ways active and does not go into TRI STATE as DBO DB7 do When OFL is set all data outputs remain high when the ADC08061 s output data is read Positive power supply voltage input Nomi nal operating supply voltage is 5V The supply pin should be bypassed with a 10 uF bead tantalum in parallel with a 0 1 ceramic capacitor Lead length should be as short as possible The internal bandgap reference s 2 5V output is available on this pin Use a 220 uF bypass capacitor between this pin and analog ground www national com Absolute Maximum Ratings notes 1 2 If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage V Logic Control Inputs Voltage at Other Inputs and Outputs Input Current at Any Pin Note 3 Package Input
20. ersion is done by pulling RD low and holding low until the conversion is complete and output data appears This typically takes 655 ns The INT interrupt line goes low at the end of conversion A typical delay of 50 ns is needed be tween the rising edge of CS after the end of a conversion and the start of the next conversion by pulling RD low The RDY output goes low after the falling edge of CS and goes high at the end of conversion It can be used to signal a pro cessor that the converter is busy or serve as a system Trans fer Acknowledge signal 2 2 RD Mode Pipelined Operation Applications that require shorter RD pulse widths than those used in the Read mode as described above can be achieved by setting RD s width between 200 ns 400 ns Figure 5 RD pulse widths outside this range will create conversion linear ity errors These errors are caused by exercising internal in terface logic circuitry using CS and or RD during a conver sion When RD goes low a conversion is initiated and the data from the previous conversion is available on the DBO DB7 outputs Reading DBO DB7 for the first two times after power up produces random data The data will be valid dur ing the third RD pulse that occurs after the first conversion 2 3 WR RD WR then RD Mode The ADC08161 is in the WR RD mode with the MODE pin tied high A conversion starts on the rising edge of the WR signal There are two options for reading the output data
21. nel Input OV Off Channel Input 5V 0 4 20 max Note 11 PSS Power Supply Sensitivity VF 5V 596 Vngr 4 75V t1 16 tu LSB max All Codes Tested Effective Bits Vin 4 85 Vp p 7 8 Bits fin 20 Hz to 20 kHz Full Power Bandwidth Vin 4 85 Vp p 300 kHz THD Total Harmonic Distortion Vin 4 85 Vp p 0 5 96 fin 20 Hz to 20 kHz S N Signal to Noise Ratio Vin 4 85 Vp p 50 dB fin 20 Hz to 20 kHz IMD Intermodulation Distortion Vin 4 85 Vp p 50 dB fin 20 Hz to 20 kHz Cyn Analog Input Capacitance 25 pF www national com AC Electrical Characteristics The following specifications apply for V 5V t t 10 ns Veer 5V Vaer_ OV unless otherwise specified Boldface limits apply for TA Ty Tmn to Tmax all other limits Ta Ty 25 C Symbol Parameter Conditions Noe Note Limit twr Write Time Mode Pin to V 100 100 ns min Figures 2 3 4 tap Read Time Time from Rising Edge Mode Pin to V Figure 2 350 350 ns min of WR to Falling Edge of RD RD Width Mode Pin to GND Figure 5 200 250 ns min 400 400 ns max WR RD Mode Conversion Time Mode Pin to V Figure 2 500 560 ns max twn tap tacca RD Mode Conversion Time Mode Pin to GND Figure 1 655 900 ns max tacco Access Time Delay from Falling lt 100 pF Mode Pin to GND 640 900 ns max Edge of RD to Output Valid Figure 1
22. onal does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications aouaigjay debpueg Ac z pue H S SU 006 L919020V
23. ses A transient voltage whose magnitude can increase as the source impedance increases may be present at the input So long as the source impedance is less than 5000 the input voltage transient will not cause errors and need not be filtered Large source impedances can slow the charging of the sam pling capacitors and degrade conversion accuracy There fore only signal sources with output impedances less than 500Q should be used if rated accuracy is to be achieved at the minimum sample time 100 ns maximum A signal source with a high output impedance should have its output buffered with an operational amplifier Any ringing or voltage shifts at the op amp s output during the sampling period can result in conversion errors Some suggested input configurations using the internal 2 5V reference an external reference and adjusting the input span are shown in Figure 8 Correct conversion results will be obtained for input voltages greater than GND 100 mV and less than V 100 mV Do not allow the signal source to drive the analog input pin more than 300 mV higher than V or more than 300 mV lower than GND The current flowing through any analog input pin should be limited to 5 mA or less to avoid permanent dam age to the IC if an analog input pin is forced beyond these voltages The sum of all the overdrive currents into all pins must be less than 20 mA Some sort of protection scheme should be used when the input signal is expected
24. to extend more than 300 mV beyond the power supply limits A simple protection network using resistors and diodes is shown in Figure 9 5 0 INHERENT SAMPLE AND HOLD An important benefit of the ADC08161 s input architecture is the inherent sample and hold S H and its ability to mea sure relatively high speed signals without the help of an ex VOLTAGE SOURCE ternal S H In a non sampling converter regardless of its speed the input must remain stable to at least 12 LSB throughout the conversion process if full accuracy is to be maintained Consequently for many high speed signals this signal must be externally sampled and held stationary during the conversion The ADC08161 is suitable for DSP based systems because of the direct control of the S H through the WR signal The WR input signal allows the A D to be synchronized to a DSP System s sampling rate or to other ADC08161s The ADC08161 can perform accurate conversions of full scale input signals at frequencies from DC to more than 300 kHz full power bandwidth without the need of an exter nal sample and hold S H 6 0 INTERNAL BANDGAP REFERENCE The ADC08161 has an internal bandgap 2 5V reference that can be used as the Vref input A parallel combination of a 0 1 ceramic capacitor and a 220 uF tantalum capacitor should be used to bypass the pin This reduces possible noise pickup that could cause conversion errors 7 0 LAYOUT GROUNDS AND BYP
25. which relate to interface timing If an interrupt driven scheme is desired the user can wait for the INT output to go low be fore reading the conversion result Figure 3 Typically INT will go low 690 ns maximum after WR s rising edge How ever if a shorter conversion time is desired the processor need not wait for INT and can exercise a read after only 350 ns Figure 2 If RD is pulled low before INT goes low INT will immediately go low and data will appear at the outputs This is the fastest operating mode tap lt tyr with a conver sion time including data access time of 560 ns Allowing 100 ns for reading the conversion data and the delay be tween conversions gives a total throughput time of 660 ns throughput rate of 1 5 MHz 2 4 WR RD Mode with Reduced Interface System Connection CS and RD can be tied low using only WR to control the start of conversion for applications that require reduced digi tal interface while operating in the WR RD mode Figure 4 Data will be valid approximately 705 ns following WR s rising edge 3 0 REFERENCE INPUTS The ADC08161 s two Vgee inputs are fully differential and define the zero to full scale input range of the A to D con verter This allows the designer to vary the span of the ana log input since this range will be equivalent to the voltage dif ference between Vgge and _ Transducers that have outputs that minimum output voltages above GND can also be compensated
26. will automatically correct an error of up to 16 LSBs 16 LSBs 312 5 mV for Vrer 5V If the first flash conversion determines that the input voltage is between 34 Vage and 4 8 Veer LSB 2 the Voltage Estimators output code will be corrected by sub tracting 1 This results in a corrected value of 01 If the first flash conversion determines that the input voltage is be tween 8 16 Vaer LSB 2 and 56 Vper the Voltage Estima tor s output code remains unchanged After correction the 2 bit data from both the Voltage Estima tor and the first flash conversion are decoded to produce the five MSBs Decoding is similar to that of a 5 bit flash con verter since there are 32 tap points on the MSB Ladder However 31 comparators are not needed since the Voltage Estimator places the eight comparators along the MSB Lad der where reference tap voltages are present that fall above and below the magnitude of Comparators are needed outside this selected range If a comparator s output is a 0 all comparators above it will also have outputs of 0 and if a comparator s output is a 1 all comparators below it will also have outputs of 1 2 0 DIGITAL INTERFACE The ADC08161 has two basic interface modes which are se lected by connecting the MODE pin to a logic high or low 2 1 RD Mode With a logic low applied to the MODE pin the converter is set to Read mode In this configuration Figure 1 a complete conv
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National Semiconductor ADC08161 500 ns A/D Converter with S/H Function 2.5V Bandgap Reference handbo