National semiconductor ADC08060 8-Bit 20 MSPS to 60 MSPS 1.3 mW/MSPS A/D Converter handbook
Contents
1. Mid point of the reference ladder This pin should be bypassed to a clean quiet point in the analog ground plane with a 0 1 uF capacitor Analog Input that is the low side bottom of the reference ladder of the ADC Nominal range is 0 0V to Ver 1 0V Voltage on Ver and Vere inputs define the Vin conversion range Bypass well See Section 2 0 for more information www national com 2 Pin Descriptions and Equivalent Circuits Continued Pin No 23 24 13 thru 16 and 19 thru 22 1 4 12 18 17 2 5 8 11 Description the last conversion result on the falling edge of CLK input the CLK input decouple well from V4 Power Down input When this pin is high the converter is in the Power Down mode and the data output pins hold CMOS TTL compatible digital clock Input Vin is sampled Conversion data digital Output pins DO is the LSB D7 is the MSB Valid data is output just after the rising edge of Power supply for the output drivers If connected to VA DR GND Bn The ground return for the output driver supply AGND iii The ground return for the analog supply www national com 0908000V ADC08060 Absolute Maximum Ratings Notes 1 Soldering Temperature Infrared 2 10 seconds Note 6 200 G If Military Aerospace specified devices are required Storage Temperature 65 C to 150 C please contact the National Semiconductor Sales Office Distributors for availability and specifications2. O ADCO8060 O LI b January 2003 National a Semiconductor ADC08060 8 Bit 20 MSPS to 60 MSPS 1 3 mW MSPS A D Converter General Description Features The ADC08060 is a low power 8 bit monolithic analog to Single ended input digital converter with an on chip track and hold circuit Opti Internal sample and hold function mized for low cost low power small size and ease of use Low voltage single 3V operation this product operates at conversion rates of 20 MSPS to 70 Small package MSPS with outstanding dynamic performance over its full Power down feature operating range while consuming just 1 3 mW per MHz of clock frequency That s just 78 mW of power at 60 MSPS e x Raising the PD pin puts the ADC08060 into a Power Down Key Specifications mode where it consumes just 1 mW Resolution 8 bits The unique architecture achieves 7 5 Effective Bits with Maximum sampling frequency 60 MSPS min 25 MHZ input frequency The excellent DC and AC charac DNL 0 4 LSB typ teristics of this device together with its low power consump ENOB 7 5 bits typ at fin 25 MHz tion and single 3V supply operation make it ideally suited THD 60 dB typ for many imaging and communications applications includ ing use in portable equipment Furthermore the ADCO8060 is resistant to latch up and the outputs are short circuit proof The top and bottom of the ADC08060 s reference ladder are available for connections enabling a wide range of
3. SINAD ENOB vs Clock Duty Cycle 48 7 68 47 7 51 46 7 35 45 7 18 m m 44 7 02 43 6 85 42 6 68 35 40 45 50 55 60 65 Clock Duty Cycle 20006240 www national com SINAD dB SINAD dB SINAD ENOB vs Supply Voltage 48 7 68 47 7 51 46 7 35 a b 5 45 7 18 X co Gi 44 7 02 43 6 85 42 6 68 2 4 27 3 0 3 3 3 6 Supply Voltage V 20006238 SINAD ENOB vs Input Freguency 48 7 68 47 7 51 46 7 35 o Bat m 45 Ti m fa 44 7 02 43 6 85 42 6 68 5 10 15 20 25 30 Input Frequency MHz 20006239 Power Consumption vs Sample Rate Power Consumption mW 20 25 30 35 40 45 50 55 60 65 70 Clock Frequency MHz 20006219 Typical Performance Characteristics v DR v 3V fox 60 MHz fin 10 MHz unless otherwise stated Continued Spectral Response f 10 1 MHz Spectral Response f n 25 MHz Frequency MHz 20006244 Intermodulation Distortion IMD Amplitude dBc Frequency MHz 20006242 Frequency MHz 20006245 www national com 0908000V ADC08060 Specification Definitions APERTURE SAMPLING DELAY is that time reguired after the fall of the clock input for the sampling switch to open The Sample Hold circuit effectively stops capturing the input sig nal and goes into the hold mode tap after the clock goes low APERTURE JITTER is the variation in aperture delay from sample to sample Aperture jitter shows up as nois
4. Sample N 4 Sample N 5 20006231 FIGURE 1 ADC08060 Timing Diagram Functional Description The ADCO8060 uses a new unique architecture that achieves over 7 4 effective bits at input frequencies up to 30 MHz The analog input signal that is within the voltage range set by Var and Vpp is digitized to eight bits Output format is straight binary Input voltages below Vpp will cause the output word to consist of all zeroes Input voltages above Vap Will cause the output word to consist of all ones Incorporating a switched capacitor bandgap the ADCO8060 exhibits a power consumption that is proportional to fre quency limiting power consumption to what is needed at the clock rate that is used This and its excellent performance over a wide range of clock frequencies makes it an ideal choice as a single ADC for many 8 bit needs Data is acquired at the falling edge of the clock and the digital equivalent of that data is available at the digital out puts 2 5 clock cycles plus top later The ADCO8060 will 13 convert as long as the clock signal is present The device is in the active state when the Power Down pin PD is low When the PD pin is high the device is in the power down mode where the output pins hold the last conversion before the PD pin went high and the device consumes just 1 mW Applications Information 1 0 REFERENCE INPUTS The reference inputs Vpr and Vpp are the top and bottom of the reference ladder
5. respectively Input signals between these two voltages will be digitized to 8 bits External volt ages applied to the reference input pins should be within the range specified in the Operating Ratings table 1 0V to Va 0 1V for Vaz and OV to Vpt 1 0V for Vag Any device used to drive the reference pins should be able to source sufficient current into the Vpr pin and sink sufficient current from the Vprp pin www national com 0908000V ADC08060 Applications Information continued 1 5V nominal ii T ois 220 1 ADCO08060 AGND DR GND CLK 2 slal r 17 24 20006232 FIGURE 2 Simple low component count reference biasing Because of the ladder and external resistor tolerances the reference voltage can vary too much for some applications The reference bias circuit of Figure 2 is very simple and the performance is adeguate for many applications However circuit tolerances will lead to a wide reference voltage range Superior performance can generally be achieved by driving the reference pins with a low impedance source The circuit of Figure 3 will allow a more accurate setting of the reference voltages The lower amplifier must have bipo lar supplies as its output voltage must go negative to force Vr to any voltage below the Vpr of the PNP transistor Of course the divider resistors at the amplifier input could be www national com changed to suit your reference voltage needs or th
6. Operating Ratings Notes 1 2 SHER vollage V a a Operating Temperature Range 40 C lt T lt 85 C Driver Supply Voltage DR Vp Va 0 3V S ppiy VEGEN ONICO Voltage on Any Input or Output Pin 0 3V to Va Driver Supply Voltage DR Vo 42 4V to Va ke Cty Re Yay m Ground Difference IGND DR GNDI OV to 300 mV ii li VU Upper Reference Voltage Vpr 1 0V to Va 0 1V Digital Output Voltage Vou Vox DR GND to DR Vp Lower Reference Voltage Vas OV to Vaz 1 0V Input Current at Any Pin Note 3 25 mA A a d Ya Package Input Current Note 3 50 mA Power Dissipation at Ta 25 C See Note 4 ESD Susceptibility Note 5 Human Body Model 2500V Machine Model 250V Converter Electrical Characteristics The following specifications apply for Va DR Vp 3 0Vbpc Var 1 9V Vpp 0 3V C 10 pF feLk 60 MHz at 50 duty cycle Boldface limits apply for Ta Tmn to Tmax all other limits Ta 25 C Notes 7 8 m e P t Conditi DC ACCURACY Integral Non Linearity Integral Non Linearity Linearity a 1 0 Differential Non Linearity 9 Missing Codes Missing Codes ANALOG INPUT AND REFERENCE CHARACTERISTICS VR V Input Voltage T Vin 0 75V 40 5 CLK LOW Cin Vin Input Capacitance IN Vrms CLK HIGH Rin R n Input Resistance BW Full Power Bandwidth OOO e NE m TM pe ooo CLK PD DIGITAL INPUT CHARACTERISTICS Vin Logical High Input Voltage DR Vp Va 3 3V Vin Logica
7. line If the clock line is longer than t e 6 x tpp where t is the clock rise time and tpp is the propagation rate of the signal along the trace the CLOCK pin should be a c terminated with a series RC to ground such that the resistor value is equal to the characteristic impedance of the clock line and the capacitor value is 4 x bp x L Z 0 C where tpp is the signal propagation rate down the clock line L is the line length and Z is the characteristic impedance of the clock line This termination should be located as close as possible to but within one centimeter of the ADCO8060 clock pin Typical tpp is about 150 ps inch on FR 4 board material For FR 4 board material the value of C becomes 17 6x10 19 xL Z o Cz where L is the length of the clock line in inches 5 0 LAYOUT AND GROUNDING Proper grounding and proper routing of all signals are es sential to ensure accurate conversion A combined analog and digital ground plane should be used Since digital switching transients are composed largely of high frequency components total ground plane copper weight will have little effect upon the logic generated noise because of the skin effect Total surface area is more impor tant than is total ground plane volume Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor performance that may seem impossible to isolate and remedy The solution is
8. to keep the analog circuitry well separated from the digital circuitry High power digital components should not be located on or near a straight line between the ADC or any linear compo nent and the power supply area as the resulting common return current path could cause fluctuation in the analog ground return of the ADC Generally analog and digital lines should cross each other at 90 to avoid getting digital noise into the analog path In high frequency systems however avoid crossing analog and digital lines altogether Clock lines should be isolated from ALL other lines analog AND digital Even the generally accepted 90 crossing should be avoided as even a little coupling can cause problems at high frequencies Best per formance at high frequencies is obtained with a straight signal path The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input Any external component e g a filter capacitor connected be tween the converter s input and ground should be connected to a very clean point in the analog ground plane te 20006236 FIGURE 5 Layout Example www national com 0908000V ADC08060 Applications Information continued Figure 5 gives an example of a suitable layout All analog circuitry input amplifiers filters reference components etc should be placed together away from any digital compo nents 6 0 DYNAMIC PERFORMANCE The
9. 060 these supply pins should be well isolated from each other to prevent any digital noise from being coupled into the analog portions of the ADC A choke or 27Q resistor is recommended between these supply lines with adequate bypass capacitors close to the supply pins As is the case with all high speed converters the ADCO8060 should be assumed to have little power supply rejection None of the supplies for the converter should be the supply that is used for other digital circuitry in any system with a lot of digital power being consumed The ADC supplies should be the same supply used for other analog circuitry No pin should ever have a voltage on it that is in excess of the supply voltage or below ground by more than 300 mV not even on a transient basis This can be a problem upon application of power and power shut down Be sure that the supplies to circuits driving any of the input pins analog or digital do not come up any faster than does the voltage at the ADCO8060 power pins Applications Information Continueg 4 0 THE DIGITAL INPUT PINS The ADCO8060 has two digital input pins The PD pin and the Clock pin 4 1 The PD Pin The Power Down PD pin when high puts the ADCO8060 into a low power mode where power consumption is reduced to 1 mW Output data is valid and accurate about 1 millisec ond after the PD pin is brought low The digital output pins retain the last conversion output code when either the clock is sto
10. ADC08060 is ac tested and its dynamic performance is guaranteed To meet the published specifications the clock source driving the CLK input must exhibit less than 10 ps rms of jitter For best ac performance isolating the ADC clock from any digital circuitry should be done with adequate buffers as with a clock tree See Figure 6 It is good practice to keep the ADC clock line as short as possible and to keep it well away from any other signals Other signals can introduce jitter into the clock signal The clock signal can also introduce noise into the analog path to ADC CLK input CRYSTAL OSC to other circuit clock inputs 20006237 FIGURE 6 Isolating the ADC Clock from Digital Circuitry 7 0 COMMON APPLICATION PITFALLS Driving the inputs analog or digital beyond the power supply rails For proper operation all inputs should not go more than 300 mV below the ground pins or 300 mV above the supply pins Exceeding these limits on even a transient www national com basis may cause faulty or erratic operation It is not uncom mon for high speed digital circuits e g 74F and 74AC devices to exhibit undershoot that goes more than a volt below ground A 51Q resistor in series with the offending digital input will usually eliminate the problem Care should be taken not to overdrive the inputs of the ADC08060 Such practice may lead to conversion inaccura cies and even to device damage Attempting to drive a high cap
11. OOO fn 29 MHz Vn gt FS 0 25dB 54 fn 4 4 MHz Vn gt FS 0 25dB 70 pp HD2 2nd Harmonic Distortion fin 10 MHz Vw FS 0 259B8_ 65 n225 Mz Vw FS 02568 6a fn 29 MHz Vn FS 0 2548 54 Op n 4 4 MHZ Vn FS 0 250B 72 pp HD3 3rd Harmonic Distortion fin 25 MHz Vin ii FS 0 25 dB fin 29 MHz Vin FS 0 25 dB f 11 MHz Vin FS 6 25 dB IMD Intermodulation Distortion POWER SUPPLY CHARACTERISTICS DC Input la Analog Supply Current fin 10 MHz Vin FS 3 dB l DC Input DR p Output Driver Supply Current fin 10 MHz Vin FS 3 dB DC Input fin 10 MHz Viy FS 3 dB PD Low CLK Low PD Hi e z 29 4 0 2 la DRIp Total Operating Current Units Limits nA pF V min max lt Bits Bits min Bits Bits dB dB min dB dB dB dB min dB dB dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc mA max mA mA max mA mA max mA max www national com 0908000V ADC08060 Converter Electrical Characteristics Continued The following specifications apply for Va DR Vp 3 0Vbpc Var 1 9V Vpp 0 3V C 10 pF for 60 MHz at 50 duty cycle Boldface limits apply for Ta Tmn to Tmax all other limits Ta 25 C Notes 7 8 Typical Limits Unit Symbol Parameter Conditions ae a oe Limits POWER SUPPLY CHARACTERISTICS mW max fin 10 MH
12. V For example if Va is 2 7Vpc the full scale input voltage must be lt 2 6Vpc to ensure accurate conversions TO INTERNAL CIRCUITRY 20006207 Note 8 To guarantee accuracy it is required that Va and DR Vp be well bypassed Each supply pin must be decoupled with separate bypass capacitors Note 9 Typical figures are at Tj 25 C and represent most likely parametric norms Test limits are guaranteed to National s AOQL Average Outgoing Quality Level www national com 6 Typical Performance Characteristics v DR v 3V fork 60 MHZ fin 10 MHz unless other wise stated 20006208 INL vs Supply Voltage INL Bits Supply Voltage V 20006215 20006209 INL LSB INL LSB DNL LSB INL vs Temperature 40 15 10 35 60 85 Temperature C 20006214 INL vs Sample Rate 20 25 30 35 40 45 50 55 60 65 Clock Frequency MHz 20006210 DNL vs Temperature Temperature C 20006217 www national com 0908000V ADC08060 Typical Performance Characteristics v DR v 3V fox 60 MHz fin 10 MHz unless otherwise stated Continued DNL Bits SNR dB SNR dB www national com DNL vs Supply Voltage Supply Voltage V 20006218 SNR vs Temperature fy 25 MHz l fy 10 MHz 40 15 10 35 60 8 Temperature C 5 20006220 SNR vs Sample Rate 20 30 40 50 60 70 Clock Frequency MHz 20006212 DNL LSB SNR dB SNR
13. Z Vin FS 3 dB PC Power Consumption f e INS ae mW PD Low elem FBE T FSE change with 2 7V to 3 3V change Power Supply Rejection Ratio l g g poe dB in Va SNR change with 200 mV at 200 kHz Power Supply Rejection Ratio g sl dB on supply AC ELECTRICAL CHARACTERISTICS ior Mamm Conversion Rate J o o me o Mmmm Clock LowTime a em ten Minimum Clock Fig Time o s i too Output Delay CK Rise te Data vaid ez 2 ma Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Operating Ratings indicate conditions for which the device is functional but do not guarantee specific performance limits For guaranteed specifications and test conditions see the Electrical Characteristics The guaranteed specifications apply only for the test conditions listed Some performance characteristics may degrade when the device is not operated under the listed test conditions Note 2 All voltages are measured with respect to GND AGND DR GND OV unless otherwise specified Note 3 When the input voltage at any pin exceeds the power supplies that is less than AGND or DR GND or greater than VA or DR Vp the current at that pin should be limited to 25 mA The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two Note 4 The absolute maximum junction temperature Tymax for
14. acitance digital data bus The more capacitance the output drivers must charge for each conversion the more instantaneous digital current is required from DR Vp and DR GND These large charging current spikes can couple into the analog section degrading dynamic performance Buffering the digital data outputs with a 74F541 for example may be necessary if the data bus Capacitance exceeds 10 pF Dynamic performance can also be improved by adding 47Q to 56Q series resistors at each digital output reducing the energy coupled back into the converter input pins Using an inadequate amplifier to drive the analog input As explained in Section 2 0 the capacitance seen at the input alternates between 3 pF and 4 pF with the clock This dynamic capacitance is more difficult to drive than is a fixed Capacitance and should be considered when choosing a driving device The LMH6702 has been found to be a good device for driving the ADCO8060 Driving the Vr pin or the Vaz pin with devices that can not source or sink the current required by the ladder As mentioned in Section 1 0 care should be taken to see that any driving devices can source sufficient current into the Ver pin and sink sufficient current from the Vpp pin If these pins are not driven with devices than can handle the required current these reference pins will not be stable resulting in a reduction of dynamic performance Using a clock source with excessive jitter using an excessivel
15. dB DNL vs Sample Rate OTN BA e 20 25 30 35 40 45 50 55 60 65 Clock Frequency MHz 20006211 SNR vs Supply Voltage 49 47 AS 43 41 39 2 4 2 7 5 0 5 3 3 6 Supply Voltage V 20006221 SNR vs Input Frequency Input Frequency MHz 20006223 Typical Performance Characteristics v DR v 3V fek 60 MHz fin 10 MHz unless otherwise stated Continued SNR dB Distortion dBc Distortion dBc SNR vs Clock Duty Cycle 50 45 40 35 30 25 559 40 45 50 55 60 65 Clock Duty Cycle 20006224 Distortion vs Supply Voltage 2 4 2 7 3 0 3 3 3 6 Supply Voltage V 20006226 Distortion vs Input Freguency OA 2nd Harmonic 9 10 15 20 25 50 Input Frequency MHz 20006228 Distortion dBc Distortion dBc Distortion dBc Distortion vs Temperature Temperature C 20006225 Distortion vs Sample Rate Clock Frequency MHz 20006213 Distortion vs Clock Duty Cycle Clock Duty Cycle 20006229 www national com 0908000V ADC08060 Typical Performance Characteristics v DR v 3V fox 60 MHz fin 10 MHz unless otherwise stated Continued SINAD dB SINAD dB SINAD dB SINAD ENOB vs Temperature x co ENOB Bits fin 10 MHz a E 42 6 68 40 15 10 35 60 85 Temperature 9C 20006230 SINAD ENOB vs Sample Rate m Z Lu Clock Frequency MHz 20006216
16. e at the output CLOCK DUTY CYCLE is the ratio of the time that the clock wavesform is at a logic high to the total time of one clock period DIFFERENTIAL NON LINEARITY DNL is the measure of the maximum deviation from the ideal step size of 1 LSB Measured at 60 MSPS with a ramp input EFFECTIVE NUMBER OF BITS ENOB or EFFECTIVE BITS is another method of specifying Signal to Noise and Distortion Ratio or SINAD ENOB is defined as SINAD 1 76 6 02 and says that the converter is equivalent to a perfect ADC of this ENOB number of bits FULL POWER BANDWIDTH is the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input FULL SCALE ERROR is a measure of how far the last code transition is from the ideal 11 2 LSB below Vp and is defined as Vs 1 5 LSB Ver where Vmax is the voltage at which the transition to the maximum full scale code occurs INTEGRAL NON LINEARITY INL is a measure of the deviation of each individual code from a line drawn from zero scale 1 2 LSB below the first code transition through positive full scale 12 LSB above the last code transition The devia tion of any given code from this straight line is measured from the center of that code value The end point test method is used Measured at 60 MSPS with a ramp input INTERMODULATION DISTORTION IMD is the creation of additional spectral components as a result of the int
17. e divider can be replaced with potentiometers for precise settings The bottom of the ladder Vas may simply be returned to ground if the minimum input signal excursion is OV Be sure that the driving sources can source sufficient current into the Var pin and sink enough current from the Vpg pin to keep these pins stable The LMC662 amplifier shown was chosen for its low offset voltage and low cost Applications Information Continued 3V 10 uF 0 1 uF LM4040 1 2 5 1 2 LMC662 1 0 01 uF 100 T a 0 01 uF 13 14 15 4 7k 16 19 1 62k 10u E eu 0 1 uF gt 71 4 7k o 22 1N4148 0 01 uF 0 01 uF 2 7 T 10 ur 6 im 2N3906 2 100 DR GND CLK 1 2 LMC662 d olslal r 17 24 53V 20006233 FIGURE 3 Driving the reference to force desired values requires driving with a low impedance source Var should always be at least 1 0V more positive than Va to minimize noise Vam pin 9 is the center of the reference ladder and should be bypassed to a clean quiet point in the analog ground plane with a 0 1 uF capacitor DO NOT allow this pin to float 2 0 THE ANALOG INPUT The analog input of the ADC08060 is a switch followed by an integrator The input capacitance changes with the clock level appearing as 3 pF when the clock is low and 4 pF when the clock is high Since a dynamic capacitance is more 15 difficult to drive than is a fixed capacitance choose an amplifier that can drive t
18. ected to cause the failure of whose failure to perform when properly used in the life support device or system or to affect its accordance with instructions for use provided in the safety or effectiveness labeling can be reasonably expected to result in a significant injury to the user National Semiconductor National Semiconductor National Semiconductor National Semiconductor Americas Customer Europe Customer Support Center Asia Pacific Customer Japan Customer Support Center Support Center Fax 49 0 180 530 85 86 Support Center Fax 81 3 5639 7507 Email new feedback nsc com Email europe support nsc com Fax 65 6250 4466 Email nsj crc jksmtp nsc com Tel 1 800 272 9959 Deutsch Tel 49 0 69 9508 6208 Email ap support nsc com Tel 81 3 5639 7560 English Tel 44 0 870 24 0 2171 Tel 65 6254 4466 www national com Fran ais Tel 33 0 1 41 91 8790 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications 49H9AUOJ C V SdSIN MUW L SdSIN 09 118 8 0908090V
19. eraction between two sinusoidal frequencies that are applied to the ADC input at the same time IMD is the ratio of the power in the second and third order intermodulation products to the total power in the original frequencies MISSING CODES are those output codes that are skipped and will never appear at the ADC outputs These codes cannot be reached with any input value POWER SUPPLY REJECTION RATIO PSRR is a mea sure of how well the ADC rejects a change in the power supply voltage For the ADCO8060 PSRR1 is the ratio of the change in dc power supply voltage to the resulting change in Full Scale Error expressed in dB PSRR2 is a measure of www national com how well an a c signal riding upon the power supply is rejected and is here defined as SNR RO PSRR2 20Log 4 10 10 10 10 where SNRO is the SNR measured with no noise or signal on the supply lines and SNR1 is the SNR measured with a 200 kHz 200 mVp p signal riding upon the supply lines OUTPUT DELAY is the time delay after the rising edge of the input clock before the data changes at the output pins OUTPUT HOLD TIME is the length of time that the output data is valid after the rise of the input clock PIPELINE DELAY LATENCY is the number of clock cycles between initiation of conversion and when that data is pre sented to the output driver stage New data is available at every clock cycle but the data lags the conversion by the Pipeline Delay plus the Ou
20. his type of load The LMH6702 has been found to be a good amplifier to drive the ADCO8060 Figure 4 shows an example of an input circuit using the LMH6702 Any input amplifier should incorporate some gain as operational amplifiers exhibit better phase margin and transient response with gains above 2 or 3 than with unity gain f an overall gain of less than 3 is required attenuate the input and operate the amplifier at a higher gain as shown in Figure 4 www national com 0908000V ADC08060 Applications Information continued 5V ny 0 1 pF Gain Adjust 2 TN gt 10 Signal DE 240 vu G 100 47 0334F e 4 7k 3V O 1k 1k O Offset Adjust zey Ground connections marked with should enter the ground plane at a common point 3V JOQ a ELl 20006234 FIGURE 4 The input amplifier should incorporate some gain for best performance see text The RC at the amplifier output filters the clock rate energy that comes out of the analog input due to the input sampling circuit The optimum time constant for this circuit depends not only upon the amplifier and ADC but also on the circuit layout and board material A resistor value should be chosen between 18Q and 47Q and the capacitor value chose ac cording to the formula 1 C 2em Refo This will provide optimum SNR performance Best THD per formance is realized when the capacitor and resistor values are both zero To optimize SINAD reduce
21. input possibilities The digital outputs are TTL CMOS compatible s a with a separate output power supply pin to support interfac Applications ing with 3V or 2 5V logic The digital inputs CLK and PD are Digital imaging systems m TTL CMOS compatible m Communication systems The ADCO8060 is offered in a 24 lead plastic package m Portable instrumentation E m No missing codes Guaranteed Power Consumption Operating 1 3 mW MSPS typ Power down 1 mW typ TSSOP and is specified over the industrial temperature Viterbi decoders range of 40 C to 85 C Set top boxes Pin Configuration 1 24 CLK gt 23 PD 3 22 DO 4 21 D1 5 20 D2 ADC08060 s 8 17 DR GND 9 16 D4 10 15 D5 11 14 D6 12 153 D7 20006201 2003 National Semiconductor Corporation DS200062 www national com 49H9AUOJ A V SdSIN MUW L SdSIN 09 19 8 0908090V ADC08060 Ordering Information ADCO8060CIMT TSSOP ADCO8060CIMTX TSSOP tape and reel Block Diagram DR Vp Va pin 18 VRT COARSE FINE oe COMPARATORS N 17 OUTPUT Vii SWITCHES kea GE COARSE FINE ace COMPARATORS N Vig CLOCK i GEN CLK ViN AGND PD DR GND pin 17 20006202 Description Analog signal input Conversion range is Vas to Vpr Analog Input that is the high top side of the reference ladder of the ADC Nominal range is 1 0V to Va Voltage on Vpr and Vpeg inputs define the V conversion range Bypass well See Section 2 0 for more information
22. l Low Input Voltage DR Vp Va 2 7V Logical High Input Current Vin DR Vp Va 3 3V Vo 10 www national com 4 Units Limits LSB max LSB max LSB min max mV max mV max mA min mA max Converter Electrical Characteristics Continued The following specifications apply for Va DR Vp 4 3 0Vp Vat 1 9V Vpp 0 3V CO 10 pF k 60 MHz at 50 duty cycle Boldface limits apply for Ta Tm tO Tmax all other limits Ta 25 C Notes 7 8 a Typical Limits Symbol Parameter Conditions Parameter gt a Note 9 Note 9 Logical Low Input Current Vi OV DR Vp Va 2 7V 50 High Level Output Voltage Va DRVp 2 7V loy 400pA 26 24 Low Level Output Voltage Va DR Vp 2 7V Io 1 0 MA 04 05 DYNAMIC PERFORMANCE ENOB Effective Number of Bits in 25 MHz Vw FS 0 2508 75 fn 29 MHZ Vn FS 0 250B 74 fn 4 4 MHz Vn FS 0 250B 47 pp SINAD Signal to Noise amp Distortion fin gt 10 MHZ Vw FS 0 250B8_ 47 445 n225 MEZ Vus 0258 ar fn 29 MHz Vn FS 0 2548 46 Op fn 4 4 MHz Vn FS 0 250B 47 n225 MEZ Yy FS 0258 ar fn 29 MHz Vn FS 0 2548 46 o fn 4 4 MHz Vn FS 0 25d0B 64 SFDR Spurious Free Dynamic Range fin 10MHz Viv FS 0 2508 63 n225 MEZ Vu FS 0258 60 fn 29 MHz Vn FS 0 2548 54 fn 4 4 MHz Vn gt FS 0 25dB 64 Op n225 MEZ Vu FS 0258 57
23. pped or the PD pin is high 4 2 The ADC08060 Clock Although the ADCO8060 is tested and its performance is guaranteed with a 60 MHz clock it typically will function well with clock frequencies from 20 MHz to 70 MHz Halting the clock will provide nearly as much power saving as raising the PD pin high Typical power consumption with a stopped clock is 3 mW compared to 1 mW when PD is high The digital outputs will remain in the same state as they were before the clock was halted Once the clock is restored or the PD pin is brought low there is a time of 2 5 clock cycles plus top before the output data is valid However because of the linear relationship between total power consumption and clock frequency the part requires several microseconds after the clock is re started or substantially changed in frequency before the part returns to its specified accuracy The low and high times of the clock signal can affect the performance of any A D Converter Because achieving a precise duty cycle is difficult the ADCO8060 is designed to maintain performance over a range of duty cycles While it is specified and performance is guaranteed with a 50 clock duty cycle and 60 Msps ADC08060 performance is typically maintained with clock high and low times of 6 7 ns corre sponding to a clock duty cycle range of 40 to 50 with a 60 MHz clock The CLOCK line should be series terminated at the clock source in the characteristic impedance of that
24. the capacitor value until SINAD performance is optimized That is until SNR THD This value will usually be in the range of 40 to 65 of the value calculated with the above formula An accurate calculation is not possible because of the board material and layout dependance The above is indended for oversampling or Nyquist applica tions There should be no resistor or capacitor between the ADC input and any amplifier for undersampling applications The circuit of Figure 4 has both gain and offset adjustments If you eliminate these adjustments normal circuit tolerances may cause signal clipping unless care is exercised in the worst case analysis of component tolerances and the input signal excursion is appropriately limited to account for the worst case conditions Of course this means that the de signer will not be able to count on getting a full scale output with maximum signal input www national com 3 0 POWER SUPPLY CONSIDERATIONS A D converters draw sufficient transient current to corrupt their own power supplies if not adequately bypassed A 10 pF tantalum or aluminum electrolytic capacitor should be placed within an inch 2 5 cm of the A D power pins with a 0 1 uF ceramic chip capacitor placed within one centimeter of the converter s power supply pins Leadless chip capaci tors are preferred because they have low lead inductance While a single voltage source is recommended for the Va and DR Vp supplies of the ADCO8
25. this device is 150 C The maximum allowable power dissipation is dictated by Tymax the junction to ambient thermal resistance Oja and the ambient temperature Ta and can be calculated using the formula PpMAX Tymax Ta Oya In the 24 pin TSSOP ja is 92 C W so PoMAX 1 358 mW at 25 C and 435 mW at the maximum operating ambient temperature of 85 C Note that the power consumption of this device under normal operation will typically be about 180 mW 88 mW quiescent power 12 mW reference ladder power The values for maximum power dissipation listed above will be reached only when the ADC08060 is operated in a severe fault condition e g when input or output pins are driven beyond the power supply voltages or the power supply polarity is reversed Obviously such conditions should always be avoided Note 5 Human body model is 100 pF capacitor discharged through a 1 5 kQ resistor Machine model is 220 pF discharged through ZERO Ohms Note 6 See AN 450 Surface Mounting Methods and Their Effect on Product Reliability or the section entitled Surface Mount found in any post 1986 National Semiconductor Linear Data Book for other methods of soldering surface mount devices Note 7 The analog inputs are protected as shown below Input voltage magnitudes up to Va 300 mV or to 300 mV below GND will not damage this device However errors in the A D conversion can occur if the input goes above DR Vp or below GND by more than 100 m
26. tput Delay SIGNAL TO NOISE RATIO SNR is the ratio expressed in dB of the rms value of the input signal frequency at the output to the rms value of the sum of all other spectral components below one half the sampling frequency not in cluding harmonics or dc SIGNAL TO NOISE PLUS DISTORTION S N D or SINAD is the ratio expressed in dB of the rms value of the input signal frequency at the output to the rms value of all of the other spectral components below half the clock fre quency including harmonics but excluding dc SPURIOUS FREE DYNAMIC RANGE SFDR is the differ ence expressed in dB between the rms values of the input signal frequency at the output and the peak spurious signal where a spurious signal is any signal present in the output spectrum that is not present at the input TOTAL HARMONIC DISTORTION THD is the ratio ex pressed in dB of the total of the first nine harmonic levels at the output to the level of the fundatmental at the output THD is calculated as THD 20 x log where f is the RMS power of the fundamental input fre quency and f through f o is the power in the first 9 harmon ics in the output spectrum ZERO SCALE OFFSET ERROR is the error in the input voltage required to cause the first code transition It is de fined as Vorr Vzt Vps where Vz is the first code transition input voltage Timing Diagram Sample N 2 Sample N 1 CLK DBO DB7 Sample N 3
27. y long clock signal trace or having other signals coupled to the clock signal trace This will cause the sampling interval to vary causing excessive output noise and a reduction in SNR performance The use of simple gates with RC timing is generally inadequate as a clock source Physical Dimensions inches millimeters unless otherwise noted lumi UD 4 16 TYP 7 72 oes CA ar Seo yP 4 4 0 1 aa 1 78 PUN L li EZE emo 1 12 ALL LEAD TIPS ae m 22X 0 65 PIN 1 IDENT LAND PATTERN RECOMENDATION 1 1 MAX TYP a SEE DETAIL A 0 9 24X n 0 09 0 20 dL SS F I I 24X 0 19 0 30 0 110 05 TYP GAGE PLANE 0 25 22x SEATING PLANE S ae DIMENSIONS ARE IN MILLIMETERS TYP CAL SCALE 20X MTC24 Rev D NOTES UNLESS OTHERWISE SPECIFIED REFERENCE JECED REGISTRATION mo 153 VARIATION AD DATED 7 93 24 Lead Package TC Order Number ADC08060CIMT NS Package Number MTC24 LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which a are intended for surgical implant support device or system whose failure to perform into the body or b support or sustain life and can be reasonably exp
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National semiconductor ADC08060 8 Bit 20 MSPS to 60 MSPS 1.3 mW/MSPS A/D Converter handbook