National semiconductor ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 8-Bit P Compatible A/D Converters handbook
Contents
1. Shutdown uP CONTROL BUS Use ADC0801 02 03 or 05 for lowest power consumption Note Logic inputs can be driven to Vcc with A D supply at zero volts Buffer prevents data bus from overdriving output of A D when in shutdown mode Functional Description 1 0 UNDERSTANDING A D ERROR SPECS A perfect A D transfer characteristic staircase waveform is shown in Figure 1 The horizontal scale is analog input volt age and the particular points labeled are in steps of 1 LSB 19 53 mV with 2 5V tied to the 2 pin The digital out put codes that correspond to these inputs are shown as D 1 D and D 1 For the perfect A D not only will center value DS005671 80 A 1 A A 1 analog inputs produce the correct out put digital codes but also each riser the transitions between adjacent output codes will be located 14 LSB away from each center value As shown the risers are ideal and have no width Correct digital output codes will be provided for a range of analog input voltages that extend 12 LSB from the ideal center values Each tread the range of analog input voltage that provides the same digital output code is there fore 1 LSB wide www national com Functional Description Continue Figure 2 shows a worst case error plot for the ADC0801 All center valued inputs are guaranteed to produce the correct output codes and the adjacent risers are guaranteed to be no closer to the center valu2. www national com 0800QV v08000V 08000V c08009Q0V L0800 QV ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 AC Electrical Characteristics continued The following specifications apply for 5 Vpc and Tmn lt Ta lt Tmax unless otherwise specified Symbol Parameter Conditions Min Typ Max Units TRI STATE Output 5 7 5 pF Capacitance Data Buffers CONTROL INPUTS Note CLK IN Pin 4 is the input of a Schmitt trigger circuit and is therefore specified separately Vin 1 Logical 1 Input Voltage 5 25 2 0 15 Except Pin 4 CLK IN Vin 0 Logical 0 Input Voltage Voc 4 75 0 8 Voc Except Pin 4 CLK IN lin 1 Logical 1 Input Current Vin 5 Voc 0 005 1 All Inputs lin 0 Logical 0 Input Current Vin 0 1 0 005 All Inputs CLOCK IN AND CLOCK R Ve CLK IN Pin 4 Positive Going 2 7 3 1 3 5 Voc Threshold Voltage CLK IN Pin 4 Negative 1 5 1 8 2 1 Voc Going Threshold Voltage Vu CLK IN Pin 4 Hysteresis 0 6 1 3 2 0 Voc Vour 0 Logical 0 CLK R Output 1572360 pA 0 4 Voc Voltage 4 75 Vous 1 Logical 1 CLK R Output 157 360 pA 2 4 Voc Voltage 4 75 DATA OUTPUTS AND INTR Vour 0 Logical 0 Output Voltage Data Outputs lour 1 6 mA 4 75 Vpc 0 4 Voc INTR Output lout 1 0 mA Vec 4 75 Voc 0 4
3. RD DATA cs OUTPUT tL 10k DS005671 47 Vec 10k RO DATA cS OUTPUT AE S DS005671 49 tin C_ 10 pF Vou DATA ud OUTPUTS GND DS005671 48 1 20 ns C_ 10 pF RD DATA OUTPUTS Vo 10 05005671 50 tr 20 ns Timing Diag All timing is measured from the 50 voltage points START CONVERSION tWwI tw WR L ACTUAL INTERNAL STATUS OF THE CONVERTER LAST DATA WAS READ 1T0 8x 11 NOT BUSY DATA IS VALID IN QUTPUT LATCHES INTERNAL Tp INT ASSERTED 1 2 Tek DS005671 51 www national com Timing Diag Fames All timing is measured from the 50 voltage points Continued Output Enable and Reset with INTR INTR RESET Note Read strobe must occur 8 clock periods 8 fc after assertion of interrupt to guarantee reset of INTR Typical Applications 6800 Interface DS005671 53 TRISTATE DS005671 52 Ratiometeric with Full Scale Adjust 5 Vc 1 L 24 sodas OPTIONAL ur FS ADJUST DS005671 54 Note before using caps at or Vngr 2 see section 2 3 2 Input Bypass Capacitors 7 www national com s0800QV v08000V 08090V c0800Q0V L0800 QV ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Typical Applications Continued Absolute with a 2 500V Reference 5 DS005671 55
4. 0 508 0 060 0 005 224010250 001820003 3179 3556 0325 0040 1 524 0 127 0 457 0 076 325 015 1016 0 256 B N20A REV G Molded Dual In Line Package Order Number ADC0801LCN ADCO802LCN ADC0803LCN ADCO804LCN or ADCO805LCN NS Package Number N20A www national com 40 Notes LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 Systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor National Semiconductor Corporation Europe Americas Fax 49 0 1 80 530 85 86 Tel 1 800 272 9959 Email europe support nsc com Fax 1 800 737 7018 Deutsch Tel 49 0 1 80 530 85 85 Email support nsc com English Tel 49 0 1 80 532 78 32 Frangais Tel 49 0 1 80 532 93 58
5. ADCOBOILCN National Semiconductor ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 8 Bit uP Compatible A D Converters General Description The ADCO801 ADC0802 ADC0803 ADCO804 and ADCO0805 are CMOS 8 bit successive approximation A D converters that use differential potentiometric ladder similar to the 256R products These converters are designed to allow operation with the NSC800 and INS8080A derivative control bus with TRI STATE output latches di rectly driving the data bus These A Ds appear like memory locations or I O ports to the microprocessor and no interfac ing logic is needed Differential analog voltage inputs allow increasing the common mode rejection and offsetting the analog zero input voltage value In addition the voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution Features m Compatible with 8080 uP derivatives no interfacing logic needed access time 135 ns m Easy interface to all microprocessors or operates stand alone November 1999 Differential analog voltage inputs m Logic inputs and outputs meet both MOS and TTL voltage level specifications m Works with 2 5V LM336 voltage reference m On chip clock generator m OV to 5V analog input voltage range with single 5V supply No zero adjust required 0 3 standard width 20 pin DIP package 20 pin molded chip carrier or small outline package Operates ratiometr
6. Vour 1 Logical 1 Output Voltage 152 360 HA 4 75 Voc 2 4 Voc Vous 1 Logical 1 Output Voltage 1572 10 pA 4 75 Voc 4 5 Voc lour TRI STATE Disabled Output Vout 9 3 Leakage All Data Buffers Vout 5 3 IsouncE Vour Short to Gnd Ta 25 C 4 5 6 Isink Vou Short to Voc 25 9 0 16 MApc POWER SUPPLY loc Supply Current Includes fc 7640 kHz Ladder Current Vuge 22 NC 25 and CS 5V ADC0801 02 03 04LCJ 05 1 1 1 8 mA ADCO0804LCN LCWM 1 9 2 5 mA Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions Note 2 All voltages are measured with respect to Gnd unless otherwise specified The separate A Gnd point should always be wired to the D Gnd Note 3 A zener diode exists internally from Voc to Gnd and has a typical breakdown voltage of 7 Voc Note 4 For Vin 2 Vin the digital output code will be 0000 0000 Two on chip diodes are tied to each analog input see block diagram which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the Vcc supply Be careful during testing at low Vcc levels 4 5V as high level analog inputs 5V can cause this input diode to conduct especially at elevated temperatures and cause errors for analog in
7. www national com 38 Functional Description continued INTERRUPT SERVICING SUBROUTINE LOC 0038 0039 003A 003B 0040 0042 0044 0045 0046 0048 004B 004C 004D 004E 0051 0052 0055 0057 0059 005A 005B 005C 005D 0060 0061 0062 0063 OBJ CODE TEST NEXT LOAD DONE SOURCE STATEMENT PUSH HL PUSH BC PUSH AF LD HL X3E00 LDC XOl OUT X00 A INA X00 LDB A LDA C CP X08 JPZ DONE LDB A JPC LOAD INCC JP TEST INA C XOR FF LD HL A INCL LD HL C INCL JP NEXT POP AF POP BC POP HL RET Save contents of all registers affected by this subroutine Assumed INT mode learlier set Initialize memory pointer where data will be stored Cregisterwillbe port ADDR of A D converters Load peripheral status word into 8 bit latch Load status word into accumulator COMMENT Save the status word Test to see if the status of all A D s have been checked If so exit subroutine Test a single bit in status word by looking for 1 to be rotated into the CARRY an INT 15 loadedasa l If CARRY is set then load contents of A D at port ADDR register If CARRY is not set increment C register to point to next A D then test next bit in status word Read data from interrupting A D and invert the data Store the data Store A D identifier A D port ADDR Test next bit in status word Re establishall registers
8. 15v 0 A D CLK IN 05005671 64 100 2 lt 1460 kHz IF MORE THAN 5 ADDITIONAL A Os USE A CMOS BUFFER NOT T2L 05005671 63 www national com 10 Typical Applications Continued Self Clocking in Free Running Mode uP Interface for Free Running A D TSTAGE SYSRESET 0248 START Vg PREVENTS RD DURING A D DS005671 65 DATA UPDATE After power up a momentary grounding of the WR input is needed to RESET mx tcu RESET guarantee operation Operating with Automotive Ratiometric Transducers Ratiometric with Vgge 2 Forced Vcc 5 Vpc Vin Vi A D ADCOB05 DS005671 67 Vin 0 15 Voc 15 of Voc lt VxpR lt 85 of Voc Compatible Differential Input Comparator with Pre Set Vos with or without Hysteresis QUTPUT 6 Voo 1 5k LM336 V7 OR Vos 1 2 CD4016 DS005671 69 See Figure 5 to select R value DB7 1 for Vin gt Vin VReF 2 Omit circuitry within the dotted area if hysteresis is not needed 150 pF Tm BINARY CTR DS005671 68 READY TO aP DS005671 66 5 11 www national com s0800QV v08000V 08090V c0800Q0V L0800 QV ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Typical Applications Continued Handling 10V Analog Inputs Low Cost Interfaced Temperature to Digital Converter LM335 DS005671 70 DS005671 71 Be
9. STX LDX RTS TEMP2 002C FFF8 5000 TEMPL 020F ENDP 5000 1 CONVRT 1 5000 X 0200 0000 0200 1 TEMP2 Save contents of X Upon IRQ low CPU jumps to 002C Start ADCO801 Wait for interrupt Is final data stored Restarts ADCO801 Read data StoreitatX Starting address for data storage Reinitialize TEMPL Return from subroutine To user s program DS005671 A1 Note 22 In order for the microprocessor to service subroutines and interrupts the stack pointer must be dimensioned in the user s program FIGURE 16 ADC0801 MC6820 PIA Interface DS005671 25 www national com 30 Functional Description continued SAMPLE PROGRAM FOR Figure 16 ADC0801 MC6820 PIA INTERFACE 0010 CE 00 38 DATAIN LDX 0013 FF FF F8 STX 0016 B6 80 06 LDAA 0019 4F CLRA 001A B7 80 07 STAA 001D B7 80 06 STAA 0020 CLI 0021 C6 34 LDAB 0023 86 3D LDAA 0025 F7 80 07 CONVRT STAB 0028 B7 80 07 STAA 002B 3E WAI 002C DE 40 LDX 002E 8C 02 OF 0031 27 OF BEQ 0033 08 INX 0034 DF 40 STX 0036 20 ED BRA 0038 DE 40 INTRPT LDX 003A B6 80 06 LDAA 003D A7 00 STAA 003F 3B RTI 0040 02 00 TEMPL FDB 0042 CE 02 00 ENDP LDX 0045 DF 40 STX 0047 39 RTS PIAORB EQU PIACRB EQU The following schematic and sample subroutine DATA IN may be used to interface up to 8 ADC0801 s directly to the MC6800 CPU This scheme can easily be extended to allow the int
10. Wait forinterrupt R2 AGAIN If 16 bytes are read go to user s program 50H A RL Input data CS still low GRO Store inmemory RO Increment storage counter Pl 1 Reset CS signal A Clear ACC to get out of the interrupt loop DS005671 A0 MM74C32 DS005671 23 FIGURE 14 Mapping the A D as an I O Device for Use with the Z 80 CPU Additional I O advantages exist as software DMA routines are available and use can be made of the output data trans fer which exists on the upper 8 address lines A8 to A15 dur www national com 28 Functional Description continued ing I O input instructions For example MUX channel selec tion for the A D can be accomplished with this operating mode 4 3 Interfacing 6800 Microprocessor Derivatives 6502 etc The control bus for the 6800 microprocessor derivatives does not use the RD and WR strobe signals Instead it em ploys a single R W line and additional timing if needed can be derived fom the 62 clock All I O devices are memory mapped in the 6800 system and a special signal VMA indi cates that the current address is valid Figure 15 shows an interface schematic where the A D is memory mapped in the 6800 system For simplicity the CS decoding is shown using DM8092 Note that in many 6800 systems an already de coded 4 5 line is brought out to the common bus at pin 21 This can be tied directly to the CS pin of the A D provided that no other dev
11. plied to the Vi pin to absorb the offset the reference volt age can be made equal to 12 of the 3V span or 1 5 Voc The A D now will encode the Vn signal from 0 5V to 3 5 V with the 0 5V input corresponding to zero and the 3 5 input corresponding to full scale The full 8 bits of resolution are therefore applied over this reduced analog input voltage range 2 4 2 Reference Accuracy Requirements The converter can be operated in a ratiometric mode or an absolute mode In ratiometric converter applications the magnitude of the reference voltage is a factor in both the out put of the source transducer and the output of the A D con verter and therefore cancels out in the final digital output code The ADC0805 is specified particularly for use in ratio metric applications with no adjustments required In absolute conversion applications both the initial value and the tem perature stability of the reference voltage are important fac tors in the accuracy of the A D converter For Vp_e 2 volt ages of 2 4 Vpc nominal value initial errors of 10 mVpc will cause conversion errors of 1 LSB due to the gain of 2 of the Verer 2 input In reduced span applications the initial value and the stability of the Vae 2 input voltage become even more important For example if the span is reduced to 2 5V the analog input LSB voltage value is correspondingly re duced from 20 mV 5V span to 10 mV and 1 LSB at the Vrer 2 input becomes 5 mV
12. For low power see also LM385 2 5 Zero Shift and Span Adjust 2V lt Vy lt 5V Vcc 8 Q 12k SETS ZERO SETS VOLTAGE SPAN CODE VOLTAGE SEE SECTION 2 4 DS005671 57 Absolute with a 5V Reference Vec VREF 5 Vpc I I wo 1 1 l 1 1 l 1 L J OPTIONAL FS ADJUST DS005671 56 Span Adjust OV lt lt 3V 5 Voc 2k LM336 DS005671 58 www national com Typical Applications Continued Directly Converting a Low Level Signal A uP Interfaced Comparator Vec 5 5 OV S Vin lt 512 mV 05005671 60 Vin gt Vin Output FF Hex For Vin lt Vin DS005671 59 00 15 Voc O Vper 2 256 mV 1 mV Resolution with uP Controlled Range 5 2 8 DAC 2500 Voc 2 500 V E MICRO DACTM DACO830 LM336 DS005671 61 2 128 mV 1 LSB 1 mV VpacsVins Vpact256 mV 0 lt Vpac lt 2 5V 9 www national com s0800QV v08000V 08090V 70800Q0V L0800 QV ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Typical Applications continued Use a large R value to reduce loading at CLK R output Digitizing a Current Flow 01 LOAD 2A FULL SCALE Voc ZERO 05005671 62 Self Clocking Multiple A Ds External Clocking 5v d b Lb 227V MIN 1 d 4 F
13. a lab DVM with a numerical sub traction feature is available to read the difference voltage directly The analog input voltage can be supplied by a low frequency ramp generator and an X Y plotter can be used to provide analog error Y axis versus analog input X axis For operation with a microprocessor or a computer based test system it is more convenient to present the errors digi tally This can be done with the circuit of Figure 11 where the output code transitions can be detected as the 10 bit DAC is incremented This provides 14 LSB steps for the 8 bit A D un der test If the results of this test are automatically plotted with the analog input on the X axis and the error in LSB s as the Y axis a useful transfer function of the A D under test results For acceptance testing the plot is not necessary and the testing speed can be increased by establishing internal limits on the allowed error for each code 4 0 MICROPROCESSOR INTERFACING To dicuss the interface with 8080A and 6800 microproces Sors a common sample subroutine structure is used The microprocessor starts the A D reads and stores the results of 16 successive conversions then returns to the user s pro gram The 16 data bytes are stored in 16 successive memory locations All Data and Addresses will be given in hexadecimal form Software and hardware details are pro vided separately for each type of microprocessor 4 1 Interfacing 8080 Microprocess
14. as they were before the interrupt Return to original program DS005671 A6 39 www national com s0800QV v08000V 08090V c0800QV L0800 QV ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Physical Dimensions inches millimeters unless otherwise noted 0 496 0 512 12 598 13 005 19 18 17 16 15 14 13 12 1 A LIII ILI 0 394 0 419 LEADNO 1 1 7 IDENT y 0 291 0 299 7 391 7 595 0 010 0 02 0 093 0 104 0 254 0 737 49 2 362 2 642 0 004 0 012 8 MAX TYP Pini fh A ALL LEADS FARIA 0102 0309 __ 1108008 10 10 alee us p Fo T1 pu 0 009 0 013 aj 0 016 0 050 pus Si a 0 050 0 014 0 020 0 229 0 330 TIPS gt 40 1270 0 356 1 270 et 0 388 0 508 TYP ALL LEADS TYP ALL LEADS 0 008 0 203 208 REV F SO Package M Order Number ADCO802LCWM or ADCO804LCWM NS Package Number M20B 1 013 1 040 __ 0 092 x 0 030 2573 2642 2 337 X 0 762 Ej 0 032 0 005 MAX DP 0813 0 127 RAD PIN NO 1 IDENT 0 260 0 005 6 604 0 127 PIN NO 1 IDEN 0 280 CE 7112 OPTION 1 MIN 0 300 0 320 OPTION 2 76208 1208 0 060 NOM 0 040 2 0 130 0 005 382 0127 1 851 TE E 0 145 0 200 53 580 95 5 0 009 0 015 800 004 1 0 229 0 381 218 0 020 20 100 0 010 Ee 0 125 0 140
15. controller and the INS8224 clock generator For simplicity the A D is controlled as an I O device specifically an 8 bit bi directional port located at an arbitrarily chosen port address EO The TRI STATE output capability of the A D eliminates the need for a peripheral interface device however address decoding is still required to generate the appropriate CS for the con verter DS005671 99 It is important to note that in systems where the A D con verter is 1 of 8 or less I O mapped devices no address de coding circuitry is necessary Each of the 8 address bits AO to A7 can be directly used as CS inputs one for each I O device 4 1 2 INS8048 Interface The INS8048 interface technique with the ADC0801 series see Figure 13 is simpler than the 8080A CPU interface There are 24 I O lines and three test input lines in the 8048 With these extra I O lines available one of the I O lines bit 0 of port 1 is used as the chip select signal to the A D thus eliminating the use of an external address decoder Bus con trol signals RD WR and INT of the 8048 are tied directly to the A D The 16 converted data words are stored at on chip RAM locations from 20 to 2F Hex The RD and WR signals are generated by reading from and writing into a dummy ad dress respectively A sample interface program is shown below 27 www national com s0800QV v08000V 08090V 708009Q0V L0800 QV ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 F
16. the differential input voltage 2 3 3 Input Source Resistance Large values of source resistance where an input bypass ca pacitor is not used will not cause errors as the input currents settle out prior to the comparison time If a low pass filter is required in the system use a low valued series resistor 1 kQ for a passive RC section or add an op amp RC ac tive low pass filter For low source resistance applications 1 a 0 1 pF bypass capacitor at the inputs will prevent noise pickup due to series lead inductance of a long wire A www national com 20 Functional Description continued 1009 series resistor can be used to isolate this capacitor both the R and C are placed outside the feed back loop from the output of an op amp if used 2 3 4 Noise The leads to the analog inputs pins 6 and 7 should be kept as short as possible to minimize input noise coupling Both noise and undesired digital clock coupling to these inputs can cause system errors The source resistance for these in puts should in general be kept below 5 Larger values of Source resistance can cause undesired system noise pickup Input bypass capacitors placed from the analog in puts to ground will eliminate system noise pickup but can create analog scale errors as these capacitors will average the transient input switching currents of the A D see section 2 3 1 This scale error depends on both a large source re s
17. www national com Italiano Tel 49 0 1 80 534 16 80 National Semiconductor National Semiconductor Asia Pacific Customer Japan Ltd Response Group Tel 81 3 5639 7560 Tel 65 2544466 Fax 81 3 5639 7507 Fax 65 2504466 Email sea support nsc com National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications SI9BAUOD C V 18 8 s08000V r08000V 0800QV 20800QV L0800Q0V
18. 0 0 280 D 1 1 0 1 13 16 13 256 4 160 0 260 1 1 0 0 3 4 3 64 3 840 0 240 B 1 0 1 1 11 16 11 256 3 520 0 220 A 1 0 1 0 5 8 5 128 3 200 0 200 9 1 0 0 1 9 16 9 256 2 880 0 180 8 1 0 0 0 1 2 1 32 2 560 0 160 7 0 1 1 1 7 16 7 256 2 240 0 140 6 0 1 1 0 3 8 3 128 1 920 0 120 0 1 0 1 5 16 2 256 1 600 0 100 4 0 1 0 0 1 4 1 64 1 280 0 080 3 0 0 1 1 3 16 3 256 0 960 0 060 2 0 0 1 0 1 8 1 128 0 640 0 040 1 0 0 0 1 1 16 1 256 0 320 0 020 0 0 0 0 0 0 0 Note 15 Display Output VMS Group VLS Group 25 www national com SO8090V P0s00 dv E0800dV 2Z0800dV LO800 QV ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Functional Description continued gt 14 VO WR 27 VO RD 25 13 DB1 16 DB2 11 DB3 9 5 DB5 18 20 DB 7 ANALOGO INPUTS AD15 36 AD14 39 DM8131 AD13 3 BUS 38 COMPARATOR AD12 37 AD11 40 AD10 1 DS005671 20 Note 16 Pin numbers for the DP8228 system controller others are INS8080A Note 17 Pin 23 of the INS8228 must be tied to 12V through a 1 resistor to generate the RST 7 instruction when an interrupt is acknowledged as required by the accompanying sample program FIGURE 12 ADC0801_INS8080A CPU Interface www national com 26 Functional Description continued SAMPLE PROGRAM FOR Figure 12 ADC0801 INS8080A CPU INTERFACE 0038 c3 0003 RST 7 JMP LD DATA 0100 21
19. 0002 START LXIH 0200H HL pair will point to data storage locations 0103 310004 RETURN LXI SP 0400H Initialize stack pointer Note 1 0106 7D MOVA L Test of bytes entered 0107 FEOF CPIOFH If 16 JMP to 0109 1301 JZ CONT user program 010C D3 E0 OUT EO H Start A D O10E FB EI Enable interrupt 010 00 LOOP NOP Loop until end of 0110 C3 OF O1 JMP LOOP conversion 0113 CONT User program to process data 0300 DB EO LD DATA INEOH Load data into accumulator 0302 77 MOVM A Store data 0303 23 INXH Increment storage pointer 0304 C30301 JMP RETURN Note 18 The stack pointer must be dimensioned because a RST 7 instruction pushes the PC onto the stack Note 19 All address used were arbitrarily chosen The standard control bus signals of the 8080 CS RD and WR can be directly wired to the digital control inputs of the A D and the bus timing requirements are met to allow both starting the converter and outputting the data onto the data bus A bus driver should be used for larger microprocessor systems where the data bus leaves the PC board and or must drive capacitive loads larger than 100 pF 4 1 1 Sample 8080A CPU Interfacing Circuitry and Program The following sample program and associated hardware shown in Figure 12 may be used to input data from the con verter to the INS8080A CPU chip set comprised of the INS8080A microprocessor the INS8228 system
20. 03 Total Adjusted Error Note 8 With Full Scale Adj 12 LSB See Section 2 5 2 ADC0804 Total Unadjusted Error Note 8 Vaer 2 2 500 Voc 1 LSB ADC0805 Total Unadjusted Error Note 8 Vrer 2 No Connection 1 LSB Vrer 2 Input Resistance Pin 9 ADC0801 02 03 05 2 5 8 0 ADC0804 Note 9 0 75 1 1 kQ Analog Input Voltage Range Note 4 V or V Gnd 0 05 Vect0 05 Voc DC Common Mode Error Over Analog Input Voltage 1 16 14 LSB Range Power Supply Sensitivity Voc 5 Voc 10 Over 1 16 tu LSB Allowed Vin and Viy Voltage Range Note 4 AC Electrical Characteristics The following specifications apply for 5 and Tmn lt Ta lt Tmax unless otherwise specified Symbol Parameter Conditions Min Typ Max Units Tc Conversion Time fci 7640 kHz Note 6 103 114 us Tc Conversion Time Notes 5 6 66 73 l feik fork Clock Frequency Vec 5V Note 5 100 640 1460 kHz Clock Duty Cycle 40 60 CR Conversion Rate in Free Running INTR tied to WR with 8770 9708 conv s Mode CS 0 fc 7640 kHz Width of WR Input Start Pulse Width CS 0 Vc Note 7 100 ns tacc Access Time Delay from Falling C 2100 pF 135 200 ns Edge of RD to Output Data Valid tu tou TRI STATE Control Delay C 210 pF 10 125 200 ns from Rising Edge of RD to See TRI STATE Test Hi Z State Circuits twi tri Delay from Falling Edge 300 450 ns of WR or RD to Reset of INTR Input Capacitance of Logic 5 1 5 pF Control Inputs
21. 3D3D JMP Normal DS005671 A5 Note 29 All numerical values are hexadecimal representations FIGURE 21 Software for Auto Zeroed Differential A D 5 3 Multiple A D Converters in a Z 80 Interrupt Driven The stack pointer must be dimensioned in the main pro Mode Continued gram as the RST 7 instruction automatically pushes the The following notes apply PC onto the stack and the subroutine uses an additional Itis assumed that the CPU automatically performs a RST 6 stack addresses 7 instruction when a valid interrupt is acknowledged The peripherals of concern are mapped into I O space CPU is in interrupt mode 1 Hence the subroutine start with the following port assignments ing address of X0038 The address bus from the Z 80 and the data bus to the Z 80 are assumed to be inverted by bus drivers A D data and identifying words will be stored in sequen tial memory locations starting at the arbitrarily chosen ad dress X 3E00 37 www national com SO8090V r08s00dv E0800dV 20800dV LO800dV ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Functional Description continued HEX PORT ADDRESS PERIPHERAL 04 A D 4 HEX PORT ADDRESS PERIPHERAL 05 A D 5 00 MM74C374 8 bit flip flop 06 A D 6 01 A D 1 07 ND 7 02 AD 2 This port address also serves as the A D identifying word in 03 A D 3 the program D4 DATA BUS MM74C374 9 08 our CLK 015 08 DS005671 29 FIGURE 22 Multiple A Ds with Z 80 Type Microprocessor
22. 4 2601 1 Auto Zero Subroutine 53006 7 3007 DS3E6 OUTC Close SW1 open SW2 3D09 0680 MVI 80 Initialize SAR bit pointer SDOB SET7F MVIA7F Initialize SAR code SDOD 4F MOVC A Return SDOE D3E5 OUT B Port SAR code 3D10 S1AA3D LXI SP Start Dimension stack pointer 3D13 D3E4 OUTA Start A D 3D15 FB IE 3Dl6 00 NOP Loop Loop until INT asserted D17 C3163D JMP Loop 1 7 MOV A D Auto Zero 3D1B C600 ADI 00 SD1D CA2DSD JZSetC Test A D output data for zero 3020 78 Shift B SD21 F600 ORI 00 Clear carry 3023 1F RAR Shift 1 inB right one place 3024 FEOO CPI 00 Is zero If yes last 35026 CA373D JZDone approximation has been made 35029 47 MOV B A 3D2A C3333D JMPNewC 3D2D 79 MOVA C Set 5028 BO ORAB Set bit inC that is in same SD2F 4F MOVC A positionas 1 3030 C3203D JMP Shift B 3D33 A9 XRAC NewC ClearbitinCthatisin 3034 C30D3D JMP Return Same poSitionas 1 inB 3037 47 MOVB A Done then output new SAR code 3D38 7C MOVA H Open SW1 close SW2 then 3039 EEOS XRI 03 proceed with program Preamp 3D3B D3E6 OUT 3 is now zeroed 3D3D Normal e Program for processing proper data values 3C3D DBE4 INA Read A D Subroutine Read A D data SC3F XRI FF Invert data 3C41 57 MOVD A 3C42 78 MOVA B Is 0 If stay 3643 EGFF 3 in auto zero subroutine 3C45 21 30 JNZAuto Zero 3C48 C3
23. 4 LSB ADC0803 12LSB ADC0804 1 LSB ADC0805 1 LSB www national com 2 Absolute Maximum Ratings Supply Voltage Vcc Note 3 Voltage Logic Control Inputs At Other Input and Outputs Lead Temp Soldering 10 seconds Dual In Line Package plastic Dual In Line Package ceramic Surface Mount Package Vapor Phase 60 seconds Electrical Characteristics Notes 1 2 If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Infrared 15 seconds Storage Temperature Range ESD Susceptibility Note 10 Package Dissipation at 25 220 C 65 to 150 C 875 mW 800V lt lt 40 lt lt 85 40 lt lt 85 0 lt lt 70 0 lt lt 70 4 5 to 6 3 Vc nd Operating Ratings notes 1 2 0 3V to 18V Temperature Range 0 3V to Vcc40 3V ADCO804LCJ ADCO0801 02 03 05LCN 260 C ADCO0804LCN 300 C ADC0802 04LCWM Range of Vec 215 C The following specifications apply for 5 Voc lt lt and 47640 kHz unless otherwise specified Parameter Conditions Min Typ Max Units ADC0801 Total Adjusted Error Note 8 With Full Scale Adj 14 LSB See Section 2 5 2 ADC0802 Total Unadjusted Error Note 8 Vnge 272 500 Voc 12 LSB ADCO08
24. As can be seen this reduces the allowed initial tolerance of the reference voltage and re quires correspondingly less absolute change with tempera ture variations Note that spans smaller than 2 5V place even tighter requirements on the initial accuracy and stability of the reference source In general the magnitude of the reference voltage will re quire an initial adjustment Errors due to an improper value of reference voltage appear as full scale errors in the A D transfer function IC voltage regulators may be used for ref erences if the ambient temperature changes are not exces sive The LM336B 2 5V IC reference diode from National Semiconductor has a temperature stability of 1 8 mV typ 6 mV max over 0 C lt T lt 70 C Other temperature range parts are also available 21 www national com s0800QV v08000V 08090V 20800Q0V L0800 QV ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Functional Description continued 3 5V 5V F vig MAX min SPAN 73V 0 5 05005671 87 Analog Input Signal Example 2 5 Errors and Reference Voltage Adjustments 2 5 1 Zero Error The zero of the A D does not require adjustment If the mini mum analog input voltage value is not ground a zero offset can be done The converter can be made to out put 0000 0000 digital code for this minimum input voltage by biasing the A D Viy input at this Value see Appli cations section This
25. D Start and Output Enable labels In addition these inputs are active low to allow an easy interface to microprocessor control busses For non microprocessor based applications the CS input pin 1 can be grounded and the standard A D Start function is ob tained by an active low pulse applied at the WR input pin 3 and the Output Enable function is caused by an active low pulse at the RD input pin 2 www national com s0800QV v08000V 08090V c0800Q0V L0800 QV ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Functional Description Continued 2 2 Analog Differential Voltage Inputs and Common Mode Rejection This A D has additional applications flexibility due to the ana log differential voltage input The Vn input pin 7 can be used to automatically subtract a fixed voltage value from the input reading tare correction This is also useful in 4 mA 20 mA current loop conversion In addition common mode noise can be reduced by use of the differential input The time interval between sampling Vin and Viy is 4 clock periods The maximum error voltage due to this slight time difference between the input voltage samples is given by 4 5 AVe MAX Vp 27rfcm where AV is the error voltage due to sampling delay Vp is the peak value of the common mode voltage fom is the common mode frequency As an example to keep this error to 14 LSB 5 mV when operating with a 60 Hz common mode frequency fem and usi
26. Differential Inputs JANNEL DIFFERENTIAL MUX c04052 P CHANNEL SELECT FROM OUTPUT DS005671 74 DS005671 75 20 Hz Uses Chebyshev implementation for steeper roll off unity gain 2nd order low pass filter Adding a separate filter for each channel increases system response time if an analog multiplexer is used Output Buffers with A D Data Enabled Increasing Bus Drive and or Reducing Time on Bus TALSTATE SUFFERS TRISTATE BUFFERS m DS005671 77 DS005671 76 All falli f A D output data is updated 1 CLK period prior to assertion of INTR ows Outpul at falling edge oos 15 www national com SO8090V r08s00dv E0800dV Z0800dV LO800dV ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Typical Applications Continued Sampling an AC Input Signal fin MAX FILTER SKIRT 60 TO 80 48 LOW PASS MULTI POLE FILTER up cerae SAMPLE AND 5 CONTROL DS005671 78 Note 11 Oversample whenever possible keep fs gt 2f 60 to eliminate input frequency folding aliasing and to allow for the skirt response of the filter Note 12 Consider the amplitude errors which are introduced within the passband of the filter 70 Power Savings by Clock Gating 78032 Complete shutdown takes 30 seconds 1 2 a 0 gm 4 3 74c04 05005671 79 Power Savings by A D
27. TERFACING MULTIPLE A D s IN AN MC6800 SYSTEM ADDRESS HEX CODE MNEMONICS COMMENTS 0010 DF 44 DATAIN STX TEMP Save Contents of X 0012 CE00 2A LDX 002 Upon IRQ LOW CPU 0015 FF FF F8 STX FFF8 Jumps to 002A 0018 B7 5000 STAA 5000 StartsallA D s 001B CLI 001C WAI Wait forinterrupt 001D CE 50 00 LDX 5000 0020 DF 40 STX INDEX1 Reset both INDEX 0022 CE 02 00 LDX 0200 land2to starting 0025 DF 42 STX INDEX2 addresses 0027 DE 44 LDX TEMP 0029 39 RTS Return from subroutine 002A DE 40 INTRPT LDX INDEX1 INDEX X 002C A6 00 LDAA X Read data in from A Dat X 002E 08 INX Increment X by one 002F DF 40 STX INDEX1 3X INDEX1 0031 DE 42 LDX INDEX2 INDEX2 X DS005671 A3 SAMPLE PROGRAM FOR Figure 17 INTERFACING MULTIPLE A D s IN AN MC6800 SYSTEM ADDRESS HEX CODE MNEMONI 0033 A700 STAA 0035 8C 0207 CPX 0038 2705 BEQ 003A 08 INX 003B DF 42 STX 003D 20 EB BRA 0053F 3B RETURN RTI 0040 50 00 INDEX1 FDB 0042 02 00 INDEX2 FDB 0044 00 00 TEMP FDB Cs COMMENTS X Store dataat X 0207 Have all A D s been read RETURN Yes branch to RETURN No increment X by one INDEX2 X INDEX2 INTRPT Branch to 002A 5000 Starting address for A D 0200 Starting address for data storage 0000 05005671 4 Note 25 In order for the microprocessor to service subroutines and interrupts the stack pointer must be dimensioned the user s program For amplification of DC input signals a maj
28. a high to low transition because the SET input can control the Q output of the INTR F F even though the RESET input is constantly at a 1 level in this operating mode This INTR output will therefore stay low for the duration of the SET signal which is 8 periods of the external clock frequency assuming the A D is not started during this interval When operating in the free running or continuous conversion mode INTR pin tied to WR and CS wired low see also section 2 8 the START F F is SET by the high to low tran sition of the INTR signal This resets the SHIFT REGISTER 17 RESET SHIFT REGISTER 0 BUSY AND QUIESCENT STATE INPUT PROTECTION FOR ALL LOGIC INPUTS INPUT TO INTERNAL CIRCUITS BV 30V F F1 START CONVERSION IF RESET 0 DS005671 13 which causes the input to the D type latch LATCH 1 to go low As the latch enable input is still present the Q output will go high which then allows the INTR F F to be RESET This reduces the width of the resulting INTR output pulse to only a few propagation delays approximately 300 ns When data is to be read the combination of both CS and RD being low will cause the INTR F F to be reset and the TRI STATE output latches will be enabled to provide the 8 bit digital outputs 2 1 Digital Control Inputs The digital control inputs CS RD and WR meet standard T L logic voltage levels These signals have been renamed when compared to the standard A
29. ance of the switches as they must conduct only the input bias current of the input amplifiers Output Port B is used as a successive approximation regis ter by the 8080 and the binary scaled resistors in series with each output bit create a D A converter During the zeroing subroutine the voltage at V increases or decreases as re quired to make the differential output voltage equal to zero This is accomplished by ensuring that the voltage at the out put of A1 is approximately 2 5V so that a logic 1 5V on 33 www national com SO8090V r08s00dv E0800dV Z0800dV LO800dV ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Functional Description Continued any output of Port B will source current into node Vx thus raising the voltage at Vx and making the output differential more negative Conversely a logic 0 0V will pull current out of node Vy and decrease the voltage causing the differ ential output to become more positive For the resistor val ues shown Vy can move 12 mV with a resolution of 50 uV which will null the offset error term to 14 LSB of full scale for AVIN 25V 175 Vei FROM OUTPUT PORTC FIGURE 16 Note 26 R2 49 5 R1 Note 27 Switches are LMC13334 CMOS analog switches Note 28 The 9 resistors used in the auto zero section can be 5 tolerance the ADC0801 It is important that the voltage levels that drive the auto zero resistors be constant Also for symmetry a logic s
30. brupt upside steps are always 1 LSB in magnitude Error Plot 1 LSB 1 LSB A 1 A 1 ANALOG INPUT Viy DS005671 82 Error Plot 1 LSB 33 4 LSB 1 2 LSB 1 1 ANALOG INPUT Viy DS005671 84 www national com S0800QV v08000V 08090V c0800Q0V L0800 QV ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Functional Description continued Transfer Function DIGITAL OUTPUT CODE A 1 A A 1 ANALOG INPUT Vj DS005671 85 Error Plot ERROR 1 1 ANALOG INPUT Viy DS005671 86 FIGURE 3 Clarifying the Error Specs of an A D Converter 12 LSB 2 0 FUNCTIONAL DESCRIPTION The ADCO0801 series contains a circuit equivalent of the 256R network Analog switches are sequenced by succes Sive approximation logic to match the analog difference input voltage Vi Vi to a corresponding tap on the R net work The most significant bit is tested first and after 8 com parisons 64 clock cycles a digital 8 bit binary code 1111 1111 full scale is transferred to an output latch and then an interrupt is asserted INTR makes a high to low transi tion Aconversion in process can be interrupted by issuing a second start command The device may be operated in the free running mode by connecting INTR to the WR input with CS 0 To ensure start up under all possible conditions an external WR pulse is required during the first power up cycle On the high
31. ckman Instruments 694 3 R10K resistor array uP Interfaced Temperature to Digital Converter 5 Vpc LM335 2 98V 25 C 10 mV K LM336 aN DS005671 72 Circuit values shown are for 0 lt lt 128 Can calibrate each sensor to allow easy replacement then A D can be calibrated with a pre set input voltage www national com 12 Typical Applications Continued Handling 5V Analog Inputs Beckman Instruments 694 3 R10K resistor array Interfaced Comparator with Hysteresis 05005671 35 Read Only Interface RD DATA IS STARTS NEW OUTPUT CONVERSION DS005671 34 DS005671 33 Protecting the Input DS005671 9 Diodes are 1N914 13 www national com S08090V r0s00 dv E0800dV 20800dV LO800 QV ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Typical Applications Continued Analog Self Test for a System SYSTEM CHANNEL DC TEST ANALDG POINTS MUX CD4051 C CHANNEL SELECT FROM OUTPUT PORT OF uP DS005671 36 A Low Cost 3 Decade Logarithmic Converter 10 mV gt Va gt 10VO O 10 DS005671 37 LM388 transistors A B C D LM324A quad op amp www national com 14 Typical Applications Continued 3 Decade Logarithmic A D Converter A B C D LM324A J 1 2 LM394 VIN E 10 mv TO 10V 1M LM336 ZERO ADJ 0 1 uF T DS005671 73 Noise Filtering the Analog Input Multiplexing
32. divider connected from Vcc to ground In all versions of the ADC0801 ADC0802 ADC0803 and ADCO805 in the ADCO804LCJ each resistor is typically 16 In all versions of the ADC0804 except the ADCO804LCJ each resistor is typically 2 2 Note 10 Human body model 100 pF discharged through a 1 5 kQ resistor Typical Performance Characteristics Logic Input Threshold Voltage vs Supply Voltage 18 5 T E 55 C lt Tq lt 125 C 1 5 e gt 3 15 15 ES 2 14 i 2 s 1 e S 4 50 4 15 5 00 5 25 5 50 Vec SUPPLY VOLTAGE DS005671 38 fci VS Clock Capacitor kHz 10 100 1000 CLOCK CAPACITOR pF DS005671 41 Output Current vs Temperature 8 5 Voc 7 z LL BATA DUTPUT E BUFFERS E 6 E SOURCE 5 5KITTTT NS 24 8 E g 4 E 5 e 3 MISINK 2 Vout 04 Voc 50 25 0 25 50 75 100 125 Ta AMBIENT TEMPERATURE C DS005671 44 Delay From Falling Edge of RD to Output Data Valid vs Load Capacitance 500 400 DELAY ns P 8 200 100 0 200 400 600 800 1000 LOAD CAPACITANCE pF DS005671 39 Full Scale Error vs Conversion Tim
33. e Tc 73 feuk LINEARITY ERROR LSBs 40 60 80 100 120 140 Tc CONVERSION TIME us DS005671 42 Power Supply Current vs Temperature Note 9 Ice POWER SUPPLY CURRENT 50 25 0 25 50 75 100 125 Ta AMBIENT TEMPERATURE C DS005671 45 CLK IN Schmitt Trip Levels vs Supply Voltage 3 5 31 27 23 CLK IN THRESHOLD VOLTAGE V 4 50 4 15 5 00 5 25 5 50 Vec SUPPLY VOLTAGE 08005671 40 Effect of Unadjusted Offset Error VS 2 Voltage 16 OV ASSUMES Vg 2 mV THIS SHOWS THE NEED FOR A ZERO ADJ IF OFFSET ERROR LSBs 0 01 0 1 1 0 5 Vnrr 2 DS005671 43 Linearity Error at Low Vrer 2 Voltages 1 0 ADCO801 2 Vger 2 256 ZERO AND FULL SCALE ADJUSTED I 1 LSB VALUE mV acie 1 22 4 88 aie 19 53 12 Bits OBITS 9 77 8 BITS 8 BITS V LSB LINEARITY ERROR LSBs e VREF 2 VOLTAGE 05005671 46 www national com s0800QV v08000V 08090V c0800QV L0800 QV ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 TRI STATE Test Circuits and Waveforms uu
34. e of Vage 2 should then be used for all the tests The digital output LED display can be decoded by dividing the 8 bits into 2 hex characters the 4 most significant MS and the 4 least significant LS Table 1 shows the fractional binary equivalent of these two 4 bit groups By adding the voltages obtained from the VMS and VLS columns in Table 1 the nominal value of the digital display when 2 2 560V can be determined For example for an output LED display of 1011 0110 or B6 in hex the voltage values from the table are 3 520 0 120 or 3 640 Vpc These voltage values represent the center values of a perfect A D converter The effects of quantization error have to be ac counted for in the interpretation of the test results 23 www national com s0800QV v08000V 08090V 708009Q0V L0800 QV ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Functional Description continued O 5 120 Vp 13k D GND 8 NSL5027 8 DS005671 18 FIGURE 9 Basic A D Tester For a higher speed test system or to obtain plotted data a digital to analog converter is needed for the test set up An accurate 10 bit DAC can serve as the precision voltage source for the A D Errors of the A D under test can be ex pressed as either analog voltages or differences in 2 digital words A basic A D tester that uses a DAC and provides the error as an analog output voltage is shown in Figure 8 The 2 op amps can be eliminated if
35. e points than 14 LSB In other words if we apply an analog input equal to the center value 14 LSB we guarantee that the A D will produce the correct digital code The maximum range of the position of the code transition is indicated by the horizontal arrow and it is guar anteed to be no more than 12 LSB The error curve of Figure 3 shows a worst case error plot for the ADC0802 Here we guarantee that if we apply an analog input equal to the LSB analog voltage center value the A D will produce the correct digital code Transfer Function DIGITAL OUTPUT CODE A 1 Ast ANALOG INPUT Vix DS005671 81 FIGURE 1 Clarifying the Error Specs of an A D Converter Accuracy 0 LSB A Perfect A D Transfer Function DIGITAL OUTPUT CODE A 1 A ANALOG INPUT DS005671 83 1 FIGURE 2 Clarifying the Error Specs of an A D Converter Accuracyzt A4 LSB Next to each transfer function is shown the corresponding error plot Many people may be more familiar with error plots than transfer functions The analog input voltage to the A D is provided by either a linear ramp or by the discrete output steps of a high resolution DAC Notice that the error is con tinuously displayed and includes the quantization uncertainty of the A D For example the error at point 1 of Figure 7 12 LSB because the digital code appeared 12 LSB in advance of the center value of the tread The error plots always have a constant negative slope and the a
36. east one of these signals returns high and the internal clocks again provide a reset signal for the start F F www national com Functional Description Continue SET 20 VREF O 9 LADDER SAR 2 AND LATCH DECODER NOTE 2 INTR F F 8 0 AGND gt Q Vcc age Q z Vin O gt 1 TRI STATE VIN OUTPUT LATCHES V Q MSB LSB 5 11 12 13 14 15 16 17 18 mur INTR CONV COMPT DIGITAL OUTPUTS COMPL a 1 TRI STATE CONTROL TS NOTE 1 O 1 OUTPUT ENABLE RDO Q RESET Note 13 CS shown twice for clarity Note 14 SAR Successive Approximation Register FIGURE 4 Block Diagram After the 1 is clocked through the 8 bit shift register which completes the SAR search it appears as the input to the D type latch LATCH 1 As soon as this 1 is output from the shift register the AND gate G2 causes the new digital word to transfer to the TRI STATE output latches When LATCH 1 is subsequently enabled the Q output makes a high to low transition which causes the INTR F F to set An inverting buffer then supplies the INTR input signal Note that this SET control of the INTR F F remains low for 8 of the external clock periods as the internal clocks run at of the frequency of the external clock If the data output is continuously enabled CS and RD both held low the INTR output will still signal the end of conversion by
37. erface of more converters In this configuration the converters are arbitrarily located at HEX address 5000 in the MC6800 memory space To save components the clock signal is derived from just one RC pair on the first converter This output drives the other A Ds All the converters are started simultaneously with a STORE instruction at HEX address 5000 Note that any other HEX address of the form 5XXX will be decoded by the circuit pull ing all the CS inputs low This can easily be avoided by using a more definitive address decoding scheme All the inter rupts are ORed together to insure that all A Ds have com pleted their conversion before the microprocessor is inter rupted The subroutine DATA IN may be called from anywhere in the user s program Once called this routine initializes the 0038 Upon IRQ low CPU FFF8 jumps to 0038 PIAORB Clear possible IRQ flags PIACRB PIAORB Set Port Bas input 7954 3D PIACRB Starts ADCO801 PIACRB Wait forinterrupt 1 020F Is final data stored ENDP TEMP1 CONVRT 1 PIAORB Read data in X StoreitatX 0200 Starting address for data storage 0200 Reinitialize 1 1 Return from subroutine 8006 To user s program 8007 DS005671 A2 CPU starts all the converters simultaneously and waits for the interrupt signal Upon receiving the interrupt it reads the converters from HEX addresses 5000 through 5007 and stores the data succe
38. gle mi croprocessor system a multiple converter scheme presents several advantages over the conventional multiplexer single converter approach With the ADC0801 series the dif ferential inputs allow individual span adjustment for each channel Furthermore all analog input channels are sensed simultaneously which essentially divides the microproces Sor s total system servicing time by the number of channels since all conversions occur simultaneously This scheme is shown in Figure 17 TRO 4 D R W 34 6 ABC O 5V 8 2 33 31 D1 32 29 D2 31 D3 30 04 29 32 05 28 30 D6 27 0 07 26 0 12 22 34 T A13 23 N A14 24 M lt L A15 25 33 VMA 5 F K DS005671 24 29 www national com S08090V r0s00 dv E0800dV Z0800dV LO800d0V ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 0010 0012 0015 0018 001B 001C 001D 001F 0022 0024 0027 0028 002A 002C 002E 0031 0033 0034 0036 0038 003B 003D 003 Functional Description continued SAMPLE PROGRAM FOR Figure 15 ADC0801 MC6800 CPU INTERFACE DF 36 CE 00 2C FF FF B7 50 00 DE 34 8C 02 OF 2714 B7 50 00 08 DF 34 20 FO DE 34 B6 50 00 A7 00 SB 02 00 00 00 CE 02 00 DF 34 DE 36 59 DATAIN CONVRT INTRPT TEMP1 TEMP2 ENDP STX LDX STX STAA CLI WAI LDX CPX BEQ STAA INX STX BRA LDX LDAA STAA RTI FDB FDB LDX
39. ically or with 5 2 5 or analog span adjusted voltage reference Key Specifications m Resolution 8 bits m Total error 14 LSB 14 LSB and 1 LSB m Conversion time 100 us Connection Diagram ADCO80X Dual In Line and Small Outline SO Packages 1 2 3 4 5 6 7 8 9 See Ordering Information Ordering Information DB7 MSB DS005671 30 TEMP RANGE 0 C TO 70 C 0 C TO 70 C 40 C TO 85 14 Bit Adjusted ADC0801LCN ERROR 12 Bit Unadjusted ADC0802LCWM ADC0802LCN 16 Bit Adjusted ADCO0803LCN 1Bit Unadjusted ADC0804LCWM ADC0804LCN ADCO0805LCN ADCO0804LCJ PACKAGE OUTLINE M20B Small N20A Molded DIP Outline TRI STATE is a registered trademark of National Semiconductor Corp Z 80 is a registered trademark of Zilog Corp 1999 National Semiconductor Corporation DS005671 www national com S19149Au02 C V eiqneduio dri 18 9 s08000V r08000V 08009QV 20800aV L0800Q0V ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Typical Applications TRANSDUCER 8 BIT RESOLUTION OVER ANY DESIRED SEE SECTION 2 4 1 SPAN ADJ O SEE SECTION 241 05005671 1 NSC800 8080 280 8048 ETC DS005671 31 Error Specification Includes Full Scale Zero Error and Non Linearity Part Full Vrer 2 2 500 Voc Vrer 2 No Connection Number Scale No Adjustments No Adjustments Adjusted ADCO0801 14 LSB ADC0802 1
40. ices are addressed at HX ADDR 4XXX or 5XXX The following subroutine performs essentially the same func tion as in the case of the 8080A interface and it can be called from anywhere in the user s program In Figure 16 the ADC0801 series is interfaced to the M6800 microprocessor through the arbitrarily chosen Port B of the MC6820 or MC6821 Peripheral Interface Adapter PIA Here the CS pin of the A D is grounded since the PIA is al Note 20 Numbers in parentheses refer to MC6800 CPU pin out Note 21 Number or letters in brackets refer to standard M6800 system common bus code FIGURE 15 ADC0801 MC6800 CPU Interface ready memory mapped in the M6800 system and no CS de coding is necessary Also notice that the A D output data lines are connected to the microprocessor bus under pro gram control through the PIA and therefore the A D RD pin can be grounded Asample interface program equivalent to the previous one is shown below Figure 16 The PIA Data and Control Registers of Port B are located at HEX addresses 8006 and 8007 re spectively 5 0 GENERAL APPLICATIONS The following applications show some interesting uses for the A D The fact that one particular microprocessor is used is not meant to be restrictive Each of these application cir cuits would have its counterpart using any microprocessor that is desired 5 1 Multiple ADC0801 Series to MC6800 CPU Interface To transfer analog data from several channels to a sin
41. istance and the use of an input bypass capacitor This error can be eliminated by doing a full scale adjustment of the A D adjust Vae 2 for a proper full scale reading see section 2 5 2 on Full Scale Adjustment with the source resistance and input bypass capacitor in place 2 4 Reference Voltage 2 4 1 Span Adjust For maximum applications flexibility these A Ds have been designed to accommodate 5 Vpc 2 5 or an adjusted voltage reference This has been achieved in the design of the IC as shown in Figure 6 Vec Ver Q DIGITAL CIRCUITS DS005671 15 FIGURE 6 The Vpererence Design on the IC Notice that the reference voltage for the IC is either 1 of the voltage applied to the Vec supply pin or is equal to the volt age that is externally forced at the Vagr 2 pin This allows for a ratiometric voltage reference using the Voc supply a 5 reference voltage can be used for the Vec supply or a voltage less than 2 5 can be applied to the Vage 2 input for increased application flexibility The internal gain to the Vrer 2 input is 2 making the full scale differential input volt age twice the voltage at pin 9 An example of the use of an adjusted reference voltage is to accommodate a reduced span or dynamic voltage range of the analog input voltage If the analog input voltage were to range from 0 5 to 3 5 instead of OV to 5 the span would be 3V as shown in Figure 7 With 0 5 Vpc ap
42. ix or Viy pin ex ceeds the allowed operating range of Vo 54 50 mV large in put currents can flow through a parasitic diode to the Vec pin If these currents can exceed the 1 mA max allowed Spec an external diode 1N914 should be added to bypass this current to the Vcc pin with the current bypassed with this diode the voltage at the Vin pin can exceed the Vec voltage by the forward voltage of this diode 2 3 2 Input Bypass Capacitors Bypass capacitors at the inputs will average these charges and cause a DC current to flow through the output resis tances of the analog signal sources This charge pumping action is worse for continuous conversions with the Vin in put voltage at full scale For continuous conversions with a 640 kHz clock frequency with the Viy input at 5V this DC current is at a maximum of approximately 5 pA Therefore bypass capacitors should not be used at the analog inputs or the Vagp 2 pin for high resistance sources gt 1 If input bypass capacitors are necessary for noise filtering and high Source resistance is desirable to minimize capacitor size the detrimental effects of the voltage drop across this input resis tance which is due to the average value of the input current can be eliminated with a full scale adjustment while the given source resistor and input bypass capacitor are both in place This is possible because the average value of the in put current is a precise linear function of
43. low CPU clock frequency more time is available in which to establish proper logic levels on the bus and there fore higher capacitive loads can be driven see typical char acteristics curves At higher CPU clock frequencies time can be extended for I O reads and or writes by inserting wait states 8080 or using clock extending circuits 6800 Finally if time is short and capacitive loading is high external bus drivers must be used These can be TRI STATE buffers low power Schottky such as the DM74LS240 series is rec ommended or special higher drive current products which are designed as bus drivers High current bipolar bus drivers with PNP inputs are recommended 2 10 Power Supplies Noise spikes on the Vec supply line can cause conversion errors as the comparator will respond to this noise A low in ductance tantalum filter capacitor should be used close to the converter Vcc pin and values of 1 uF or greater are rec ommended If an unregulated voltage is available in the sys tem a separate LM340LAZ 5 0 TO 92 5V voltage regulator for the converter and other analog circuitry will greatly re duce digital noise on the Vcc supply 2 11 Wiring and Hook Up Precautions Standard digital wire wrap sockets are not satisfactory for breadboarding this A D converter Sockets on PC boards can be used and all logic signal wires and leads should be grouped and kept as far away as possible from the analog signal leads Exposed leads
44. ng a 640 kHz A D clock fc would allow a peak value of the common mode voltage Vp which is given by Vo AVe MAx fcLio P 221 fom 4 5 or _ 5 x 10 3 640 103 6 28 60 4 5 which gives Vp 1 9V The allowed range of analog input voltages usually places more severe restrictions on input common mode noise lev els An analog input voltage with a reduced span and a relatively large zero offset can be handled easily by making use of the differential input see section 2 4 Reference Voltage 2 3 Analog Inputs 2 3 1 Input Current Normal Mode Due to the internal switching action displacement currents will flow at the analog inputs This is due to on chip stray ca pacitance to ground as shown in Figure 5 PEAK 60 ns TIME 6 VA 5 ANY Viu l of SW 1 and SW2 5 Cstray 5 x 12 pF 60 ns FIGURE 5 Analog Input Impedance 05005671 14 The voltage on this capacitance is switched and will result in currents entering the Vi input pin and leaving the Vn input which will depend on the analog differential input volt age levels These current transients occur at the leading edge of the internal clocks They rapidly decay and do not cause errors as the on chip comparator is strobed at the end of the clock period Fault Mode If the voltage source applied to the V
45. og Input from 0 5V Digital Out 00 x to 3 5V Digital Out FF ex FIGURE 7 Adapting the A D Analog Input Voltages to Match an Arbitrary Input Signal Range is applied to pin 6 and the zero reference voltage at pin 7 should then be adjusted to just obtain the 0 to 1 code transition The full scale adjustment should then be made with the proper Vn voltage applied by forcing a voltage to the Vin input which is given by Cmax Yun Vin fs adj Vmax 1 5 256 where Vmax The high end of the analog input range and Vuin the low end the offset zero of the analog range Both are ground referenced The 2 or Voc voltage is then adjusted to provide a code change from FEpex to FFyex This completes the ad justment procedure 2 6 Clocking Option The clock for the A D can be derived from the CPU clock or an external RC can be added to provide self clocking The CLK IN pin 4 makes use of a Schmitt trigger as shown in Figure 8 www national com 22 Functional Description continued 05005671 17 1 fc k R86 R 10 kQ FIGURE 8 Self Clocking the A D Heavy capacitive or DC loading of the clock R pin should be avoided as this will disturo normal converter operation Loads less than 50 pF such as driving up to 7 A D converter clock inputs from a single clock R pin of 1 converter are al lowed For larger clock line loading a CMOS or low power TTL buffer or PNP input logic
46. or Derivatives 8048 8085 This converter has been designed to directly interface with derivatives of the 8080 microprocessor The A D can be mapped into memory space using standard memory ad dress decoding for CS and the MEMR and MEMW strobes or it can be controlled as an I O device by using the I O R and I O W strobes and decoding the address bits AO A7 or address bits 8 A15 as they will contain the same 8 bit address information to obtain the CS input Using the I O space provides 256 additional addresses and may allow a simpler 8 bit address decoder but the data can only be input to the accumulator To make use of the additional memory reference instructions the A D should be mapped into memory space An example of an A D in I O space is shown in Figure 12 www national com 24 Functional Description continued DAC1000 10 BIT DAC 8 BIT A D UNDER TEST VANALOG OUTPUT ANALOG INPUT VOLTAGE 100X ANALOG ERROR VOLTAGE 05005671 89 FIGURE 10 A D Tester with Analog Error Output DAC1000 10 BIT DAC DIGITAL OUTPUT Amt NDER 05005671 90 FIGURE 11 Basic Digital A D Tester TABLE 1 DECODING THE DIGITAL OUTPUT LEDs OUTPUT VOLTAGE FRACTIONAL BINARY VALUE FOR CENTER VALUES HEX BINARY WITH Vngr 272 560 Voc MS GROUP LS GROUP VMS VLS GROUP GROUP Note 15 Note 15 F 1 1 1 1 15 16 15 256 4 800 0 300 E 1 1 1 0 7 8 7 128 4 48
47. or system error is the input offset voltage of the amplifiers used for the preamp Figure 18 is a gain of 100 differential preamp whose offset voltage errors will be cancelled by a zeroing subroutine which is performed by the INS8080A microprocessor sys tem The total allowable input offset voltage error for this preamp is only 50 uV for 1 4 LSB error This would obviously require very precise amplifiers The expression for the differ ential output voltage of the preamp is 2R2 Vo Vin Vin P SIGNAL GAIN 2R2 Vos Vos Voss IxRx 1 p DC ERROR TERM where lx is the current through resistor Rx All of the offset error terms can be cancelled by making IlxRx Vos Voss Vosa This is the principle of this auto zeroing scheme The INS8080A uses the 3 I O ports of an INS8255 Program able Peripheral Interface PPI to control the auto zeroing and input data from the ADC0801 as shown in Figure 19 The PPI is programmed for basic I O operation mode 0 with Port A being an input port and Ports B and C being output ports Two bits of Port C are used to alternately open or close the 2 switches at the input of the preamp Switch SW1 is closed to force the preamp s differential input to be zero dur ing the zeroing subroutine and then opened and SW2 is then closed for conversion of the actual differential input signal Using 2 switches in this manner eliminates concern for the ON resist
48. outine will read a peripheral status word from the DM74LS373 which contains the logic state of the INTR out puts of all the converters Each converter which initiates an interrupt will place a logic 0 in a unique bit position in the status word and the subroutine will determine the identity of the converter and execute a data read An identifier word which indicates which A D the data came from is stored in the next sequential memory location above the location of the data so the program can keep track of the identity of the data entered 35 www national com SO8090V P0s00 dv E0800dV 2Z0800dV LO800 QV ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Functional Description continued START ZEROING SUBROUTINE CLOSE SWi OPEN SW2 INITIALIZE SAR BIT POINTER REG B X 80 INITIALIZE SAR CODE IN REG C REG X 7F OUTPUT FIRST SAR CODE PORT B X 80 START A D AND READ DATA OR REG B WITH REG CLEAR BIT IN PORT B WHEN REAPPLIED SHIFT 1 IN REG B RIGHT TO POINT TO NEXT BIT OPEN SW1 IS REG B CLOSE SW2 ZERO PREAMP IS ZEROED AND PROPER INPUT CONVERSIONS CAN BE DONE EXCLUSIVE OR REG B WITH REG C TO SET NEXT BIT IN PORT B OUTPUT NEW SAR CODE TO PORT B DS005671 28 FIGURE 20 Flow Chart for Auto Zero Routine www national com 36 Functional Description continued 5000 3E90 MVI 90 53002 D3E7 Out Control Port Program PPI 300
49. puts near full scale The spec allows 50 mV forward bias of either diode This means that as long as the analog Vy does not exceed the supply voltage by more than 50 mV the output code will be correct To achieve an absolute 0 Vpc to 5 Vpc input voltage range will therefore require a minimum supply voltage of 4 950 over temperature variations initial tolerance and loading Note 5 Accuracy is guaranteed at 640 kHz At higher clock frequencies accuracy can degrade For lower clock frequencies the duty cycle limits can be ex tended so long as the minimum clock high time interval or minimum clock low time interval is no less than 275 ns Note 6 With an asynchronous start pulse up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process The start request is internally latched see Figure 4 and section 2 0 www national com 4 AC Electrical Characteristics continued Note 7 The CS input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width An arbitrarily wide pulse width will hold the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse see timing diagrams Note 8 None of these A Ds requires a zero adjust see section 2 5 1 To obtain zero code at other analog input voltages see section 2 5 and Figure 7 Note 9 The Vngr 2 pin is the center point of a two resistor
50. should be used to minimize the loading on the clock R pin do not use a standard TTL buffer 2 7 Restart During a Conversion If the A D is restarted CS and WR go low and return high during a conversion the converter is reset and a new con version is started The output data latch is not updated if the conversion in process is not allowed to be completed there fore the data of the previous conversion remains in this latch The INTR output simply remains at the 1 level 2 8 Continuous Conversions For operation in the free running mode an initializing pulse should be used following power up to ensure circuit opera tion In this application the CS input is grounded and the WR input is tied to the INTR output This WR and INTR node should be momentarily forced to logic low following a power up cycle to guarantee operation 2 9 Driving the Data Bus This MOS A D like MOS microprocessors and memories will require a bus driver when the total capacitance of the data bus gets large Other circuitry which is tied to the data bus will add to the total capacitive loading even in TRI STATE high impedance mode Backplane bussing also greatly adds to the stray capacitance of the data bus There are some alternatives available to the designer to handle this problem Basically the capacitive loading of the data bus slows down the response time even though DC specifications are still met For systems operating with a relatively s
51. ssively at arbitrarily chosen HEX ad dresses 0200 to 0207 before returning to the user s pro gram All CPU registers then recover the original data they had before servicing DATA IN 5 2 Auto Zeroed Differential Transducer Amplifier and A D Converter The differential inputs of the ADC0801 series eliminate the need to perform a differential to single ended conversion for a differential transducer Thus one op amp can be elimi nated since the differential to single ended conversion is pro vided by the differential input of the ADC0801 series In gen eral a transducer preamp is required to take advantage of the full A D converter input dynamic range 31 www national com s0800QV v08000V 08090V c0800QV L0800 QV ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Functional Description continued R W 1 DATA BUS 00 33 31 D1 32 29 02 31 K 03 30 D4 29 32 05 28 30 27 T 07 26 J A2 11 U A1 10 0 9 40 al 4 D WXY el 414243 5 A12 22 34 13 23 N AM 24 M c A15 25 33 DS005671 26 Note 23 Numbers in parentheses refer to MC6800 CPU pin out Note 24 Numbers of letters in brackets refer to standard M6800 system common bus code FIGURE 17 Interfacing Multiple A Ds in an MC6800 System www national com 32 Functional Description continued SAMPLE PROGRAM FOR Figure 17 IN
52. to low transition of the WR input the internal SAR latches and the shift register stages are reset As long as the CS input and WR input remain low the A D will remain in a reset state Conversion will start from 1 to 8 clock peri ods after at least one of these inputs makes a low to high transition A functional diagram of the A D converter is shown in Figure 4 All of the package pinouts are shown and the major logic control paths are drawn in heavier weight lines The converter is started by having CS and WR simulta neously low This sets the start flip flop F F and the result ing 1 level resets the 8 bit shift register resets the Interrupt INTR F F and inputs a 1 to the D flop F F1 which is at the input end of the 8 bit shift register Internal clock signals then transfer this 1 to the output of F F1 The AND gate G1 combines this 1 output with a clock signal to provide a reset signal to the start F F If the set signal is no longer present either WR or CS is a 1 the start F F is reset and the 8 bit shift register then can have the 1 clocked in which starts the conversion process If the set signal were to still be present this reset pulse would have no effect both outputs of the start F F would momentarily be at a 1 level and the 8 bit shift register would continue to be held in the reset mode This logic therefore allows for wide CS and WR sig nals and the converter will start after at l
53. to the analog inputs can cause undesired digital noise and hum pickup therefore shielded leads may be necessary in many applications A single point analog ground that is separate from the logic ground points should be used The power supply bypass ca pacitor and the self clocking capacitor if used should both be returned to digital ground Any Vre 2 bypass capacitors analog input filter capacitors or input signal shielding should be returned to the analog ground point A test for proper grounding is to measure the zero error of the A D converter Zero errors in excess of 14 LSB can usually be traced to im proper board layout and wiring see section 2 5 1 for mea suring the zero error 3 0 TESTING THE A D CONVERTER There are many degrees of complexity associated with test ing an A D converter One of the simplest tests is to apply a known analog input voltage to the converter and use LEDs to display the resulting digital output code as shown in Figure 9 For ease of testing the 2 pin 9 should be supplied with 2 560 and a Vec supply voltage of 5 12 should be used This provides an LSB value of 20 mV If a full scale adjustment is to be made an analog input volt age of 5 090 Vpc 5 120 1 LSB should be applied to the Vin pin with the Viy pin grounded The value of the Vrer 2 input voltage should then be adjusted until the digital output code is just changing from 1111 1110 to 1111 1111 This valu
54. unctional Description continued 1NS8048 ANALOG INPUT 0 0801 CLKR CLK IN AGND DGND DS005671 21 FIGURE 13 INS8048 Interface SAMPLE PROGRAM FOR Figure 13 INS8048 INTERFACE 0410 JMP ORG 04 50 JMP ORG 99 FE ANL 81 MOVX 89 01 START ORL B8 20 MOV B9 FF MOV BA 10 MOV 23 FF AGAIN MOV 99 FE ANL 91 MOVX 05 EN 96 21 LOOP JNZ EA 1B DJNZ 00 NOP 00 NOP ORG 81 INDATA MOVX AO MOV 18 INC 8901 ORL 27 CLR 93 RETR 4 2 Interfacing the Z 80 The 2 80 control bus is slightly different from that of the 8080 General RD and WR strobes are provided and sepa rate memory request MREQ and I O request IORQ sig nals are used which have to be combined with the general ized strobes to provide the equivalent 8080 signals An advantage of operating the A D in I O space with the Z 80 is that the CPU will automatically insert one wait state the RD and WR strobes are extended one clock period to allow more time for the I O devices to respond Logic to map the A D in I O space is shown in Figure 14 10H Program starts at addr 10 3H 50H Interrupt jump vector 10H Main program Pl 0FEH Chip select A R1L Read inthe lst data toreset the intr Pl 1 Set port pinhigh RO 20H Data address Rl 0FFH Dummy address R2 10H Counter for 16 bytes A 0FFH Set ACC for intr loop Pl 0FEH Send CS bit 0 of Pl R1 A Send WR out I Enable interrupt LOOP
55. utilizes the differential mode operation of the A D The zero error of the A D converter relates to the location of the first riser of the transfer function and can be measured by grounding the Vix input and applying a small magnitude positive voltage to the Vi input Zero error is the differ ence between the actual DC input voltage that is necessary to just cause an output digital code transition from 0000 0000 to 0000 0001 and the ideal 12 LSB value 12 LSB 9 8 mV for Vnge 272 500 2 5 2 Full Scale The full scale adjustment can be made by applying a differ ential input voltage that is 112 LSB less than the desired ana log full scale voltage range and then adjusting the magni tude of the Vage 2 input pin 9 or the Vcc supply if pin 9 is not used for a digital output code that is just changing from 1111 1110 to 1111 1111 2 5 3 Adjusting for an Arbitrary Analog Input Voltage Range If the analog zero voltage of the A D is shifted away from ground for example to accommodate an analog input signal that does not go to ground this new zero reference should be properly adjusted first A Vin voltage that equals this desired zero reference plus 12 LSB where the LSB is calcu lated for the desired analog span 1 LSB analog span 256 SPAN 2 0 5 Voc 1 2 LM358 ZERO SHIFT R ADJ ADJ DS005671 88 Add if Vagg 2 lt 1 with LM358 to draw to ground b Accommodating an Anal
56. ven in Figure 21 All addresses used are compatible with the BLC 80 10 microcomputer system In particular Port A and the ADC0801 are at port address E4 Port B is at port address E5 Port C is at port address E6 PPI control word port is at port address E7 Program Counter automatically goes to ADDR 3C3D upon acknowledgement of an interrupt from the ADC0801 5 3 Multiple A D Converters in a Z 80 Interrupt Driven Mode In data acquisition systems where more than one A D con verter or other peripheral device will be interrupting pro gram execution of a microprocessor there is obviously a 8080A CONTROL SIGNALS DM8131 OUTPUT VOUTI OUTPUTS v pg VREF 2 DS005671 92 need for the CPU to determine which device requires servic ing Figure 22 and the accompanying software is a method of determining which of 7 ADC0801 converters has com pleted a conversion INTR asserted and is requesting an in terrupt This circuit allows starting the A D converters in any sequence but will input and store valid data from the con verters with a priority sequence of A D 1 being read first A D 2 second etc through A D 7 which would have the lowest priority for data being read Only the converters whose INT is asserted will be read The key to decoding circuitry is the DM74LS373 8 bit D type flip flop When the Z 80 acknowledges the interrupt the pro gram is vectored to a data input Z 80 subroutine This sub r
57. wing of OV to 5V is convenient To achieve this a CMOS buffer is used for the logic output signals of Port B and this CMOS package is powered with a stable 5V source Buffer amplifier A1 is necessary so that it can source or sink the D A output current 5Vpc FROM OUTPUT 390k PORT B BUFFER ag FIGURE 16 sw3 1207 O fs 156M ar 1k 316M DS005671 91 FIGURE 18 Gain of 100 Differential Transducer Preamp www national com 34 Functional Description continued INVERTING ADDRESS BUFFERS 8080A ADDRESS BUS PORTA PORTA BUFFERS INS8202 8080A DATA BUS FIGURE 19 Microprocessor Interface Circuitry for Differential Preamp A flow chart for the zeroing subroutine is shown in Figure 20 It must be noted that the ADC0801 series will output an all zero code when it converts a negative input Vi Vin Also a logic inversion exists as all of the I O ports are buff ered with inverting gates Basically if the data read is zero the differential output volt age is negative so a bit in Port B is cleared to pull Vx more negative which will make the output more positive for the next conversion If the data read is not zero the output volt age is positive so a bit in Port B is set make Vx more posi tive and the output more negative This continues for 8 ap proximations the differential output eventually converges to within 5 mV of zero The actual program is gi
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