National semiconductor ADC08031/ADC08032/ADC08034/ADC08038 8-Bit High-Speed Serial I/O A/D Converters with Multiplexer Options Voltage Reference Track/Hold Function handbook
Contents
1. June 2000 National Semiconductor ADC08031 ADC08032 ADC08034 ADC08038 8 Bit High Speed Serial I O A D Converters with Multiplexer Options Voltage Reference and Track Hold Function General Description Test systems Embedded diagnostics The ADC08031 ADC08032 ADC08034 ADC08038 are 8 bit ii successive approximation A D converters with serial I O and configurable input multiplexers with up to 8 channels The Features serial I O is configured to comply with the NSC MICROW Serial digital data link requires few I O pins IRE serial data exchange standard for easy interface tothe Analog input track hold function COPS family of controllers and can easily interface with 2 4 or 8 channel input multiplexer options with standard shift registers or microprocessors address logic The ADC08034 and ADC08038 provide 2 6V band gap de m OV to 5V analog input range with single 5V power rived reference For devices offering guaranteed voltage ref supply erence performance over temperature see ADCO8131 ADC08134 ADC08138 A track hold function allows the analog voltage at the positive input to vary during the actual A D conversion The analog inputs can be configured to operate in various combinations of single ended differential or pseudo differential modes In addition input voltage spans Key Specifications as small as 1V can be accommodated i m Resolution 8 bits i i m Conversion ti2. SAR STATUS SARS TRI STATE MSB FIRST DATA lt LSB FIRST DATA DATA OUT 00 TRI STATE 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 MSB LSB MSB DS010555 15 www national com 8 ADC08031 ADC08032 ADC08034 ADC08038 lagrams Continued ing D iming I 91 SssoL0sd asn 31915 141 v1vd 31 15 141 3115 1941 TTT TTL 29 INIL 901VNV 9 Sc USYE SI 3S 957 u Sxoor gL eins exei asn 15414 8S1 Ir Q13H PC lt N 1VG 15414 8SN 40 135 SSW gt L 9 S VIVO 15313 951 N 94 N1V 1544 8SN as1 0 r S 9 L 851 GSW SS4490 d NI NOISH3ANOO Q V v1vd LNdino 91 Sh 1203135 1 15 141 N9IS 000 SSINGGV 41 135 gt 0 6 8 L c 210 195 1149410 15414 851 1081 02 01 35 35 oNISn 0d 1no viva 404 3S SUVS 511 15 YVS 19 NI VLVG 59 193135 210 32012 www national com ADC08031 ADC08032 ADC08034 ADC08038 ADC08038 Functional Block Diagram O SARS 13 14 15 Clock Generator ampled Data Comparator so ini D 3 wo g 2 o a 5 2 x 2 2 52 AN O 2
3. To understand the operation of these converters it is best to refer to the Timing Diagrams and Functional Block Diagram and to follow a complete conversion sequence For clarity a separate timing diagram is shown for each device 1 Aconversion is initiated by pulling the CS chip select line low This line must be held low for the entire conver sion The converter is now waiting for a start bit and its MUX assignment word 2 Oneach rising edge of the clock the status of the data in DI line is clocked into the MUX address shift register The start bit is the first logic 1 that appears on this line all leading zeros are ignored Following the start bit the converter expects the next 2 to 4 bits to be the MUX as signment word Functional Description continued 3 When the start bit has been shifted into the start location of the MUX register the input channel has been as signed and a conversion is about to begin An interval of 1 clock period where nothing happens is automatically inserted to allow the selected MUX channel to settle The SARS line goes high at this time to signal that a con version is now in progress and the DI line is disabled it no longer accepts data The data out DO line now comes out of TRI STATE and provides a leading zero for this one clock period of MUX settling time During the conversion the output of the SAR comparator indicates whether the analog input is greater than high or l
4. Ve 5 3 T 25 C 4 2 0 25 t 0 25 m E E Veer 5 0V 5 a a 0 00 i 0 00 r r A 0 1 2 3 4 5 100 50 50 100 150 0 250 500 750 1000 1250 1500 1750 REFERENCE VOLTAGE V TEMPERATURE 9C CLOCK FREQUENCY kHz DS010555 32 DS010555 33 05010555 34 Power Supply Current vs Output Current vs Power Supply Current Temperature ADC08038 Temperature vs Clock Frequency ADC08034 ADC08031 35 T 2 5 30 lt lt 2 0 20 25 Z z x 1 5 amp 15 20 o e B 1 0 79 3 5 E source Voc E B 05 ac 10 05 2 5 i r r 0 0 1 0 0 r r r r 100 50 0 50 100 150 0 250 500 750 1000 1250 1500 1750 100 50 0 50 100 150 TEMPERATURE C CLOCK FREQUENCY kHz TEMPERATURE C D5010555 96 DS010555 37 DS010555 35 Note For ADC08032 add IREF 5 www national com 8 0800QV r 0800Q0V c 0800QV I 0800QV ADC08031 ADC08032 ADC08034 ADC08038 Leakage Current Test Circuit OFF CHANNEL CHANNELS VOLTAGE SE DS010555 7 TRI STATE Test Circuits and Waveforms tu Vcc cs DATA OUTPUT C R DO AND SARS OUTPUTS DS010555 38 DS010555 39 t 65 R Cs DATA OUTPUT DO AND C SARS OUTPUTS VoL DS010555 41 DS010555 40 Timing Diagrams Data Input Timing CLK DATA IN DI 08010555 10 reset these devices CLK and CS must be
5. tors should not be used if the source resistance is greater than 1kO The worst case leakage current of 1 over tem perature will create a 1mV input error with a 1KO source re sistance An op amp RC active low pass filter can provide both impedance buffering and noise filtering should a high impedance signal source be required 5 0 OPTIONAL ADJUSTMENTS 5 1 Zero Error The zero of the A D does not require adjustment If the mini mum analog input voltage value is not ground a zero offset can be done The converter can be made to out Functional Description continued put 0000 0000 digital code for this minimum input voltage by biasing any Vn input at this Vinov value This utilizes the differential mode operation of the A D The zero error of the A D converter relates to the location of the first riser of the transfer function and can be measured by grounding the input and applying a small magnitude positive voltage to the input Zero error is the differ ence between the actual DC input voltage which is neces sary to just cause an output digital code transition from 0000 0000 to 0000 0001 and the ideal 12 LSB value 12 LSB 9 8mV for 5 000 5 2 Full Scale The full scale adjustment can be made by applying a differ ential input voltage which is 11 LSB down from the desired analog full scale voltage range and then adjusting the mag nitude of the VggelN input or Vec for th
6. 1 270 OP 0 356 0 508 TYP ALL LEADS TYP ALL LEADS y 0 008 0 203 M20B REV P Order Number ADC08038CIWM NS Package Number M20B 0 373 0 400 9 474 10 16 0 090 2 286 0 092 DIA 0 032 0 005 2 337 0 813 0 127 0 250 0 005 RAD 6 35 0 127 PIN NO 1 V mua U OPTION 1 2 280 0 040 7 112 0090 1016 ne OPTION 2 0 300 0 320 0 762 0 145 0 200 7 62 8 128 20 17 39 3 683 5 080 0 009 0 015 0 229 0 381 0 125 0 140 95 5 3 175 3 556 90 4 TYP dd 0 018 0 003 I 0 457 0 076 2255 1116 5 0 100 0 010 8 255 0 381 2 540 0 254 0 045 0 015 Lac 1 143 0 381 0 060 0 050 1 524 1 270 Order Number ADC08031CIN NS Package Number NO8E 23 0 020 0 508 MIN REV www national com 8608020 7608020 2208020 1808002 0 092 X 0 030 2 337 X 0 762 Multiplexer Options Voltage Reference and Track Hold Function LIFE SUPPORT POLICY 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Nationa
7. Differential Bits min Linearity Reference Input Resistance Note 11 max Total Unadjusted Error BIN BIWM Vin Analog Input Voltage Note 12 Vcc 0 05 V max Common Mode Error Common Mode Error A LSB Power Po Common TE Sensitivity AL 5V 5 LSB max On Channel Leakage On Channel 5V 0 2 uA max Current Note 13 Off Channel LU On Channel 0 2 max Off Channel BEEN Off Channel Leakage On Channel 0 2 max Current Note 13 Off Channel EE 1 On Channel 0 2 max DIGITAL AND DC CHARACTERISTICS Vas Logical I mutVolage vm Vo Logical 0 Input Votage Moos 47V Vimao ko Logical O input Current Vs M ma Vout 1 Logical 1 Output Voltage Voc 4 75V lour 360 pA V min V min Logical 0 Output Voc 4 75V lout 1 6 mA 3 www national com ADC08031 ADC08032 ADC08034 ADC08038 Electrical Characteristics Continued The following specifications apply for Vec Vrer 5 and 1 MHz unless otherwise specified Boldface limits apply for T4 Ty Tmn to Tmax all other limits T4 T 25 C Symbol Parameter Conditions Typical Limits Units Note 8 Note 9 Limits DIGITAL AND DC CHARACTERISTICS TRI STATE Output Current Vout OV max ouput Source Current vorz mm Output Sink Curent
8. SYSTEM TEST qp POINTS TO CONTROLLER 00 ADC08031 c A C DI COM AGND Vin 3 DS010555 26 DO all 1s if VN gt Vin DS010555 25 DO all 0s if ViN lt Diodes are 1N914 Digital Load Cell 330 ADC08031 STRAIN GAUGE LOAD CELL 3000 30 mV F S 10k OFFSET 20k DS010555 27 Uses one more wire than load cell itself Two mini DIPs could be mounted inside load cell for digital output transducer Electronic offset and gain trims relax mechanical specs for gauge factor and offset Low level cell output is converted immediately for high noise immunity 19 www national com 8 0800QV r 0800Q0V c 0800QV He60800QV ADC08031 ADC08032 ADC08034 ADC08038 Applications Continued 4 mA 20 mA Current Loop Converter INP Voc CD4024 Vo5 ADC08031 CS LM385 2 5V IN 6N139 COUPLER Vcc LM385 2 5V y Vo GND DS010555 28 All power supplied by loop 1500V isolation at output www national com 20 Applications Continued Isolated Data Converter TRANSFORMER TRW TC SS0 32 Vcc OUT 10k 2N2222 1N4148 CLK ADC08038 CS 2N2222 8 ANALOG CHANNELS DO DGND AGND D 6N139 HIGH GAIN OPTOCOUPLER DS010555 29 No power required remotely e 1500V isolation 21 www national com 8 0800QV r 0800Q0V c 0800QV HE0800QV ADC08031 ADC08032 ADC08034 ADC08038 Physical Dimensions inches mil
9. The guaranteed specifications apply only for the test conditions listed Some performance character istics may degrade when the device is not operated under the listed test conditions Note 3 All voltages are measured with respect to AGND 0 unless otherwise specified Note 4 When the input voltage Vij at any pin exceeds the power supplies lt AGND or Vin gt Vcc the current at that pin should be limited to 5 mA The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four pins Note 5 The maximum power dissipation must be derated at elevated temperatures and is dictated by T jMAx and the ambient temperature Ta The maximum allowable power dissipation at any temperature is Pp TA 8jA or the number given in the Absolute Maximum Ratings whichever is lower For these de www national com 4 Electrical Characteristics continued vices 125 C The typical thermal resistances of these parts when board mounted follow ADC08031 and 08032 with BIN and CIN suffixes 120 C W ADC08038 with CIN suffix 80 C W ADC08031 with CIWM suffix 140 C W ADC08032 140 C W ADC08034 140 C W ADC08038 with CIWM suffix 91 C W Note 6 Human body model 100 pF capacitor discharged through a 1 5 kQ resistor Note 7 See AN450 Surface Mounting Methods and Their Effect on Produc
10. Vour Veo 80 mm Supply Current ADC08031 ADC08034 CS HIGH 3 0 mA max and ADC08038 ADC08032 Note 16 7 0 mA max REFERENCE CHARACTERISTICS VrerOUT Nominal Reference Output VrerOUT Option Available Only on V ADC08034 and ADC08038 Electrical Characteristics The following specifications apply for Vec 5 and t t 20 ns unless otherwise specified Boldface limits apply for T Ty Tmn to Tmax all other limits T4 T 25 T T 25 C Symbol Parameter Conditions Typical Limits Units Clock Frequency 10 kHz min Clock Duty Cycle 40 min Tc Conversion Time Not Including fork 1 MHz 8 1 fGLK max teenie CS Falling Edge or Data Input ns min Valid to CLK Rising Edge Data Input Valid after CLK Rising Edge loat CLK Falling Edge to Output C 100 pF Data Valid Note 15 Data MSB First ns max Data LSB First ns max ns min tr TRI STATE Delay from Rising Edge ns of CS to Data Output and SARS Hi Z ns max pF pF C 100 pF 2kQ Gu Capacitance oflogcinpus Cour Capacitance oftogicOuputs 8 Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Note 2 Operating Ratings indicate conditions for which the device is functional These ratings do not guarantee specific performance limits For guaranteed speci fications and test conditions see the Electrical Characteristics
11. 08032 Small Outline Package DS010555 30 Absolute Maximum Ratings Notes 1 3 If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage Vcc 6 5V Voltage at Inputs and Outputs 0 3V to Vec 0 3V Input Current at Any Pin Note 4 5 mA Package Input Current Note 4 20 mA Power Dissipation at T4 25 C Note 5 800 mW ESD Susceptibility Note 6 1500V Soldering Information N Package 10 sec 235 C SO Package Vapor Phase 60 sec 215 C Infrared 15 sec Note 7 220 C Storage Temperature Operating Ratings notes 2 3 Temperature Range ADC08031BIN ADC08031CIN ADCO08032BIN ADC08032CIN ADCO08034BIN ADCO08034CIN ADCO08038BIN ADCO8038CIN ADC08031BIWM ADCO8032BIWM ADCO08034BIWM ADCO8038BIWM ADC08031CIWM ADC08032CIWM ADC08034CIWM ADC08038CIWM Supply Voltage 65 C to 150 C Tmn lt TA lt Tmax 40 lt lt 485 C 4 5 Vog to 6 3 8 0800QV r 0800Q0V c 0800QV He60800QV Electrical Characteristics The following specifications apply for Voc Vrer 5 Voc an 1 MHz unless otherwise specified Boldface limits apply for T4 Ty Tmn tO Tmax all other limits T4 Ty Symbol Parameter Conditions Typical Limits Units Note 8 Note 9 Limits CONVERTER AND MULTIPLEXER CHARACTERISTICS LSB max Note 10 1 CIN CIWM LSB max
12. simultaneously high for a period of tseLecr or greater Otherwise these devices are compatible with industry standards ADC0831 2 4 8 www national com 6 Timing Diagrams continued Data Output Timing CLK DATA OUT DO 08010555 11 ADC08031 Start Conversion Timing CLK START CONVERSION 00 MSB BIT 6 DS010555 12 ADCO08031 Timing 0 1 2 3 4 5 6 7 8 8 10 11 CHIP SELECT cs DATA OUT 00 TRI STATE TRI STATE 7 MSB LSB DS010555 13 LSB first output not available on ADC08031 LSB information is maintained for remainder of clock periods until CS goes high ADC08032 Timing 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK gt lt set up E OUTPUT para ANALOG SAMPLING TIME gt CHIP SELECT CS ADDRESS MUX START BIT ODD SIGN DATA IN DI LSB FIRST DATA x SGL DIF 9 ts FIRST DATA DATA OUT 00 TRI STATE TRI STATE 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 MSB LSB MSB DS010555 14 7 www national com 8608020 7608020 2208020 1608002 ADC08031 ADC08032 ADC08034 ADC08038 Timing Diagrams Continued ADC08034 Timing 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 CLOCK CLK gt ser ur OUTPUT DATA ANALOG SAMPLING TIME ta CHIP SELECT CS ADDRESS MUX START BIT ODD SIGN L EA SGL DIF M A D CONVERSION IN PROGRESS
13. INPUT SHIFT REGISTER 74C165 SHIFT LOAD SIN ANAL0G INPUTS ADC08038 D GND VREF OUT START PUSH TO 1 6 74014 START THE A D CONVERSION OUTPUT SHIFT REGISTER 740164 1 3k 8 1 2 74074 MSB DATA DISPLAY 138 DS010555 44 Pinouts shown for ADC08038 For all other products tie to pin functions as shown Low Cost Remote Temperature Sensor ADC08031 5 VREF IN DS010555 45 www national com 16 Applications Continued Digitizing a Current Flow vec 0 1 LOAD 2A FULL SCALE 5 Vog 100 240k 0 08034 VREF 100 ZERO IN 1k ADJ FS AGND GND ADJ 120k Operating with Ratiometric Transducers Vec 5 Q ADC08031 10k VREF IN 1k FS ADJ 24k DS010555 23 Vin 0 15 Vcc 15 of Vcc lt lt 85 of Vcc 17 DS010555 22 www national com 8608020 7608020 2208020 1808002 ADC08031 ADC08032 ADC08034 ADC08038 Applications Continued Span Adjust OV lt Vy lt 5 2k ADC08031 VREF IN LM336 eT 1 uF SET FOR 3V DS010555 46 Zero Shift and Span Adjust 2V lt Vin lt 5V Vec 5 Voc ADC08031 SETS ZERO CODE VOLTAGE 1k 2Voc ZERO ADJ 2 7k www national com 18 DS010555 47 Applications Continued Protecting the Input High Accuracy Comparators 5V Vcc
14. SIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Japan Ltd Tel 81 3 5639 7560 Fax 81 3 5639 7507 National Semiconductor Asia Pacific Customer Response Group Tel 65 2544466 Fax 65 2504466 Email ap support nsc com
15. be tied to Vcc done internally on the ADC08032 This tech nique relaxes the stability requirements of the system refer ence as the analog input and A D reference move together maintaining the same output code for a given input condition 0 08034 VREF IN 08010555 52 a Ratiometric 4 0 THE ANALOG INPUTS The most important feature of these converters is that they can be located right at the analog signal source and through just a few wires can communicate with a controlling proces sor with a highly noise immune serial bit stream This in itself greatly minimizes circuitry to maintain analog signal accu racy which otherwise is most susceptible to noise pickup However a few words are in order with regard to the analog inputs should the input be noisy to begin with or possibly riding on a large common mode voltage The differential input of these converters actually reduces the effects of common mode input noise a signal common to both selected and inputs for a conversion 60 Hz is most typical The time interval between sampling the in put and then the input is 1 2 of a clock period The change in the common mode voltage during this short time interval can cause conversion errors For sinusoidal common mode signal this error is 0 5 Verror max 2 2 J CLK where fcm is the frequency of the common mode signal www national com For absolute accuracy wh
16. co o l 2 g 5 lt 4 lt O O 0 O O O O O O lt gt x 18 oO 73 3 CQ Functional Description 1 0 MULTIPLEXER ADDRESSING The design of these converters utilizes a comparator struc ture with built in sample and hold which provides for a differ ential analog input to be converted by approximation routine The actual voltage converted is always the difference be tween an assigned input terminal and input terminal The polarity of each input terminal of the pair indicates which line the converter expects to be the most positive If the as signed input voltage is less than the input voltage the converter responds with an all zeros output code www national com 10 CH7 O 08010555 17 n E LAMA Q Q Q Q N gt gt gt gt 1 Ladder and Decoder To Internal Circuits Internal Circuits H Input ESD Protection Circuitry Qe 9 e To Channel Inputs Pin 1 8 Other Protection To Internal 20 Circuitry 10 DGND XE 19 Reference 12 11 2 5V Bandgap a For the ADC08034 the SEL 1 Flip Flop is bypassed for the ADC08032 both SEL 0 and SEL 1 Flip Flops are bypassed AGND O COM O Some of these functions pins are no
17. cription continued TABLE 4 MUX Addressing ADC08034 Single Ended MUX Mode MUX Address COM is internally tied to AGND MUX Addressing ADC08032 Single Ended MUX Mode Differential MUX Mode MUX Address SGL DIF START ODD SELECT SIGN 1 _0 1 Sm SG Differential Mode MUX Address Channel START SGL ODD DIF S IGN _ _ 0 0 RN Since the input configuration is under software control it can be modified as required before each conversion A channel can be treated as a single ended ground referenced input for one conversion then it can be reconfigured as part of a differential channel for another conversion Figure 1 illus trates the input flexibility which can be achieved The analog input voltages for each channel can range from 50mV below ground to 50mV above Vec typically 5V with out degrading conversion accuracy 2 0 THE DIGITAL INTERFACE A most important characteristic of these converters is their serial data link with the controlling processor Using a serial communication format offers two very significant system im provements it allows many functions to be included in a small package and it can eliminate the transmission of low www national com 12 level analog signals by locating the converter right at the analog sensor transmitting highly noise immune digital data back to the host processor
18. e ADC08032 for digital output code which is just changing from 1111 1110 to 1111 1111 5 3 Adjusting for an Arbitrary Analog Input Voltage Range If the analog zero voltage of the A D is shifted away from ground for example to accommodate an analog input signal which does not go to ground this new zero reference should be properly adjusted first A Vi voltage which equals this desired zero reference plus 12 LSB where the LSB is calculated for the desired analog span using 1 LSB analog span 256 is applied to selected input and the zero reference voltage at the corresponding input should then be adjusted to just obtain the 00 ey to 01 code tran sition The full scale adjustment should be made with the proper Vin voltage applied by forcing a voltage to the in put which is given by Vmax V Vin fs adj Vmax 1 5 56 where Vmax the high end of the analog input range and Vmin the low end the offset zero of the analog range Both are ground referenced The VggelN or Vec voltage is then adjusted to provide code change from to FFyex This completes the ad justment procedure www national com 8 0800QV r 0800Q0V c 0800QV I 0800QV ADC08031 ADC08032 ADC08034 ADC08038 Applications A Stand Alone Hook Up for ADC08038 Evaluation MUX ADDRESS O 5Voc START BIT SGL DIF PARALLEL INPUTS
19. e current the following two cases are considered one with the selected channel tied high 5 Vpc and the remaining seven off channels tied low 0 Vpc total current flow through the off chan nels is measured two with the selected channel tied low and the off channels tied high total current flow through the off channels is again measured The two cases considered for determining on channel leakage current are the same except total current flow through the selected channel is measured Note 14 A 4095 to 60 duty cycle range insures proper operation at all clock frequencies In the case that an available clock has a duty cycle outside of these limits the minimum time the clock is high or low must be at least 450 ns The maximum time the clock can be high or low is 100 us Note 15 Since data MSB first is the output of the comparator used in the successive approximation loop an additional delay is built in see Block Diagram to allow for comparator response time Note 16 For the ADC08032 VnggrIN is internally tied to Vcc therefore for the ADC08032 reference current is included in the supply current Typical Performance Characteristics Linearity Error vs Linearity Error vs Linearity Error vs Reference Voltage Temperature Clock Frequency 0 50 T 0 50 5 Voc 5 Voc fork MHz
20. ere the analog input varies be tween very specific voltage limits the reference pin can be biased with a time and temperature stable voltage source For the ADC08034 and the ADC08038 a band gap derived reference voltage of 2 6V Note 8 is tied to Vae OUT This can be tied back to VggelN Bypassing VegrOUT with a 100uF capacitor is recommended The LM385 and LM336 reference diodes are good low current devices to use with these converters The maximum value of the reference is limited to the supply voltage The minimum value however can be quite small see Typical Performance Characteristics to allow di rect conversions of transducer outputs providing less than a 5V output span Particular care must be taken with regard to noise pickup circuit layout and system error voltage sources when operating with a reduced span due to the increased sensitivity of the converter 1 LSB equals 256 TRANSDUCER 0 08038 VREF IN 08010555 53 b Absolute with a Reduced Span FIGURE 2 Reference Examples 14 S its peak voltage value and is the A D clock frequency For a 60Hz common mode signal to generate 1 4 LSB error amp 5mV with the converter running at 250kHz its peak value would have to be 6 63V which would be larger than allowed as it exceeds the maximum analog input limits Source resistance limitation is important with regard to the DC leakage currents of the input multiplexer Bypass capaci
21. ess than low a series of successive voltages gener ated internally from a ratioed capacitor array first 5 bits and a resistor ladder last 3 bits After each comparison the comparator s output is shipped to the DO line on the falling edge of CLK This data is the result of the conver sion being shifted out with the MSB first and can be read by the processor immediately After 8 clock periods the conversion is completed The SARS line returns low to indicate this 1 clock cycle later 8 Single Ended Q lt 05010555 48 4 Differential 08010555 50 The stored data in the successive approximation register is loaded into an internal shift register If the programmer prefers the data can be provided in an LSB first format this makes use of the shift enable SE control line On the ADC08038 the SE line is brought out and if held high the value of the LSB remains valid on the DO line When SE is forced low the data is clocked out LSB first On de vices which do not include the SE control line the data LSB first is automatically shifted out the DO line after the MSB first data stream The DO line then goes low and stays low until CS is returned high The ADC08031 is an exception in that its data is only output in MSB first format All internal registers are cleared when the CS line is high and the tse_ect requirement is met See Data Input Tim ing under Timing Diagrams If another conversion is de si
22. ine Because the ADC08031 contains only one differential input channel with a fixed polarity assignment it does not require addressing The common input line COM on the ADC08038 can be used as a pseudo differential input In this mode the voltage on this pin is treated as the input for any of the other input channels This voltage does not have to be analog ground it can be any reference potential which is common to all of the inputs This feature is most useful in single supply applica tions where the analog circuity may be biased up to a poten tial other than ground and the output signals are all referred to this potential TABLE 1 Multiplexer Package Options Part Number of Analog Number Channels Package Single Ended Differential Pins AS 1 1 8 Number of TABLE 2 MUX Addressing ADC08038 Single Ended MUX Mode MUX Address START SGL ODD EI COM E 1 i Analog Single Ended Channel ES qM Juli m e e I c3 oec Lot ttt t Jj TABLE 3 MUX Addressing ADC08038 Differential Mode MUX Address START SGL ODD SELECT SIGN Analog Differential Channel Pair __ O 01 2 O 7 l k T HF 1 www national com 8 08090VY r 08090AV Z 08090V LE0809QAV ADC08031 ADC08032 ADC08034 ADC08038 Functional Des
23. l Semiconductor ADC08031 ADC08032 ADC08034 ADC08038 8 Bit High Speed Serial I O A D Converters with Corporation Europe Americas Fax 49 0 180 530 85 86 Tel 1 800 272 9959 Email europe support nsc com Fax 1 800 737 7018 Deutsch Tel 49 0 69 9508 6208 Email support nsc com English Tel 44 0 870 24 0 2171 www national com Frangais Tel 33 0 1 41 91 8790 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications Physical Dimensions inches millimeters unless otherwise noted Continued 1 013 1 040 25 73 26 42 NE Ds ss 5 u 1 0 032 0 005 MAX DP 0 813 0 127 RAD PIN NO 1 IDENT 0260 005 6 604 0 127 PIN NO 1 IDENT 0 280 kus OPTION 1 MIN 0 300 0 320 OPTION 2 7 620 8 128 0 130 0 005 T 3 302 0 127 651 dcs 0145 0200 3 683 5 080 95 5 0 009 0 015 90 0 004 MEE 0 229 0 381 0 020 TYP 0 125 0 140 0 508 0 080 0 005 2 540 z 0 254 0 018 0 003 3175 3556 MIN 0 040 1 524 0 127 0 457 0 076 0 325 0 015 1016 255 ass 100 N20A REV Order Number ADC08038CIN NS Package Number N20A NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRE
24. limeters unless otherwise noted 0 291 0 299 7 391 7 595 0 009 0 013 0 229 0 330 TYP ALL LEADS 0 102 ALL LEAD TIPS pee 0 017 ase 0 432 8 MAX TYP ALL LEADS 0 030 0 050 0 762 1 270 TYP ALL LEADS 0 346 0 362 8 788 9 195 14 13 12 1110 9 8 0 394 0 419 10 01 10 64 LEAD NO 1 IDENT Q A 0 027 0 686 0 093 0 104 2 362 2 642 0 037 J 044 0 940 1 118 20 050 1 270 270 Order Number ADC08031CIWM ADC08032CIWM ADC08034CIWM NS Package Number M14B www national com 22 0 004 0 012 0 102 305 dt SEATING A PLANE a 0014 0019 7 0 356 0 483 M14B REV D TYP Physical Dimensions inches millimeters unless otherwise noted Continued 0 496 0 512 12 598 13 005 20 19 18 17 16 15 14 13 12 11 0 394 0 419 10 008 10 643 30 TYP LEAD NO 11 IDENT Y y 1 2 3 4 5 6 7 8 9 10 0 010 max 0 254 0 291 0 299 7 391 7 595 0 010 0 029 0 093 0 104 0 254 0 737 49 2 362 2 642 Mc 035 ALL LEADS ee 0 030 i oe 3x Fa A A PLANE 9 009 0 013 0107 0 016 0 050 0 050 0 014 0 020 U lt 0 229 0 330j acl eno TIPS gt 0406 1270 0356
25. me fg 1 MHz max Applications Power dissipation 20mW max Single supply 5Vpc X596 Total unadjusted error LSB and 1LSB No missing codes over temperature zero or full scale adjustment required TTL CMOS input output compatible On chip 2 6V band gap reference 0 3 standard width 8 14 or 20 pin DIP package 14 20 pin small outline packages Digitizing automotive sensors Process control monitoring Remote sensing in noisy environments Instrumentation Ordering Information Industrial 40 C lt Ta lt 85 C ADCO8031CIN NO8E ADC08038CIN N20A ADCO08031CIWM ADC08032CIWM ADC08034CIWM ADC08038CIWM M20B Not recomended for new designs COPS microcontrollers and MICROWIRE are trademarks of National Semiconductor Corporation 2000 National Semiconductor Corporation DS010555 www national com p oH yX381L pue S49149AU02 O I leues peeds ufip 119 8 0802 7 0802 0802 2 ADC08031 ADC08032 ADC08034 ADC08038 Connection Diagrams ADC08038 1 2 3 4 5 6 7 8 c e gt Q 2 05010555 2 ADC08031 Dual In Line Package N Vcc CLK DO IN lt 2 I GQ N an N Co DS010555 5 ADC08031 Small Outline Package DS010555 31 www national com cs NC CHO NC CH1 NC GND 0 08034 08010555 3 0
26. red CS must make a high to low transition followed by address information The DI and DO lines can be tied together and controlled through a bidirectional processor bit with one wire This is possible because the DI input is only looked at during the MUX addressing interval while the DO line is still in a high impedance state 8 Pseudo Differential Cc oc 4 c r9 C B oU POBRE bis DS010555 49 Mixed Mode DS010555 51 FIGURE 1 Analog Input Multiplexer Options for the ADC08038 www national com 8608020 7608020 2208020 1608002 ADC08031 ADC08032 ADC08034 ADC08038 Functional Description continued 3 0 REFERENCE CONSIDERATIONS The voltage applied to the reference input on these convert ers defines the voltage span of the analog input the difference between Vin max and Over which the 256 possible output codes apply The devices can be used either in ratiometric applications or in systems requiring ab solute accuracy The reference pin must be connected to a voltage source capable of driving the reference input resis tance which can be as low as 1 3kQ This pin is the top of a resistor divider string and capacitor array used for the suc cessive approximation conversion In a ratiometric system the analog input voltage is propor tional to the voltage used for the A D reference This voltage is typically the system power supply so the VggelN pin can
27. t Reliability or Linear Data Book section Surface Mount for other methods of soldering surface mount devices Note 8 Typicals are at Ty 25 C and represent the most likely parametric norm Note 9 Guaranteed to National s AOQL Average Outgoing Quality Level Note 10 Total unadjusted error includes offset full scale linearity multiplexer Note 11 Cannot be tested for the ADC08032 Note 12 For Vin Vin4 the digital code will be 0000 0000 Two on chip diodes are tied to each analog input see Block Diagram which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than Vcc supply During testing at low Vcc levels e g 4 5V high level analog inputs e g 5V can cause an input diode to conduct especially at elevated temperatures which will cause errors for analog inputs near full scale The spec allows 50 mV forward bias of either diode this means that as long as the analog does not exceed the supply voltage by more than 50 mV the output code will be correct Ex ceeding this range on an unselected channel will corrupt the reading of a selected channel Achievement of an absolute 0 Vog to 5 input voltage range will there fore require a minimum supply voltage of 4 950 Vog over temperature variations initial tolerance and loading Note 13 Channel leakage current is measured after a single ended channel is selected and the clock is turned off For off channel leakag
28. t available with other options A unique input multiplexing scheme has been utilized to pro vide multiple analog channels with software configurable single ended differential or pseudo differential which will convert the difference between the voltage at any analog in put and a common terminal operation The analog signal conditioning required in transducer based data acquisition systems is significantly simplified with this type of input flex ibility One converter package can now handle ground refer enced inputs and true differential inputs as well as signals with some arbitrary reference voltage A particular input configuration is assigned during the MUX addressing sequence prior to the start of a conversion The MUX address selects which of the analog inputs are to be Functional Description continued enabled and whether this input is single ended or differential Differential inputs are restricted to adjacent channel pairs For example channel 0 and channel 1 may be selected as a differential pair but channel 0 or 1 cannot act differentially with any other channel In addition to selecting differential mode the polarity may also be selected Channel 0 may be selected as the positive input and channel 1 as the negative input or vice versa This programmability is best illustrated by the MUX addressing codes shown in the following tables for the various product options The MUX address is shifted into the converter via the DI l
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