PHILIPS PCF2104x LCD controller/driver handbook
Contents
1. lower 4 bits 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 4 bits 0000 0001 0010 87 0011 ge ue xxxx 0100 D Ho xxxx 0110 7 E H 452 i i xxxx 1000 9 5 i E a 1001 10 a en poo CF xxxx 1010 11 Sa LET LET 1011 12 maian LET 1100 13 sa 1101 14 m rof rrt os EIN 2 CLIE C ann a LI ins a xox 1111 16 SU ses l l MLB895 Fig 5 Character set C in PCF2104C 1997 Dec 16 10 Philips Semiconductors Product specification LCD controller driver PCF2104x ver 4 bis 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 6 bits ERE PO Em xg B 21 05 0001 2 3 B TE cane 02. m m 5 7 mum m m m rd oH i 1000 9 mum 7 u 7 7 Bs xox 1001 10 freee xxxx 1010 11 mammm Ta a n 7 7 1011 12 mm mj mum mum 7 7 7 7 iH a mm am m am xxx 1100 13 mm n a a u a a m 7 7 7 m m m 1101 14 mmn 7 7 7 nun 1110 15 n n a 7 a 1111 16 5 a u amm a MGM134 Fig 7 Character set N in CGROM PCF2104N 1997 Dec 16 12 Philips Semiconductors Product specification LCD controller driver PCF2104x character codes CGRAM character patterns DDRAM data ad
3. SNOJ eu WH 0 OVS no aq y pepeo LYS 0 ZVS L EVS L VS 1 SVS 0 975 SI YQ 24 1091000 eu 21949 BHpajmouyoe eu Buunq 10 yes 614 021 LC 510 021 INS SIUM 01195 0 Seu eur V 1 1 58 0 09 SdiiHd 10 02 eyeq eu jou siu 0 09 4 19 sjuejuoo uonisod peyius 0 0 84 0 83 0 Sad 0 94d 0 288 SuJnja1 sseJppy 0 sseJppe 5195 61 2 0 MY 0 SH 17 09 eq 81 8 days se 10 514 221 dois snq 9 jeuondo 11 509 221 4315 43 1997 Dec 16 Product specification Philips Semiconductors PCF2104x LCD controller driver LUOP X 71 spud 5 2 0 0 83 0 988 0 980 0 280 0 MA 0 SH Kejdsip 1819 Aedsiq
4. 210 O O INTEGRATED CIRCUITS DATA SHEET PCF2104x LCD controller driver Product specification 1997 Dec 16 Supersedes data of 1997 Apr 01 File under Integrated Circuits 1012 Philips PHILIP 5 Semiconductors DH LI p Philips Semiconductors esses LCD controller driver Product specification PCF2104x CONTENTS 1 FEATURES 2 APPLICATIONS 3 GENERAL DESCRIPTION 3 1 Packages 3 2 Available types 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING 7 PIN FUNCTIONS 7 1 RS register select parallel control 7 2 R W read write parallel control 7 3 E data bus clock parallel control 7 4 DBO to DB7 data bus parallel control 7 5 C1 to C60 column driver outputs 7 6 R1 to R32 row driver outputs 7 7 VLCD LCD power supply 7 8 OSC oscillator 7 9 SCL serial clock line 7 10 SDA serial data line 7 11 SAO address pin 7 12 T1 test pad 8 FUNCTIONAL DESCRIPTION 8 1 LCD bias voltage generator 8 2 Oscillator 8 3 External clock 8 4 Power on reset 8 5 Registers 8 6 Busy Flag 8 7 Address Counter AC 8 8 Display data RAM DDRAM 8 9 Character generator ROM CGROM 8 10 Character generator RAM CGRAM 8 11 Cursor control circuit 8 12 Timing generator 8 13 LCD row and column drivers 8 14 Programming of MUX 1 16 displays with PCF2104x 8 15 Programming of MUX 1 32 displays with PCF2104x 8 16 Reset function 9 INSTRUCTIONS 9 1 Clear display 9 2 Return home 9 3 Entry
5. DBO to DB7 MLA799 1 Fig 27 Parallel bus read operation sequence reading data PCF2104x to microcontroller 1997 Dec 16 33 Philips Semiconductors LCD controller driver 17 APPLICATION INFORMATION Product specification PCF2104x R1 to R32 E to P80CL51 PCF2104x LCD C1 to C60 P10 to P17 DBO to DB7 MGC620 Fig 28 Direct connection to 8 bit microcontroller 8 bit bus P10 RS P11 RW to R32 P12 E to P80CL51 PCF2104x LCD C1 to C60 P14 to P17 DB4 to DB7 MGC621 Fig 29 Direct connection to 8 bit microcontroller 4 bit bus R7 to R16 R25 to R32 1 to R8 R17 to R24 2 x 24 CHARACTER LCD DISPLAY nF PCF2104x SPLIT SCREEN C1 to C60 Vss Vss MGC624 080 to 087 RS RW Fig 30 Typical application using parallel interface 1997 Dec 16 34 Philips Semiconductors Product specification LCD controller driver PCF2104x Ri to R16 16 17 24 2x24 CHARACTER LCD DISPLAY 100 SPLIT SCREEN 2104 C1 to C60 Pe Vss Vss R1 to R16 2 x 12 CHARACTER 100 LCD DISPLAY PCF2104x 60 V C1 to C60 3S SS MGC625 SCL SDA MASTER TRANSMITTER PCF84C81 Fig 31 Application using 2 interface 1997 Dec 16 35 Philips Semiconductors LCD controller driver 17 1 8 bit operation 2 x 12 display using internal reset Ta
6. Clear display Return home will not modify the data register content 10 INTERFACE TO MICROCONTROLLER PARALLEL INTERFACE The PCF2104x can send data in either two 4 bit operations or one 8 bit operation and can thus interface to 4 bit or 8 bit microcontrollers In the 8 bit mode data is transferred as 8 bit bytes using the 8 data lines DBO to DB7 Three further control lines E RS and R W are required In the 4 bit mode data is transferred in two cycles of 4 bits each The higher order bits corresponding to DB4 to DB7 in 8 bit mode are sent in the first cycle and the lower order bits DBO to DB3 in 8 bit mode in the second cycle Data transfer is complete after two 4 bit data transfers It should be noted that two cycles are also required for the Busy Flag check 4 bit operation is selected by instruction See Figs 15 16 and 17 for examples of bus protocol In the 4 bit mode pins DB3 to DBO must be left open circuit They are pulled up to Vpp internally Philips Semiconductors LCD controller driver 11 INTERFACE TO MICROCONTROLLER 2C BUS INTERFACE 11 1 Characteristics of the I2C bus The 12 is for bidirectional two line communication between different ICs or modules The two lines are a serial data line SDA and a serial clock line SCL Both lines must be connected to a positive supply via a pull up resistor Data transfer may be initiated only when the bus is not busy 11 2 Bit trans
7. sri op EM 8 8 Jes 4 514 pexoeuo eq Jg 980 0 988 0 280 0 0 SH 5 2 Jes 4 5 siu eq Jg NOILdIH2S3Q 980 0 988 0 280 0 WH 0 SH HOdA sesu Jaye sui em eJe S JO 4315 21 40 1 JON 19 uonezieniu LL 45 1997 Dec 16 Philips Semiconductors Product specification LCD controller driver PCF2104x DISPLAY LAYOUT COLUMNS PCF2104x column 15 46 60 output numbers LCD column 1 31 60 numbers DOT MATRIX LCD 16 45 2104 column output numbers DISPLAY LAYOUT ROWS R8 to R1 R9 to R16 MGC623 R17 to R24 R32 to R25 Fig 32 Example of 4 x 12 display layout PCF2104x 1997 Dec 16 46 Philips Semiconductors Product specification LCD controller driver PCF2104x display glass dot
8. Josuno 5196 195 peBueuoun sjuejuoo uonisod 5 sseJppy 0 sseJppe 5195 sseJppy 0 sseJppe INVHOd 5195 pue Aejdsip amua 2219 18819 SATOAD 490719 NOILdIH2S3Q 980 WH SH dON NOILONHLSNI 1 jou suomonuisu 9IqEL 19 1997 Dec 16 Philips Semiconductors Product specification LCD controller driver PCF2104x Table 4 Command bit identities BIT LOGIC 0 LOGIC 1 decrement increment display off display on character at cursor position does not blink character at cursor position blinks left shift right shift 4 bits 8 bits 2 line x 12 characters MUX 1 16 2 lines x 24 characters MUX 1 32 reserved 4 lines x 12 characters MUX 1 32 end of internal operation internal operation in progress Co last control byte only data bytes to follow next two bytes are a data byte and another control byte RS R W ZX X US IX ZX KKK instruction busy flag and data register i address counter read read E MGA804 Fig 15 4 bit transfer example 1997 Dec 16 20 Philips Semiconductors Product specification LCD controller driver PCF2104x internal internal op
9. seui jo eui Ajroedsg 514 9 si eoejiejur Jes 09 0 18d 0 zgd 0 gaa 0 0 988 0 980 0 280 0 MA 0 SH 0 09 0 9 0 288 0 vad 0 588 0 99 0 288 0 0 SH 0 X 18Q N 1 S80 0 99 0 280 0 MA 0 SH ees y s eu SI 4g ueuM eui pexoeuo eq ueo Jg 19 uonoun 14 pexoeuo eq JOUUE9 Jg 09 X 19 vad S80 0 980 0 280 0 MA 0 SH Jes uomnoun J UONONJJSU 14 eq Jg sm UCU X 08d X 19 X 80 988 0 980 0 280 0 MA 0 SH Jes 4 5 siu eq JOUUE9 Jg 5 2 X 09 X 19 X 1 S80 0 99 0 280 0 0 SH sesu Sul eM eJe S JO NOILdIH2S3
10. 3 5 V to Vpp 9 V Tamb 40 C to 85 C unless otherwise specified SYMBOL PARAMETER LCD frame frequency internal clock CONDITIONS MIN external clock frequency Bus timing characteristics Parallel Interface notes 1 and 2 WRITE OPERATION WRITING DATA FROM MICROCONTROLLER TO PCF2104x address hold time 25 data set up time enable cycle time enable pulse width 500 tasu address set up time address hold time 50 25 data delay time tup data hold time Timing characteristics 12 interface note 2 fscL SCL clock frequency tolerable spike width on bus bus free time set up time for a repeated START condition start condition hold time SCL LOW time SCL HIGH time tr SCL and SDA rise time t SCL and SDA fall time tsu DAT data set up time data hold time tsU STO set up time for STOP condition us 1 Vpp 5 0 V 2 Alltiming values are valid within the operating supply voltage and ambient temperature range and are referenced to and with an input voltage swing of Vss to Vpp 1997 Dec 16 32 Philips Semiconductors Product specification LCD controller driver PCF2104x 16 TIMING DIAGRAMS RS DBO to DB7 MLA798 1 9 26 Parallel bus write operation sequence writing data from microcontroller to PCF2104x RS
11. 359 2 689 102 Canada PHILIPS SEMICONDUCTORS COMPONENTS Tel 1 800 234 7381 China Hong Kong 501 Hong Kong Industrial Technology Centre 72 Tat Chee Avenue Kowloon Tong HONG KONG Tel 852 2319 7888 Fax 852 2319 7700 Colombia see South America Czech Republic see Austria Denmark Prags Boulevard 80 PB 1919 DK 2300 COPENHAGEN S Tel 45 32 88 2636 Fax 45 31 57 1949 Finland Sinikalliontie 3 FIN 02630 ESPOO Tel 358 9 615800 Fax 358 9 61580 xxx France 4 Rue du Port aux Vins BP317 92156 SURESNES Cedex Tel 33 1 40 99 6161 Fax 33 1 40 99 6427 Germany HammerbrookstraBe 69 D 20097 HAMBURG Tel 49 40 23 53 60 Fax 49 40 23 536 300 Greece No 15 25th March Street GR 17778 TAVROS ATHENS Tel 30 1 4894 339 239 Fax 30 1 4814 240 Hungary see Austria India Philips INDIA Ltd Shivsagar Estate A Block Dr Annie Besant Rd Worli MUMBAI 400 018 Tel 91 22 4938 541 Fax 91 22 4938 722 Indonesia see Singapore Ireland Newstead Clonskeagh DUBLIN 14 Tel 353 1 7640 000 Fax 353 1 7640 200 Israel RAPAC Electronics 7 Kehilat Saloniki St TEL AVIV 61180 Tel 972 3 645 0444 Fax 972 3 649 1007 Italy PHILIPS SEMICONDUCTORS Piazza IV Novembre 3 20124 MILANO Tel 39 2 6752 2531 Fax 39 2 6752 2557 Japan Philips Bldg 13 37 Kohnan 2 chome Minato ku TOKYO 108 Tel 81 3 3740 5130 Fax 81 3 3740 5077 Korea Philips House 260 199 Itaewon dong Yongsan ku SEOUL Te
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13. Pays 10 SI JOSIND pue JOU SI 1 jou 40181 1 eui pepeo si ejep Meu 088 0 13 S OU pejus SI 0 1 288 0 83 0 988 0 288 Sng 2z eui JO Joy ON 2 ejou OU 195 8 Gc 0 0 08d 0 19 snq Ozl 10 epoo 0 1 0 vad 0 988 99 0 9 15114 S 18H91 10 epoo 19 x 8 SdiIHd 1 196 8 EJEP vc eoeuelui 604 2 eui pepeo si 0 Jo Bung X 0 X 19 180 S GSW 7 05 1240 Ino S 21949 eDpejwouxoe X 80 X vad X SAC 99 28d 4 9 106 8 1 19 EJEP uMouxun SEM JO au BJOJOIOY seu JOU 5 195 Jeuyeu
14. display position 14 15 1997 Dec 16 18 19 20 21 2 2 cases oe e e oT 14 L8 D T9 MLB901 Fig 14 DDRAM to display mapping left shift PCF2104x Philips Semiconductors LCD controller driver 8 15 Programming of MUX 1 32 displays with PCF2104x To drive a 2 line by 24 characters MUX 1 32 display use instruction Function set to set M N to 0 1 respectively To drive a 4 line by 12 characters MUX 1 32 display use instruction Function set to set M N to 1 1 respectively 8 16 Reset function The PCF2104 automatically initializes resets when power is turned on The state after reset is given in Table 2 Table 2 State after reset DESCRIPTION 1 Display clear 2 Function set DL 1 8 bit interface M N 0 1 line display G 0 not used 3 Display on off control D 0 display off 0 cursor off B 0 blink off 4 Entry mode set I D 1 1 increment G 0 not used Default address pointer to DDRAM The Busy Flag BF indicates the busy state BF logic 1 until initialization ends The busy state lasts 2 ms The chip may also be initialized by software See Tables 10 and 11 6 2 interface reset 1997 Dec 16 Product specification PCF2104x 9 INSTRUCTIONS Only two PCF2104x registers the instruction register IR and the data register DR can be directly controlled by the microcontroller Before interna
15. 0 157 C24 R25 890 156 C25 R26 9000 288 C26 R27 555557 R28 920 053 C28 R1 esp 52 C29 R2 la 51 C30 R3 1951 50 C31 R4 49 C32 L 48 SCL 97 147 C34 98 1 46 C35 RS 199 45 C36 R W 10071 44 C37 5 63 x 2 2 mm Tt 0 143 C38 DB7 2 1 0 42 C39 086 1031 04 C40 y C40 C41 DBS 1041 139 C42 DB4 1050 PCF2104x L138 C43 137 C44 DB3 1061 186 C45 DB2 107 135 C46 ae DBO 185 d 132 C49 SDA 10 1 131 C50 30 C51 29 C52 VLCD 1110 yd L 28 C53 0000 00000000000000000000000 Y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Q 10 Oo M m do 10 s 20062 0 5 10 mm gt MGC628 Chip dimensions approximately 5 10 x 5 63 mm Gold bump dimensions approximately 89 x 89 x 25 um Fig 35 Bonding pad locations 1997 Dec 16 49 Philips Semiconductors Product specification LCD controller driver PCF2104x Table 12 Bonding pad locations dimensions in um All x y coordinates are referenced to centre of chip see Fig 35 C42 39 C41 40 1997 Dec 16 50 Philips Semiconductors Product specification LCD controller driver PCF2104x SYMBOL
16. 0 99 988 0 280 0 1 SH 151 Je o1 peius s N NVHDO EL NOILONYLSNI 4315 41 1997 Dec 16 Product specification Philips Semiconductors PCF2104x LCD controller driver 088 19 0 288 0 80 80 0 99 0 288 5 SOM _ 01 SIM 91 0181 0 08d 0 Lad 0 1 84 0 0 Sad 0 01 SIM LL 0 08d 0 Lad 0 pue 10S1n9 eu 0 0 288 0 Sad 0 19 ueeq seu WWHdQ 941 SOM 01 SIM OL 0 SH 0 09 JO q PUBS 6 0 0 OVS L LYS 0 275 1 SVS 1 975 0 975 E JO NLJS 9 pepeeau si 910J8J9U 0119 eq 1 SH 104 uelis snq 92l 1 jou Ae dsiq WWHDO 0 10 94 0 jo euin eu 1e eu 0 0 288 0 83 0 Sad 0 0 288 eu 1148 0
17. 11 821 2333 Fax 55 11 829 1849 Spain Balmes 22 08007 BARCELONA Tel 34 3 301 6312 Fax 34 3 301 4107 Sweden Kottbygatan 7 Akalla S 16485 STOCKHOLM Tel 46 8 632 2000 Fax 46 8 632 2745 Switzerland Allmendstrasse 140 CH 8027 ZURICH Tel 41 1 488 2686 Fax 41 1 481 7730 Taiwan Philips Semiconductors 6F No 96 Chien Kuo N Rd Sec 1 TAIPEI Taiwan Tel 886 2 2134 2870 Fax 886 2 2134 2874 Thailand PHILIPS ELECTRONICS THAILAND Ltd 209 2 Sanpavuth Bangna Road Prakanong BANGKOK 10260 Tel 66 2 745 4090 Fax 66 2 398 0793 Turkey Talatpasa Cad No 5 80640 GULTEPE ISTANBUL Tel 90 212 279 2770 Fax 90 212 282 6707 Ukraine PHILIPS UKRAINE 4 Patrice Lumumba str Building B Floor 7 252042 KIEV Tel 380 44 264 2776 Fax 380 44 268 0461 United Kingdom Philips Semiconductors Ltd 276 Bath Road Hayes MIDDLESEX 5 Tel 44 181 730 5000 Fax 44 181 754 8421 United States 811 East Arques Avenue SUNNYVALE CA 94088 3409 Tel 1 800 234 7381 Uruguay see South America Vietnam see Singapore Yugoslavia PHILIPS Trg N Pasica 5 v 11000 BEOGRAD Tel 381 11 625 344 Fax 381 11 635 777 Internet http www semiconductors philips com Building BE p P O Box 218 5600 MD EINDHOVEN The Netherlands Fax 31 40 27 24825 Philips Electronics N V 1997 SCA53 All rights are reserved Reproduction in whole or in part is prohibited without the prior written consent o
18. 51 105112 eu uo jewod je 788 0 Sad 99 0 280 0 WH SH Aq ueeq seu 941 SAHM INVHOG INVHOO 6 pays jou Aejdsiq 13 0 y 0 y jo euin eui eu 0 105 0 0 9 0 99 0 280 0 WH 0 SH eu ulus oj pue 5196 es v 0 08d0 L7 19 1 288 0 0 9 0 99 0 280 0 0 SH Jaye si ejdsip 1051n9 pue Aejdsip uo suny ejdsiq 0 0 19 0 0 Sad 0 99 0 280 0 WH 0 SH Reldsip x 2 9409105 16 8 01 5196 19 4 2 19591 ejdsip y Aq SI XpOLZ4Od uo Ajddns L NOILVH3dO NOILONHLSNI 4315 195 19591 4 8 914 1 38 1997 Dec 16 Product specification Philips Semiconductors PCF2104x LCD controller driver 0 sseJppe uonisod eui pue ejdsip yoq N 0 09 19
19. LL A M LT 123 32 Fig 11 Typical LCD waveforms 2 line mode MGA803 1 n state 1 ON state 2 ON 35 15 NP UE E ED ES glee al ES 2 line display 1 32 1997 Dec 16 16 Philips Semiconductors LCD controller driver 8 14 Programming of MUX 1 16 displays with PCF2104x The PCF2104x can be used in the following ways 1 line mode to drive a 2 line display 2x 12 characters with MUX rate 1 16 resulting in better contrast The internal data flow of the chip is optimized for this purpose display position display position 13 14 15 DDRAM address 0 OD OE os Product specification PCF2104x Using the Function set instruction M and set to 0 0 respectively Figures 12 13 and 14 show the DDRAM addresses of the display characters The second row of each table corresponds to either the right half of a 1 line display or to the second line of a 2 line display Wrap around of data during display shift or when writing data is non standard Fig 12 DDRAM to display mapping no shift PCF2104x MLB899 display position 1 2 3 DDRAM address 4F 00 01 display position 14 15 18 19 20 21 2 2 caen e o T9 MLB900 Fig 13 DDRAM to display mapping right shift PCF2104x display position 1 2 8 DDRAM address 01 02 03
20. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale 21 PURCHASE OF PHILIPS COMPONENTS Purchase of Philips 2 components conveys a license under the Philips 2 patent to use the components in the 2 system provided the system conforms to the 2 specification defined by Philips This specification can be ordered using the code 9398 393 40011 1997 Dec 16 52 Philips Semiconductors Product specification LCD controller driver PCF2104x NOTES 1997 Dec 16 53 Philips Semiconductors Product specification LCD controller driver PCF2104x NOTES 1997 Dec 16 54 Philips Semiconductors Product specification LCD controller driver PCF2104x NOTES 1997 Dec 16 55 Philips Semiconductors Argentina see South America Australia 34 Waterloo Road NORTH RYDE NSW 2113 Tel 61 2 9805 4455 Fax 61 2 9805 4466 Austria Computerstr 6 A 1101 WIEN P O Box 213 Tel 43 1 60 101 Fax 43 1 60 101 1210 Belarus Hotel Minsk Business Center Bld 3 r 1211 Volodarski Str 6 220050 MINSK Tel 375 172 200 733 Fax 375 172 200 773 Belgium see The Netherlands Brazil see South America Bulgaria Philips Bulgaria Ltd Energoproject 15th floor 51 James Bourchier Blvd 1407 SOFIA Tel 359 2 689 211 Fax
21. of the display are always shifted together data does not shift from one line to the other 17 4 operation 2 x 12 display A control byte is required with most instructions see Table 9 17 5 Initializing by instruction If the power supply conditions for correctly operating the internal reset circuit are not met the PCF2104x must be initialized by instruction Tables 10 and 11 show how this may be performed for 8 bit and 4 bit operation Philips Semiconductors LCD controller driver Product specification PCF2104x Table 6 4 bit operation 1 line display example using internal reset INSTRUCTION Power supply on PCF2104x is initialized by the internal reset circuit Function set RS 0 R W 0 DB7 0 DB6 0 DB5 1 DB4 0 Function set RS 0 R W 0 DB7 0 DB6 0 RS 0 R W 0 DB7 0 DB6 0 OPERATION Initialized No display appears Sets to 4 bit operation In this instance operation is handled as 8 bits by initialization and only this instruction completes with one write Sets to 4 bit operation selects 2 x 12 display 4 bit operation starts from this point and resetting is needed Display on off control RS 0 R W 0 DB7 0 DB6 0 RS 0 0 DB7 1 DB6 1 Turns on display and cursor Entire display is blank after initialization Entry mode set RS 0 R W 0 DB7 0 0 RS 0 R W 0 DB7 0 DB6 1 Write data to CGR
22. 010 3 T n Les be B a xxxx 0011 4 mE SUI ae SEE a ran 2122 0100 5 P Et EE B vox 0101 25 PAM EUR xxxx 0110 7 PD SUP 42 0111 8 TE 1 vi ae 1010 11 H a UT vox wn 2 P 1100 13 21 DU SU xxxx 1110 15 T nja i 15 i 3 1 1111 16 2s UO p a i Fig 6 Character set L in CGROM PCF2104L 1997 Dec 16 11 Philips Semiconductors Product specification LCD controller driver PCF2104x upper lower 4 bits 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 4 bits rr H mum xxxx 0000 a m aus 0001 2 ss mu mmm m m mm mam 0010 3 e e mu mum 0011 4 0100 5 0101 6 0110 7 7 5 m 0111 8 EEE Elden
23. 04 1 09 09 MH 0 uz SsoJppe De A A Wo Y Pd 7 2 viva Y 10 1 00 I OV TOHLNOO 1 0 8 5 1 27 1997 Dec 16 Philips Semiconductors LCD controller driver 1997 Dec 16 acknowledgement from PCF2104x acknowledgement from master no acknowledgement from master Product specification PCF2104x Fig 24 Master reads slave immediately after first byte READ mode RS previously defined 28 data pointer 5 SLAVE 5 ADDRESS 1 1 n bytes last byte R W update MGC619 Product specification Philips Semiconductors PCF2104x LCD controller driver 018 184 1 lt pue MA 0 pue esu Buruy 614 221 9 614 TOS vas d NOILIGNOO 4018 390IIMONYJOY 857 9v 9 GN Z 8 18915 71090104 29 1997 Dec 16 Philips Semiconductors Product specification LCD controller driver PCF2104x 12 LIMITING VALUES In accordance with the Absolut
24. 288 0 WH SH 01 9IUM NOILONULSNI EL 4315 39 1997 Dec 16 Product specification Philips Semiconductors PCF2104x LCD controller driver 09 1 188 0 _O9OH9IN 0 0 sad 0 0 280 0 WH 0 SH Jo euin eui 16 uius ejdsip 10 sies 0 09 19 ead eaa 0 0 99 988 0 280 0 SH SOM AVY 0 LE 01 09 0 19 1 ead 0 0 99 988 0 280 0 WH 1 SH IN S HM AVY 0 6 2 0 099 0 13 0 0 ead pug eu 0 yd 0 988 99 Z8d 0 WH 0 SH Jo peau eui 10642 y oj sseJppe 5195 SSeJpp 195 8 09 19 0 0 eaa 830 988 99 0 280 0 M H 1 SH 5 INVHOIQ WVHOO 01 M 1 9 eui peyius pue 0 049 0 13 0 0 ead Aq 10510 eu 0 9 4 L pad 0 9 99 0 280 0 L SH peioejes ueeq seu 941 SAMM d INVHO
25. 80 characters Character generator ROM 240 characters Character generator RAM 16 characters 4 8 bit parallel bus or 2 wire 2 interface CMOS TTL compatible 32 row 60 column outputs MUX rates 1 32 and 1 16 Uses common 11 code instruction set Logic supply voltage range Vpp Vss 2 5 to 6 V Display supply voltage range Vpp Vicp 3 5 to 9 V Low power consumption 2 address 011101 SAO N APPLICATIONS Telecom equipment Portable instruments Point of sale terminals 3 GENERAL DESCRIPTION The PCF2104x integrated circuit is similar to the PCF2114x described in the PCF2116 family data sheet 4 ORDERING INFORMATION Product specification PCF2104x but does not contain the high voltage generator of that device The PCF2104x is optimized for chip on glass applications The x in 2104 represents a specific letter code for a character set in the character generator ROM CGROM Two standard character sets are currently available specified by the letters C and L see Figs 5 and 6 Other character sets are available on request The PCF2104x is a low power CMOS LCD controller and driver designed to drive a split screen dot matrix LCD display of 1 or 2 lines by 24 characters or 2 or 4 lines by 12 characters with a 5 x 8 dot format All necessary functions for the display are provided in a single chip including on chip generation of LCD bias voltages which resu
26. AM DDRAM RS 1 R W 0 DB7 0 DB6 1 RS 1 R W 0 DB7 0 DB6 1 1997 Dec 16 Sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the DD CGRAM Display is not shifted Writes P The DDRAM has already been selected by initialization at power on The cursor is incremented by 1 and shifted to the right 37 Product specification Philips Semiconductors PCF2104x LCD controller driver 21 088 0 19 9 ead 0 0 9 1 9 0 28d 0 WH SH IN SOM INVHOG INVHOO LE 0 19 0 0 eaa 0 1 84 0 99 0 28d 0 1 SH eoeds INVHOG INVHOO 01 09 1 19 1 0 288 0 0 9 0 99 0 280 0 0 SH euin lus 10 8196 6 09 1 19 0 0 ead 788 0 8 99 0 280 0 1 SH 5 SOM _ INVHOG INVHOO 01 8 4 0 0 19 0 288 k 988 1 99 0 280 0 1 SH SOM SIM 9 eui peyius pue 0 048d 0 19 0 0 eaa Aq
27. CF2104x LCD controller driver 250 Sul 69 sr oz 580 36 651 9 9 ZH 061 9 01 280 eq 0 0 0 0 0 SH 09 2 10 SH s snq 2 eui UI 14 8 8189 14 10 euru WVU 10 01 10 NVHS 5 0 peal ejep SIUM peau Sjuejuoo 18 UN09 pue peuuojed si 48 Asng SSeJppe 195 SSeJppe NVHOI 5195 pue Asng peau INVHQG 195 INVHOO 195 6 pue W N ejdsip Jo aveau sies 19 4 Sjuejuoo 1 AeIdSIPp syius 105 10S1n9 pue 2 yo uo q ses uius 051 041000 ejdsiq peal pue Buunp peuuojied 25941 Ae dsip jo 1145 pue
28. CTERS 7 DISPLAY ADDRESS ADDRESS COUNTER COUNTER AC 7 INSTRUCTION POWER ON DECODER RESET 8 DATA BUSY INSTRUCTION REGISTER DR FLAG REGISTER IR 7 8 BUFFER 4 4 109 106 105 102 100 97 110 3 080 to DB3 DB4 to DB7 R W RS MGC627 SCL SDA Fig 1 Block diagram 1997 Dec 16 Philips Semiconductors Product specification LCD controller driver PCF2104x 6 PINNING SYMBOL FFC PAD TYPE DESCRIPTION OSC oscillator external clock input Vpp SAO 70 logic supply voltage 2 address pin input Vss R8 to R5 70 ground LCD row driver outputs R32 to R29 R24 to R17 13 to 20 LCD row driver outputs LCD row driver outputs C60 to C1 21 to 80 LCD column driver outputs R9 to R16 R25 to R28 81 to 88 89 to 92 LCD row driver outputs LCD row driver outputs R1 to R4 93 to 96 LCD row driver outputs serial clock input 97 98 99 data bus clock input register select input SCL E RS T1 101 read write input test pad input DB7 to DBO SDA 102 to 109 110 8 bit bidirectional data bus input output serial data input output 111 LCD supply voltage input 7 5 74 DBO to DB7 data bus parallel control The bidirectional 3 state data b
29. O View HIGH level input voltage pins E RS R W DBO to DB7 and SAO ViH osc pull up current at pins DBO to DB7 Vss RS and R W LOW level output current pins VoL 0 4 V Voo 5 DBO to DB7 leakage current pins OSC E RS Vi Vpp or Vss R W DBO to DB7 and SAO 12 SDA SCL Vite LOW level input voltage note 3 leakage current or Vss SDA LOW level output current SDA Vor 0 4 V 5 V LCD outputs Rrow row output resistance pins note 5 R1 to R32 column output resistance pins note 5 3 6 C1 to C60 bias voltage tolerance pins note 6 320 130 mV R1 to R32 and C1 to C60 Notes 1 LCD outputs are open circuit inputs at Vpp Vss Vpp bus inactive internal or external clock with duty cycle 50 1551 only 2 Resets all logic when Vpp lt Vpor 3 When the voltages are above or below the supply voltages Vss an input current may flow this current must not exceed 0 5 mA 4 Tested on sample basis 5 Resistance of output terminals R1 to R32 and C1 to C60 with load current 150 9 V outputs measured one at a time 6 LCD outputs open circuit 1997 Dec 16 31 Philips Semiconductors LCD controller driver 15 AC CHARACTERISTICS Product specification PCF2104x Vpp 2 5 to 6 0 V Vss 0 V
30. PAD C4 77 C3 78 2349 2349 2349 2349 2349 2349 2349 2349 F 1997 Dec 16 51 Philips Semiconductors Product specification LCD controller driver PCF2104x 19 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development Preliminary specification This data sheet contains preliminary data supplementary data may be published later Product specification This data sheet contains final product specifications Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System IEC 134 Stress above one or more of the limiting values may cause permanent damage to the device These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied Exposure to limiting values for extended periods may affect device reliability Application information Where application information is given it is advisory and does not form part of the specification 20 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury
31. Q 4315 10 eoepiequi 19 8 OF 44 1997 Dec 16 Product specification Philips Semiconductors PCF2104x LCD controller driver spud S vaa 1 89 1 980 0 280 0 0 SH 0 vad 0 Sad 0 988 0 280 0 MH 0 SH Kejdsip 12919 0 vad 0 0 980 280 0 0 SH 0 vad 0 Sad 0 988 0 280 0 MH 0 SH Aedsiq 0 vad 0 0 980 280 0 0 SH 0 vad 0 Sad 0 988 0 280 0 WH 0 SH onsuejoegeuo pue jo Ajioedg s 195 0 0 N 99 280 0 0 SH 0 vad Sad 0 99 0 280 0 WH 0 SH 8 s 01 198 198 4 ees euim eui si euin pexoeuo JOU SI 44 ueuM eui Jaye eq ueo Jg 0 vad Sad 0 988 0 280 0 WH 0 SH Jes 4 814 eq Jg 980 0 988 0 280 0 WH 0 SH
32. Q NWNVHOO 01 M G pays jou Aejdsiq 0 09 19 eaa 0 ead NvHad 99 94 euim eui eu Josuno 0 0 988 0 99 0 288 0 WH 0 SH 941 146 0 pue Aq eu sjes Si 0 09 19 280 1 680 uonezi eniul 0 vad 0 988 0 99 0 288 0 WH 0 SH Jaye si ejdsip mu pue ejdsip uo suny e dsiq 0 0 13 0 288 k 1 988 0 988 0 280 0 WH 0 SH Ke dsip pz x 2 5109058 uone1edo 16 8 01 sies Jes 2 19591 ejdsip y Aq SI XpOLZ4Od uo Ajddns AV1dSId NOILONHLSNI 4316 19591 ejdsip 8 9 91 1 40 1997 Dec 16 Product specification Philips Semiconductors PCF2104x LCD controller driver 0 09 19 0 280 0 sseippe _ WO9OHOIN 0 0 saa 0 98 0 280 0 0 SH uonisod eui pue ejdsip GL vl z 09 0 19 284 1 ead 1145 puooes 0
33. a 4 line display from 00 to 13 20 to 33 40 to 53 and 60 to 73 for lines 1 2 3 and 4 respectively For 2 and 4 line displays the end address of one line and the start address of the next line are not consecutive When the display is shifted each line wraps around independently of the others see Figs 3 and 4 When data is written to the DDRAM wrap around occurs from 4F to 00 in 1 line mode and from 27 to 40 and 67 to 00 in 2 line mode from 13 to 20 33 to 40 53 to 60 and 73 to 00 in 4 line mode 8 9 Character generator ROM CGROM The character generator ROM generates 240 character patterns in 5 x 8 dot format from 8 bit character codes Figures 5 and 6 show the character sets currently available 1997 Dec 16 Product specification PCF2104x 8 10 Character generator RAM CGRAM Up to 16 user defined characters may be stored in the character generator RAM The CGROM and CGRAM use a common address space of which the first column is reserved for the CGRAM see Fig 5 Figure 8 shows the addressing principle for the CGRAM 8 11 Cursor control circuit The cursor control circuit generates the cursor underline and or character blink as shown in Fig 9 at the DDRAM address contained in the Address Counter When the Address Counter contains the CGRAM address the cursor will be inhibited 8 12 Timing generator The timing generator produces the various signals required to drive the internal circuitry Internal chip operatio
34. ble 7 shows an example of a 1 line display in 8 bit operation The PCF2104x functions must be set by the function set instruction prior to display Since the display data RAM can store data for 80 characters the RAM can be used for advertising displays when combined with display shift operation Since the display shift operation changes the display position only and DDRAM contents remain unchanged Display data entered first can be displayed when the Return home instruction is performed 17 2 4 bit operation 2 x 12 display using internal reset The program must set functions prior to 4 bit operation Table 6 shows an example When power is turned on 8 bit operation is automatically selected and the PCF2104x attempts to perform the first write as an 8 bit operation Since nothing is connected to DBO to DB3 a rewrite is then required However since one operation is completed in two accesses of 4 bit operation a rewrite is required to set the functions see Table 6 step 3 Thus DB4 to DB7 of the function set are written twice 1997 Dec 16 36 Product specification PCF2104x 17 3 8 bit operation 2 x 24 display For a 2 line display the cursor automatically moves from the first to the second line after the 40th digit of the first line has been written Thus if there are only 8 characters in the first line the DDRAM address must be set after the eighth character is completed see Table 8 It should be noted that both lines
35. cated by the cursor blinks when B logic 1 The blink is displayed by switching between display characters and all dots on with a period of 1 second when fosc 150 kHz see Fig 9 At other clock frequencies the blink period is equal to 150 2 The cursor and the blink can be set to display simultaneously 9 5 Cursor display shift Cursor display shift moves the cursor position or the display to the right or left without writing or reading display data This function is used to correct a character or move the cursor through the display In 2 or 4 line displays the cursor moves to the next line when it passes the last position of the line 40 20 decimal When the displayed data is shifted repeatedly all lines shift at the same time displayed characters do not shift into the next line The Address Counter AC content does not change if the only action performed is shift display but increments or decrements with the cursor shift 9 6 Function set 9 6 1 DL PARALLEL MODE ONLY Sets interface data width Data is sent or received in bytes DB7 to DBO when DL logic 1 or in two nibbles DB7 to DB4 when DL logic 0 When 4 bit width is selected data is transmitted in two cycles using the parallel bus Function set from 12 interface DL bit can not bet set to logic 0 from the 12 interface If bit DL has been set to logic 0 via the parallel bus programming via the interface is com
36. clock pulse for START acknowledgement condition MBC602 Fig 21 Acknowledgement on the I2C bus 1997 Dec 16 25 Product specification Philips Semiconductors 5 22 014 CN LL O MH Sseippe 012 0 RE 41999 0 Ojvj bt 01110 Jejuiod ayepdn 09 Wu lt 0 uz sselppe 5 A A A A NC V ALA IOHINOO 0 V viva VI LAS IOHINOO 1 0 8 0 1 015 t 77 4 gt TD O gt 26 1997 Dec 16 Product specification Philips Semiconductors PCF2104x LCD controller driver MH SH 195 58 PIOM SSeJppe Jaye ase 62 014 Jejuiod eyep 81909 ni 158 eq e s eig 1527 1 3AV 1S D Jojsew ou 0124
37. dress CGRAM data 7 6 5 4 3 2 6 5 4 3 2 4 3 2 1 0 higher lower higher lower higher lower 4 order order order order gt order order bits bits bits bits bits bits 00000000 0000000 0 0 1 0 1 0 character 0 1 1 pattern 1 0 0 example 1 1 0 1 1 1 0 1 1 1 d cursor position 000 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 character 0 1 d pattern 1 0 0 example 2 1 0 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 ee ee Con 2 0 00 0 1 1 1 1 1 1 1 1 1 1 o 0 0 O 1 1 1d 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 dq aput 4 MGA800 1 Character code bits 0 to 3 correspond to CGRAM address bits 3 to 6 CGRAM address bits 0 to 2 designate character pattern line position The 8th line is the cursor position and display is performed by logical OR with the cursor Data in the 8 line will appear in the cursor position Character pattern column positions correspond to CGRAM data bits 0 to 4 bit 4 being at the left end as shown in the figure CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0 CGRAM data logic 1 corresponds to selection for display Only bits 0 to 5 of the CGRAM address are set by the Set CGRAM address instruction Bit 6 can be set using the Set DDRAM address instruction or by using the auto increment feature during CGRAM write All bits 0 to 6 can be read using the Read Busy Flag and address instruction Fig 8 Re
38. e Maximum Rating System IEC 134 SYMBOL PARAMETER MIN MAX UNIT supply voltage 0 5 48 0 LCD supply voltage Vpp 11 input voltage OSC RS R W and DBO to 087 Vss 0 5 Vpp 0 5 output voltage R1 to R32 C1 to C60 and Vicp 0 5 0 5 DC input current 10 10 DC output current 10 10 Iss lLcp Vss Vicp current 50 50 Prot total power dissipation 400 mW Po power dissipation per output 100 Tstg storage temperature 4150 13 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling However to be totally safe it is desirable to take normal precautions appropriate to handling MOS devices see Handling MOS Devices 14 DC CHARACTERISTICS Vpp 2 5 to 6 V Vss 0 V 3 5 to Vpp 9 V Tamb 40 to 85 C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN supply voltage 2 5 supply current external Vicp note 1 supply current 2 Vpp 5 9 V fose 150 kHz Tamb 25 C supply current 3 5 V fose 150 kHz Tamb 25 input current notes 1 and 6 Vpor Power on reset voltage level 1997 Dec 16 30 Philips Semiconductors Product specification LCD controller driver PCF2104x SYMBOL PARAMETER CONDITIONS Logic LOW level input voltage pins E RS R W DBO to DB7 and SA
39. e display MLA793 Fig 2 DDRAM to display mapping no shift PCF2104x 1997 Dec 16 Philips Semiconductors LCD controller driver Product specification PCF2104x 53 40 41 42 43 44 45 46 47 48 49 4A 444444444 MLA803 9 6A display PCF2104x line 1 line 2 line 1 line 2 Display Position 123 4 5 22 23 24 decimal v sala DDRAM 00 01 02 03 5116 Address vh hex 1 line display 27 00 01 02 03 14 15 16 DDRAM Address hex 67 40 41 42 43 54 55 56 2 line display MLA802 1234 5 6 7 8 9 10 11 12 13 00 01 02 03 04 05 06 07 08 09 2 25 52 DDRAM Address hex line 3 line 4 Fig 3 DDRAM to display mapping right shift Display Position decimal DDRAM Address hex DDRAM Address hex DDRAM Address hex 123 4 5 22 23 24 oi foe a 7 1 line display oi va os ls po line 1 18444 2 line display MEABITS 123456 6 8 9101112 PEPE EERE ve 21 22 23 24 25 26 27 28 29 2 28 22 line 2 61 62 63 64 65 66 67 68 69 6 6 8 6 line 4 4 line display MLA816 Fig 4 DDRAM to display mapping left shift 2104 1997 Dec 16 Philips Semiconductors Product specification LCD controller driver PCF2104x
40. eration or ZK X 777 instruction busy flag busy flag instruction write check check write MGA805 IR7 IR3 instruction 7 bit 3 bit Address Counter 3 bit Fig 16 An example of 4 bit data transfer timing sequence RS internal ommum instruction busy flag busy flag busy flag instruction write check check check write MGA806 Fig 17 Example of Busy Flag check timing sequence 1997 Dec 16 21 Philips Semiconductors LCD controller driver 9 1 Clear display Clear display writes space code 20 hexadecimal into all DDRAM addresses the character pattern for character code 20 must be a blank pattern sets the DDRAM Address Counter to logic 0 and returns the display to its original position if it was shifted Consequently the display disappears and the cursor or blink position goes to the left edge of the display the first line if 2 or 4 lines are displayed and sets the entry mode I D logic 1 increment mode S of entry mode does not change The instruction Clear display requires extra execution time This may be allowed for by checking the Busy Flag BF or by waiting until 2 ms has elapsed The latter must be applied where no read back options are foreseen as in some chip on glass COG applications 9 2 Return home Return home sets the DDRAM Address Counter to logic 0 and returns the dis
41. f the copyright owner The information presented in this document does not form part of any quotation or contract is believed to be accurate and reliable and may be changed without notice No liability will be accepted by the publisher for any consequence of its use Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights Printed in The Netherlands 417067 1200 04 pp56 Philips Semiconductors Date of release 1997 Dec 16 Document order number 9397 750 02924 lets make things better S PHILIPS
42. fer One data bit is transferred during each clock pulse The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal 11 3 Start and stop conditions Both data and clock lines remain HIGH when the bus is not busy A HIGH to LOW transition of the data line while the clock is HIGH is defined as the START condition S A LOW to HIGH transition of the data line while the clock is HIGH is defined as the STOP condition P 11 4 System configuration A device generating a message is a transmitter a device receiving a message is the receiver The device that controls the message is the master and the devices which are controlled by the master are the slaves data line stable data valid Product specification PCF2104x 11 5 Acknowledge The number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlimited Each byte of eight bits is followed by an acknowledge bit The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse A slave receiver which is addressed must generate an acknowledge after the reception of each byte Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitte
43. ill not be executed until BF logic 0 so BF should be checked before sending another instruction At the same time the value of the Address Counter expressed in binary A 6 to 0 is read out The Address Counter is used by both CGRAM and DDRAM and its value is determined by the previous instruction 9 10 Write data to CGRAM or DDRAM Writes binary 8 bit data D 7 to D 0 to the CGRAM or the DDRAM Whether the CGRAM or DDRAM is to be written to is determined by the previous specification of CGRAM or DDRAM address setting After writing the address automatically increments or decrements by 1 in accordance with the entry mode Only bits DO to D4 of CGRAM data are valid bits D5 to D7 are don t care 1997 Dec 16 Product specification PCF2104x 9 11 Read data from CGRAM or DDRAM Reads binary 8 bit data D 7 to D 0 from the CGRAM DDRAM The most recent Set address instruction determines whether the CGRAM or DDRAM is to be read The Read data instruction gates the content of the data register DR to the bus while E HIGH After E goes LOW again internal operation increments or decrements the AC and stores RAM data corresponding to the new AC into the DR Remark the only three instructions that update the data register DR are Set CGRAM address e Set DDRAM address e Read data CGRAM DDRAM Other instructions e g Write data Cursor display shift
44. l 82 2 709 1412 Fax 82 2 709 1415 Malaysia No 76 Jalan Universiti 46200 PETALING JAYA SELANGOR Tel 60 3 750 5214 Fax 60 3 757 4880 Mexico 5900 Gateway East Suite 200 EL PASO TEXAS 79905 Tel 9 5 800 234 7381 Middle East see Italy For all other countries apply to Philips Semiconductors Marketing amp Sales Communications a worldwide company Netherlands Postbus 90050 5600 PB EINDHOVEN Bldg VB Tel 31 40 27 82785 Fax 31 40 27 88399 New Zealand 2 Wagener Place C P O Box 1041 AUCKLAND Tel 64 9 849 4160 Fax 64 9 849 7811 Norway Box 1 Manglerud 0612 OSLO Tel 47 22 74 8000 Fax 47 22 74 8341 Philippines Philips Semiconductors Philippines Inc 106 Valero St Salcedo Village 2108 MCC MAKATI Metro MANILA Tel 63 2 816 6380 Fax 63 2 817 3474 Poland UI Lukiska 10 PL 04 123 WARSZAWA Tel 48 22 612 2831 Fax 48 22 612 2327 Portugal see Spain Romania see Italy Russia Philips Russia Ul Usatcheva 35A 119048 MOSCOW Tel 7 095 755 6918 Fax 7 095 755 6919 Singapore Lorong 1 Toa Payoh SINGAPORE 1231 Tel 65 350 2538 Fax 65 251 6500 Slovakia see Austria Slovenia see Italy South Africa S A PHILIPS Pty Ltd 195 215 Main Road Martindale 2092 JOHANNESBURG P O Box 7430 Johannesburg 2000 Tel 27 11 470 5911 Fax 27 11 470 5494 South America Rua do Rocio 220 5 floor Suite 51 04552 903 Sao Paulo SAO PAULO SP Brazil Tel 55
45. l operation control information is stored temporarily in these registers to allow interface to various types of microcontrollers which operate at different speeds or to allow interfacing to peripheral control ICs The PCF2104x operation is controlled by the instructions shown in Table 3 together with their execution time Details are explained in subsequent sections Instructions are of 4 categories those that 1 Designate PCF2104x functions such as display format data length etc 2 Set internal RAM addresses 3 Perform data transfer with internal RAM 4 Others In normal use category 3 instructions are used most frequently However automatic incrementing by 1 or decrementing by 1 of internal RAM addresses after each data write lessens the microcontroller program load The display shift in particular can be performed concurrently with display data write thus enabling the designer to develop systems in minimum time with maximum programming efficiency During internal operation no instruction other than the Busy Flag address read instruction will be executed Because the Busy Flag is set to logic 1 while an instruction is being executed it is advisable to ensure that the flag it is at logic 0 before sending the next instruction or wait for the maximum instruction execution time as given in Table 3 An instruction sent while the Busy Flag is HIGH will not be executed Product specification Philips Semiconductors P
46. lationship between CGRAM addresses data and display patterns 1997 Dec 16 13 Philips Semiconductors Product specification LCD controller driver PCF2104x cursor MGA801 5 x 7 dot character font alternating display cursor display example blink display example Fig 9 Cursor and blink display examples 1997 Dec 16 14 Philips Semiconductors LCD controller driver Product specification PCF2104x Vpp Vo Na V5 Vicp ROW 1 Vpp Vo Va Na V5 VLcD ROW 9 Vpp Vo V3 V5 Vi CD ROW 2 Vpp Vo Va V5 VLCD COL 1 VDD Vo Va Na V5 VLCD COL 2 0 25 state1 OV 0 25 VoP VoP 0 25 Vop state2 OV 0 25 Vop VoP frame gt lt 1 Fig 10 Typical LCD waveforms 1 line mode MGA802 1 state 1 ON r state 2 ON 1 line display 1 16 1997 Dec 16 15 Philips Semiconductors LCD controller driver Product specification PCF2104x ROW 1 ROW 9 ROW 2 COL 1 COL 2 0 15 Vop state2 OV e frame 123 32 lt frame n1 LEE EHE HEEL
47. lts in a minimum of external components and lower System power consumption To allow partial Vpp shutdown the ESD protection system of the SCL and SDA pins does not use a diode connected to Vpp The chip contains a character generator and displays alphanumeric and kana characters The PCF2104x interfaces to most microcontrollers via a 4 or 8 bit bus or via the 2 wire 12 3 1 Packages PCF2104xU 2 chip with bumps in tray PCF2104xU 7 chip with bumps on tape For further details see Chapter 18 3 2 Available types PCF2104CU x character set C in CGROM e PCF2104LU x character set L in CGROM e PCF2104NU x character set N in CGROM TYPE NUMBER PACKAGE NAME DESCRIPTION VERSION PCF2104CU 2 chip with bumps in tray PCF2104CU 7 chip with bumps on tape PCF2104LU 2 chip with bumps in tray PCF2104LU 7 chip with bumps on tape PCF2104NU 2 chip with bumps in tray chip with bumps on tape PCF2104NU 7 1997 Dec 16 Philips Semiconductors Product specification LCD controller driver PCF2104x 5 BLOCK DIAGRAM C1 to C60 to R32 COLUMN DRIVERS Vicb GENERATOR 6 60 32 SHIFT REGISTER DATA LATCHES 32 BIT SHIFT REGISTER 5 x 12 bit PCF2104x CHARACTER CHARACTER js GENERATOR GENE PA T R CGROM 240 CHARACTERS CHARACTERS Ti TIMING 7 8 GENERATOR DISPLAY DATA RAM DDRAM 80 CHARA
48. matrix COLUMN LAYOUT ROW LAYOUT 1to8 16109 MLB898 2 lines by 12 characters display Fig 33 Display example PCF2104x 2 lines by 12 characters 1997 Dec 16 47 Philips Semiconductors LCD controller driver 1 R8 R17 R24 PCF2104x CHIP ON GLASS m 4 LINE BY 12 CHARACTER E MGC626 SDA VLCD Fig 34 Chip on glass application Product specification PCF2104x 1997 Dec 16 48 Philips Semiconductors Product specification LCD controller driver PCF2104x 18 BONDING PAD LOCATIONS QN OMR f rger 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 000000 0000000000000000000000 R15 Zy 029 R16 88
49. mode set 9 3 1 9 3 2 5 1997 16 Display on off control D Cursor display shift Function set DL parallel mode only N M Set CGRAM address Set DDRAM address Read busy flag and address Write data to CGRAM or DDRAM Read data from CGRAM or DDRAM INTERFACE TO MICROCONTROLLER PARALLEL INTERFACE INTERFACE TO MICROCONTROLLER INTERFACE Characteristics of the 12 Bit transfer Start and stop conditions System configuration Acknowledge 2 protocol LIMITING VALUES HANDLING DC CHARACTERISTICS AC CHARACTERISTICS TIMING DIAGRAMS APPLICATION INFORMATION 8 bit operation 2 x 12 display using internal reset 4 bit operation 2 x 12 display using internal reset 8 bit operation 2 x 24 display operation 2 x 12 display Initializing by instruction BONDING PAD LOCATIONS DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS 12C COMPONENTS BUS Philips Semiconductors LCD controller driver 1 FEATURES Single chip LCD controller driver 1 or 2 line display of up to 24 characters line or 2 or 4 lines of up to 12 characters per line 5 x 7 character format plus cursor 5 x 8 for kana Japanese syllabary and user defined symbols On chip generation of intermediate LCD bias voltages oscillator requires no external components external clock also possible Display data RAM
50. n is not disturbed by operations on the data buses 8 13 LCD row and column drivers The PCF2104x contains 32 row and 60 column drivers which connect the appropriate LCD bias voltages in sequence to the display in accordance with the data to be displayed The bias voltages and the timing are selected automatically when the number of lines in the display is selected Figures 10 and 11 show typical waveforms In the 1 line mode 1 16 the row outputs are driven in pairs R1 R17 R2 R18 for example This allows the output pairs to be connected in parallel thereby providing greater drive capability Unused outputs should be left unconnected Philips Semiconductors LCD controller driver Product specification PCF2104x non displayed DDRAM addresses Porten 12345 22 23 24 gt decimal o 02 03 04 15116117 s s cc DDRAM Address 1 line display hex non displayed DDRAM address 00 01 02 031 04 15 16 17 18 19 eps 2627 line 1 DDRAM Address hex 40 41 42 43 44 55 56 57 58 s 66 line 2 2 line display 792 non displayed DDRAM addresses 1234567 8 9 10 1112 gt 00 01 02 03 04 05 06 07 08 09 OD OE OF 10 11 12 13 line 1 DDRAM Address hex o m 4 lin
51. ntrast is negligible Table 1 Optimum values for Vop NUMBER OF BIAS LEVELS DISCRIMINATION Von 1997 Dec 16 Product specification PCF2104x 8 2 Oscillator The on chip oscillator provides the clock signal for the display system No external components are required Pin OSC must be connected to Vpp 8 3 External clock If an external clock is to be used it must be input at pin OSC The resulting display frame frequency is given by V2304fosc A clock signal must always be present otherwise the LCD may be frozen in a DC state 8 4 Power on reset The Power on reset block initializes the chip after power on or power failure 8 5 Registers The PCF2104x has two 8 bit registers an instruction register IR and a data register DR The register select signal RS determines which register will be accessed The instruction register stores instruction codes such as display clear and cursor shift and address information for the Display Data RAM DDRAM and Character Generator RAM CGRAM The instruction register can be written to but not read from by the system controller The data register temporarily stores data to be read from the DDRAM and CGRAM When reading data from the DDRAM or CGRAM corresponding to the address in the Address Counter is written to the data register prior to being read by the Read data instruction 8 6 Busy Flag The Busy Flag indicates the free busy stat
52. play to its original position if it was shifted DDRAM contents do not change The cursor or blink position goes to the left of the display the first line if 2 or 4 lines are displayed I D and of entry mode do not change 9 3 Entry mode set 9 3 1 VD When I D logic 1 0 the DDRAM or CGRAM address increments decrements by 1 when data is written to or read from the DDRAM or CGRAM The cursor or blink position moves to the right when incremented and to the left when decremented The cursor and blink are inhibited when the CGRAM is accessed 9 3 2 5 When logic 1 the entire display shifts either to the right I D logic 0 or to the left I D logic 1 during DDRAM write Consequently it looks as if the cursor stands still and the display moves The display does not shift when reading from the DDRAM or when writing to or reading from the CGRAM When logic 0 the display does not shift 9 4 Display on off control 9 4 1 D The display is on when D logic 1 and off when D logic 0 Display data in the DDRAM is not affected and can be displayed immediately by setting D to logic 1 1997 Dec 16 Product specification PCF2104x 942 The cursor is displayed when C logic 1 and inhibited when C logic 0 Even if the cursor disappears the display functions etc remain in operation during display data write The cursor is displayed using 5 dots in the 8th line see Fig 9 943 B The character indi
53. plicated 9 6 2 Sets number of display lines 1 In a 4 bit application DB3 to DBO are left open internal pull ups Hence in the first function set instruction after power on G and H are set to 1 A second function set must then be sent 2 nibbles to set G and H to their required values Philips Semiconductors LCD controller driver 9 7 Set CGRAM address Set CGRAM address sets bits 0 to 5 of the CGRAM address in Table 3 into the Address Counter binary A 5 to A 0 Data can then be written to or read from the CGRAM Only bits 0 to 5 of the CGRAM address are set by the Set CGRAM address instruction Bit 6 can be set using the Set DDRAM address instruction or by using the auto increment feature during CGRAM write All bits 0 to 6 can be read using the Read busy flag and address instruction 9 8 Set DDRAM address Set DDRAM address sets the DDRAM address App in Table 3 into the Address Counter binary A 6 to 0 Data can then be written to or read from the DDRAM Table 5 Hexadecimal address ranges ADDRESS FUNCTION 00 to 4F 1 line by 24 2 line by 12 00 to OB and OC to 4F 00 to 27 and 40 to 67 00 to 13 20 to 33 40 to 53 and 60 to 73 2 line by 24 4 line by 12 9 9 Read busy flag and address Read busy flag and address reads the Busy Flag BF When BF logic 1 it indicates that an internal operation is in progress The next instruction w
54. pue sseJppe 0 51956 es 9 0 09 Lad 519 OyI OSW ur HUEIQ oz 1819821249 1 9 0 0 0 0 19 smous pue ejdsip uo sun m yo uo e dsiq G 0 08d 0 Lad jo SUEJS 81049 0 0 84 83 0 0 288 esind 195 S19818S 4 v 0 0 SH 0 09 10 M H Su 5195 395 0 011U09 PUBS e 0 0 OVS 016 0 L LYS 0 275 1 SVS 1 975 0 975 Aq eq v qs 21949 eDpejwouxoe OM 10 2 ejdsip on pes 51 021 NOILVH3dO 509 221 4315 SSA Aejdsip sng 9 jo 6 eiqer 42 1997 Dec 16 Product specification Philips Semiconductors PCF2104x LCD controller driver aBpajmouyoe qv3u eui eu Aq 16 Je VAS Z X dois 04 92
55. r The device that acknowledges must pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse set up and hold times must be taken into consideration A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition 11 6 12C bus protocol Before any data is transmitted on the 2 the device which should respond is addressed first The addressing is always carried out with the first byte transmitted after the start procedure The 12C bus configuration for the different PCF2104x READ and WRITE cycles is illustrated in Figs 22 23 and 24 change of data allowed MBC621 Fig 18 Bit transfer 1997 Dec 16 24 Philips Semiconductors Product specification LCD controller driver PCF2104x START condition STOP condition MBC622 Fig 19 Definition of START and STOP conditions SDA MASTER TRANSMITTER RECEIVER SLAVE MASTER TRANSMITTER TRANSMITTER RECEIVER RECEIVER SCL MGA807 Fig 20 System configuration DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER SCL FROM MASTER not acknowledge x EE y acknowledge 222203 228212 5 zi
56. s when 2 control is used These pins output the row select waveforms to the left and right halves of the display 7 7 Vicp LCD power supply Negative power supply for the liquid crystal display 1997 Dec 16 5 Philips Semiconductors LCD controller driver 7 8 OSC oscillator When the on chip oscillator is used this pin must be connected to Vpp An external clock signal if used is input at this pin 7 9 SCL serial clock line Input for the 2 clock signal 7 10 SDA serial data line Input output for the 12C bus data line 7 11 SAO address The hardware sub address line is used to program the device sub address for 2 different PCF2104xs on the same 12 712 1 test pad Must be connected to Vss Not user accessible 8 FUNCTIONAL DESCRIPTION see Fig 1 8 1 LCD bias voltage generator The intermediate bias voltages for the LCD display are also generated on chip This removes the need for an external resistive bias chain and significantly reduces the system power consumption The optimum levels depend on the multiplex rate and are selected automatically when the number of lines in the display is defined The optimum value of Vop depends on the multiplex rate the LCD threshold voltage Vin and the number of bias levels The relationships are given in Table 1 Using a 5 level bias scheme for 1 16 MUX rate allows Vop lt 5 V for most LCD liquids The effect on the display co
57. us of the PCF2104x Logic 1 indicates that the chip is busy and further instructions will not be accepted The Busy Flag is output at pin DB7 when RS logic 0 and R W logic 1 Instructions should only be written after checking that the Busy Flag is at logic 0 or waiting for the required number of clock cycles Philips Semiconductors LCD controller driver 8 7 Address Counter The Address Counter assigns addresses to the DDRAM and CGRAM for reading and writing and is set by the instructions Set CGRAM address and Set DDRAM address After a read write operation the Address Counter is automatically incremented or decremented by 1 The Address Counter contents are output to the bus DBO to DB6 when RS logic 0 and R W logic 1 8 8 Display data RAM DDRAM The DDRAM stores up to 80 characters of display data represented by 8 bit character codes DDRAM locations not used for storing display data can be used as general purpose RAM The basic DDRAM to display mapping scheme is shown in Fig 2 With no display shift the characters represented by the codes in the first 12 or 24 RAM locations starting at address 00 in line 1 are displayed Subsequent lines display data starting at addresses 20 40 or 60 Hex Figures 3 and 4 show the DDRAM to display mapping scheme when the display is shifted The address range for a 1 line display is 00 to 4F for a 2 line display from 00 to 27 line 1 and 40 to 67 line 2 for
58. us transfers data between the system controller and the PCF2104x DB7 may be used as the Busy Flag signalling that internal operations are not yet completed In 4 bit operations the 4 higher order lines DB4 to DB7 are used DBO to DB3 must be left open circuit There is an internal pull up on each of the data lines Note that these pins must be left open circuit when I C bus control is used 7 1 RS register select parallel control RS selects the register to be accessed for read and write when the device is controlled by the parallel interface RS logic 0 selects the instruction register for write and the Busy Flag and Address Counter for read RS logic 1 selects the data register for both read and write There is an internal pull up on pin RS 7 2 R W read write parallel control 75 Cito C60 column driver outputs R W selects either the read R W logic 1 or write R W logic 0 operation when control is by the parallel interface There is an internal pull up on this pin These pins output the data for pairs of columns This arrangement permits optimized chip on glass COG layout for 4 line by 12 characters 7 3 E data bus clock parallel control 7 6 Rito R32 row driver outputs The E pin is set HIGH to signal the start of a read or write operation when the device is controlled by the parallel interface Data is clocked in or out of the chip on the negative edge of the clock Note that this pin must be tied to logic 0 Vs
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PHILIPS PCF2104x LCD controller/driver handbook