Home

PHILIPS P89C60X2/61X2 80C51 8-bit Flash microcontroller family handbook

1. 2003 Sep 11 8 Philips Semiconductors Product data 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM P89C60X2 61 X2 PIN NUMBER MNEMONIC PLCC MEL LQFP TYPE NAME AND FUNCTION generator circuits Crystal 2 Output from the inverting oscillator amplifier NOTE To avoid latch up effect at power on the voltage on any pin at any time must not be higher than Vcc 0 5 V or Vss 0 5 V respectively 2003 Sep 11 9 Philips Semiconductors 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM Product data P89C60X2 61 X2 SPECIAL FUNCTION REGISTERS see notes on next page DIRECT BIT ADDRESS SYMBOL OR ALTERNATIVE PORT la ACC AUXR AUXR1 B CKCON DPTR DPH DPL PCON PSW RACAP2H RACAP2L SADDR SADEN SBUF SCON SP TCON T2CON T2MOD THO THI TH2 TLO TLI TL2 TMOD WDTRST 2003 Sep 11 Accumulator Auxiliary Auxiliary 1 B register Clock Control Register Data Pointer 2 bytes Data Pointer High Data Pointer Low Interrupt Enable Interrupt Priority Interrupt Priority High Port 0 Port 1 Port 2 Port 3 Power Control Program Status Word Timer 2 Capture High Timer 2 Capture Low Slave Address Slave Address Mask Serial Data Buffer Serial Control Stack Pointer Timer Control Timer 2 Control Timer 2 Mode Control Timer High 0 Timer High 1 Timer High 2 Timer Low 0 Timer Low 1 Timer Low 2 T
2. www AllDataSheet com
3. Transmission is initiated by any instruction that uses SBUF as a S1P1 of the 10th machine cycle after write to SBUF destination register The write to SBUF signal at S6P2 also loads a 1 into the 9th position of the transmit shift register and tells the TX Reception is initiated by the condition REN 1 and R1 0 At S6P2 Control block to commence a transmission The internal timing is of the next machine cycle the RX Control unit writes the bits such that one full machine cycle will elapse between write to SBUF 11111110 to the receive shift register and in the next clock phase and activation of SEND activates RECEIVE SEND enables the output of the shift register to the alternate output RECEIVE enable SHIFT CLOCK to the alternate output function line function line of P3 0 and also enable SHIFT CLOCK to the alternate of P3 1 SHIFT CLOCK makes transitions at S3P1 and S6P1 of output function line of P3 1 SHIFT CLOCK is low during S3 S4 and every machine cycle At S6P2 of every machine cycle in which S5 of every machine cycle and high during S6 S1 and S2 At RECEIVE is active the contents of the receive shift register are 2003 Sep 11 30 Philips Semiconductors 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM shifted to the left one position The value that comes in from the right is the value that was sampled at the P3 0 pin at S5P2 of the same machine cycle As data bits come in from the right
4. 0 MOVX R0 acc where RO contains OAOH accesses the ERAM at address OAOH rather than external memory An access to external data memory locations higher than the ERAM will be performed with the MOVX DPTR instructions in the same way as in the standard 80C51 so with PO and P2 as data address bus and P3 6 and P3 7 as write and read timing signals Refer to Figure 30 With EXTRAM 1 MOVX Ri and MOVX DPTR will be similar to the standard 80051 MOVX Ri will provide an 8 bit address multiplexed with data on Port 0 and any output port pins can be used to output higher order address bits This is to provide the external paging capability MOVX DPTR will generate a 16 bit address Port 2 outputs the high order eight address bits the contents of DPH while Port 0 multiplexes the low order eight address bits DPL with data MOVX Ri and MOVX DPTR will generate either read or write signals on P3 6 WR and P3 7 RD The stack pointer SP may be located anywhere in the 256 bytes RAM lower and upper RAM internal data memory The stack may not be located in the ERAM Reset Value xxxx xx00B EXTRAM Bit 7 Function 1 Disable Enable ALE AO Operating Mode 0 ALE is emitted at a constant rate of 1 g the oscillator frequency 12 clock mode 1 3 fosc in 6 clock mode 1 ALE is active only during off chip memory access EXTRAM EXTRAM Operating Mode Internal External RAM ac
5. DATA BUS Function i Function i Function P1 5 Vss P0 6 AD6 PORT 1 A MI P1 6 NIC PO 5 AD5 P1 7 P2 0 A8 P0 4 AD4 RST P2 1 A9 P0 3 AD3 P3 0 RxD P2 2 A10 P0 2 AD2 NIC P2 3 A11 PO 1 AD1 P3 1 TxD P2 4 A12 P0 0 ADO P3 2 INTO P2 5 A13 Voc P3 3 INTT P2 6 A14 NIC P3 4 T0 P2 7 A15 P1 0 7 P3 5 T1 PSEN P1 1 1 P3 6 WR ALE P1 2 P3 7 RD NIC P1 3 XTAL2 EA Vpp P1 4 XTAL1 P0 7 AD7 i wih ADDRESS BUS AAAA YTY PORT 2 SECONDARY FUNCTIONS I SU01672 NO INTERNAL CONNECTION SU01487 PLASTIC DUAL IN LINE PACKAGE PIN FUNCTIONS T2 P1 0 Vcc T2EX P1 1 P0 0 ADO P1 2 PO 1 AD1 P0 2 AD2 5 Function i Function i Function NIC P3 4 T0 P2 7 A15 P1 0 T2 P3 5 T1 PSEN P1 1 T2EX P3 6 WR ALE P1 2 P3 7 RD NIC P1 3 XTAL2 EA Vpp P1 4 XTAL1 P0 7 AD7 P1 5 Vss P0 6 AD6 P1 6 NIC PO 5 AD5 P1 7 P2 0 A8 P0 4 AD4 RST P2 1 A9 P0 3 AD3 P3 0 RxD P2 2 A10 P0 2 AD2 NIC P2 3 A11 P0 1 AD1 P3 1 TxD P2 4 A12 P0 0 ADO P3 2 INTO P2 5 A13 Voc P3 3 INTT P2 6 A14 P0 3 AD3 P1 5 P0 4 AD4 P1 6 PO 5 AD5 P1 7 P0 6 AD6 ONoOahwWnd RST P0 7 AD7 RxD P3 0 DUAL EA Vpp IN LINE PACKAGE ALE PROG EN P2 7 A TO P3 4 P2 6 A NO INTERNAL CONNECTION SU01062 T1 P3 5 P2 5 A WR P3 6 P2 4 A RD P3 7 P2 3 A XTAL2 P2 2 A XTAL1 P2 1 A9 Vss P2 0 A8 SU01780 2003 Sep 11 7 Philips Semiconductors Product data 80C51 8 bit Flash microcontroller family 64KB Fla
6. In addition the transition at T2EX causes bit EXF2 in T2CON to be set and EXF2 like TF2 can generate an interrupt which vectors to the same location as Timer 2 overflow interrupt The Timer 2 interrupt service routine can interrogate TF2 and EXF2 to determine which event caused the interrupt The capture mode is illustrated in Figure 9 There is no reload value for TL2 and TH2 in this mode Even when a capture event occurs from T2EX the counter keeps on counting T2EX pin transitions or osc 12 12 clock Mode or osc 6 6 clock Mode pulses Auto Reload Mode Up or Down Counter In the 16 bit auto reload mode Timer 2 can be configured as either a timer or counter C T2 in T2CON then programmed to count up or down The counting direction is determined by bit DCEN Down 2003 Sep 11 Counter Enable which is located in the T2MOD register see Figure 10 After reset DCEN 0 which means Timer 2 will default to counting up If DCEN is set Timer 2 can count up or down depending on the value of the T2EX pin Figure 11 shows Timer 2 which will count up automatically since DCEN 0 In this mode there are two options selected by bit EXEN2 in T2CON register If EXEN2 0 then Timer 2 counts up to OFFFFH and sets the TF2 Overflow Flag bit upon overflow This causes the Timer 2 registers to be reloaded with the 16 bit value in RCAP2L and RCAP2H The values in RCAP2L and RCAP2H are preset by software If EXEN2 1 then a 16 bit reload can be t
7. RCLK has the same effect for the n 16 in 6 clock mode 32 in 12 clock mode serial port receive baud rate With these two bits the serial port can RCAP2H RCAP2L The content of RCAP2H and RCAP2L have different receive and transmit baud rates one generated by taken as a 16 bit unsigned integer Timer 1 the other by Timer 2 va The Timer 2 as a baud rate generator mode shown in Figure 13 is Figure 13 shows the Timer 2 in baud rate generation mode The valid only if RCLK and or TCLK 1 in T2CON register Note that a baud rate generation mode is like the auto reload mode in that a rollover in TH2 does not set TF2 and will not generate an interrupt rollover in TH2 causes the Timer 2 registers to be reloaded with the Thus the Timer 2 interrupt does not have to be disabled when 16 bit value in registers RCAP2H and RCAP2L which are preset by Timer 2 is in the baud rate generator mode Also if the EXEN2 software T2 external enable flag is set a 1 to 0 transition in T2EX The baud rates in modes 1 and 3 are determined by Timer 2 s Timer counter 2 trigger input will set EXF2 T2 external flag but overflow rate given below will not cause a reload from RCAP2H RCAP2L to TH2 TL2 Therefore when Timer 2 is in use as a baud rate generator T2EX Modes 1 and 3 Baud Rates Timer 2 Dientes Rate can be used as an additional external interrupt if needed The timer can be configured for either timer or counter operation When T
8. reset When the WDT overflows it will drive an output reset HIGH pulse at the RST pin see the note below Using the WDT To enable the WDT the user must write 01EH and 0E1H in sequence to the WDTRST SFR location OA6H When the WDT is 2003 Sep 11 enabled the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow The 14 bit counter overflows when it reaches 16383 3FFFH and this will reset the device When the WDT is enabled it will increment every machine cycle while the oscillator is running This means the user must reset the WDT at least every 16383 machine cycles To reset the WDT the user must write 01EH and 0E1h to WDTRST WDTRST is a write only register the WDT counter cannot be read or written When the WDT overflows it will generate an output RESET pulse at the reset pin see note below The RESET pulse duration is 98 x Tosc 6 clock mode 196 in 12 clock mode where Tosc 1 fosc To make the best use of the WDT it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset Philips Semiconductors Product data 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM P89C60X2 61 X2 ABSOLUTE MAXIMUM RATINGS 2 3 PARAMETER RATING UNIT Operating temperature under bias 0 to 70 Storage temperature range 65 to 150 Voltage on EA Vpp pin to Vsg Voltage on any other pin to Vss Maximum loc per I O pin Po
9. 1s shift out to the left When the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift register it flags the RX Control block to do one last shift and load SBUF At S1P1 of the 10th machine cycle after the write to SCON that cleared RI RECEIVE is cleared as RI is set More About Mode 1 Ten bits are transmitted through TxD or received through RxD a start bit 0 8 data bits LSB first and a stop bit 1 On receive the stop bit goes into RB8 in SCON In the 80C51 the baud rate is determined by the Timer 1 or Timer 2 overflow rate Figure 17 shows a simplified functional diagram of the serial port in Mode 1 and associated timings for transmit receive Transmission is initiated by any instruction that uses SBUF as a destination register The write to SBUF signal also loads a 1 into the 9th bit position of the transmit shift register and flags the TX Control unit that a transmission is requested Transmission actually commences at S1P1 of the machine cycle following the next rollover in the divide by 16 counter Thus the bit times are synchronized to the divide by 16 counter not to the write to SBUF signal The transmission begins with activation of SEND which puts the start bit at TxD One bit time later DATA is activated which enables the output bit of the transmit shift register to TxD The first shift pulse occurs one bit time after that As data bits shift out
10. 3 V for the POF to remain normally resumes program execution from where it left off up to two unaffected by the Vcc level Table 5 External Pin Status During Idle and Power Down Modes MODE PROGRAM MEMORY ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3 ae memi 1 i ba ba ba vas ide Semi 1 Fom Dea Aes Daa PPowerdown ema 0 0 Data pe Data data Powerdown Stemi 0 0 Feat Oma pata paia TIMER 0 AND TIMER 1 OPERATION Mode 0 operation is the same for Timer 0 as for Timer 1 There are two different GATE bits one for Timer 1 TMOD 7 and one for Timer Timer 0 and Timer 1 0 TMOD 3 The Timer or Counter function is selected by control bits C T in the Special Function Register TMOD These two Timer Counters have four operating modes which are selected by bit pairs M1 MO in TMOD Modes 0 1 and 2 are the same for both Timers Counters Mode 3 is different The four operating modes are described in the Mode 2 following text Mode 1 Mode 1 is the same as Mode 0 except that the Timer register is being run with all 16 bits Mode 2 configures the Timer register as an 8 bit Counter TLn with Mode 0 automatic reload as shown in Figure 6 Overflow from TLn not only sets TFn but also reloads TLn with the contents of THn which is Putting either Timer into Mode 0 makes it look like an 8048 Timer preset by software The reload leaves THn unchanged which is an 8 bit Counter wi
11. Figure 29 The Lower 128 bytes can be accessed by either direct or indirect addressing The Upper 128 bytes can be accessed by indirect addressing only The Upper 128 bytes occupy the same address space as the SFR That means they have the same address but are physically separate from SFR space When an instruction accesses an internal location above address 7FH the CPU knows whether the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction Instructions that use direct addressing access SFR space For example MOV 0A0H data accesses the SFR at location OAOH which is P2 Instructions that use indirect addressing access the Upper 128 bytes of data RAM AUXR Address 8EH Not Bit Addressable Product data P89C60X2 61X2 For example MOV RO0 acc where RO contains OAOH accesses the data byte at address OAOH rather than P2 whose address is OAOH The ERAM can be accessed by indirect addressing with EXTRAM bit cleared and MOVX instructions This part of memory is physically located on chip logically occupies the first 256 768 bytes of external data memory in the P89C60X2 61X2 With EXTRAM 0 the ERAM is indirectly addressed using the MOVX instruction in combination with any of the registers RO R1 of the selected bank or DPTR An access to ERAM will not affect ports PO P3 6 WR and P3 7 RD P2 SFR is output during external addressing For example with EXTRAM
12. T2CON 7 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software TF2 will not be set when either RCLK or TCLK 1 T2CON 6 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 1 When Timer 2 interrupt is enabled EXF2 1 will cause the CPU to vector to the Timer 2 interrupt routine EXF2 must be cleared by software EXF2 does not cause an interrupt in up down counter mode DCEN 1 T2CON 5 Receive clock flag When set causes the serial port to use Timer 2 overflow pulses for its receive clock in modes 1 and 3 RCLK 0 causes Timer 1 overflow to be used for the receive clock T2CON 4 Transmit clock flag When set causes the serial port to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3 TCLK 0 causes Timer 1 overflows to be used for the transmit clock T2CON 3 Timer 2 external enable flag When set allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port EXEN2 0 causes Timer 2 to ignore events at T2EX TR2 T2CON 2 Start stop control for Timer 2 A logic 1 starts the timer C T2 T2CON 1 Timer or counter select Timer 2 0 Internal timer OSC 12 in 12 clock mode or OSC 6 in 6 clock mode 1 External event counter falling edge triggered CP RL2 T2CON 0 Capture Reload flag When set captures will occur on negative transitions at T2EX if EXEN2 1 When clea
13. a Given or Broadcast Address In Mode 0 SM2 should be 0 Enables serial reception Set by software to enable reception Clear by software to disable reception The 9th data bit that will be transmitted in Modes 2 and 3 Set or clear by software as desired In modes 2 and 3 the 9th data bit that was received In Mode 1 if SM2 0 RB8 is the stop bit that was received In Mode 0 RB8 is not used Transmit interrupt flag Set by hardware at the end of the 8th bit time in Mode 0 or at the beginning of the stop bit in the other modes in any serial transmission Must be cleared by software Receive interrupt flag Set by hardware at the end of the 8th bit time in Mode 0 or halfway through the stop bit time in the other modes in any serial reception except see SM2 Must be cleared by software SU01628 Figure 20 SCON Serial Port Control Register 37 Philips Semiconductors Product data 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM P89C60X2 61 X2 CODICI Gry GD Cy ED E DATA BYTE ONLY IN STOP MODE 2 3 BIT SET FE BIT IF STOP BIT IS 0 FRAMING ERROR SMO TO UART MODE CONTROL elo Le E O PCON ECON Dw ape le a 0 SCON 7 SMO 1 SCON 7 FE SU01191 Figure 21 UART Framing Error Detection RECEIVED ADDRESS DO TO D7 PROGRAMMED ADDRESS COMPARATOR IN UART MODE 2 OR MODE 3 AND SM2 1 INTERRUPT IF REN 1 RB8 1 AND RECEIVED ADDRESS PROGRAMMED ADDRESS WHEN
14. activates the 6 clock mode when programmed using a parallel programmer superceding the X2 bit CKCON 0 Please also see Table 4 below Table 4 CPU clock mode 12 clock mode default FX2 clock mode bit X2 bit can only be set by CKCON 0 parallel programmer erased erased programmed 2003 Sep 11 Product data P89C60X2 61X2 Programmable Clock Out Pin A 50 duty cycle clock can be programmed to be output on P1 0 This pin besides being a regular I O pin has two alternate functions It can be programmed 1 to input the external clock for Timer Counter 2 or 2 to output a 50 duty cycle clock ranging from 61 Hz to 4 MHz at a 16 MHz operating frequency in 12 clock mode 122 Hz to 8 MHz in 6 clock mode To configure the Timer Counter 2 as a clock generator bit C T2 in T2CON must be cleared and bit T20E in T2MOD must be set Bit TR2 T2CON 2 also must be set to start the timer The Clock Out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers RCAP2H RCAP2L as shown in this equation Oscillator Frequency n x 65536 RCAP2H RCAP2L Where n 2 in 6 clock mode 4 in 12 clock mode RCAP2H RCAP2L the content of RCAP2H and RCAP2L taken as a 16 bit unsigned integer In the Clock Out mode Timer 2 roll overs will not generate an interrupt This is similar to when it is used as a baud rate generator It is possible to use Timer 2 as a baud rate generator an
15. address byte however will interrupt all slaves so that each slave can examine the received byte and see if it is being addressed The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming 2003 Sep 11 29 Product data P89C60X2 61 X2 The slaves that weren t being addressed leave their SM2s set and go on about their business ignoring the coming data bytes SM2 has no effect in Mode 0 and in Mode 1 can be used to check the validity of the stop bit In a Mode 1 reception if SM2 1 the receive interrupt will not be activated unless a valid stop bit is received Serial Port Control Register The serial port control and status register is the Special Function Register SCON shown in Figure 14 This register contains not only the mode selection bits but also the 9th data bit for transmit and receive TB8 and RB8 and the serial port interrupt bits TI and RI Baud Rates The baud rate in Mode 0 is fixed Mode 0 Baud Rate Oscillator Frequency 12 in 12 clock mode or 6 in 6 clock mode The baud rate in Mode 2 depends on the value of bit SMOD in Special Function Register PCON If SMOD 0 which is the value on reset and the port pins in 12 clock mode the baud rate is 1 64 the oscillator frequency If SMOD 1 the baud rate is 1 32 the oscillator frequency In 6 clock mode the baud rate is 1 32 or 1 16 the oscillator frequency respectively Mode 2 Baud Rate 2SMOD n
16. enable bit SU01522 Figure 24 Interrupt Enable IE Register Address 0B8H Reset Value xx000000B Bit Addressable 7 6 5 PT2 PS Priority Bit 1 assigns higher priority Priority Bit 0 assigns lower priority SYMBOL FUNCTION Not implemented reserved for future use Not implemented reserved for future use PT2 Timer 2 interrupt priority bit PS Serial Port interrupt priority bit PT1 Timer 1 interrupt priority bit PX1 External interrupt 1 priority bit PTO Timer 0 interrupt priority bit PXO External interrupt 0 priority bit 8U01523 Figure 25 Interrupt Priority IP Register Address B7H Reset Value xx000000B Bit Addressable 7 6 5 4 0 PT2H PSH Priority Bit 1 assigns higher priority Priority Bit 0 assigns lower priority SYMBOL FUNCTION Not implemented reserved for future use Not implemented reserved for future use Timer 2 interrupt priority bit high Serial Port interrupt priority bit high Timer 1 interrupt priority bit high External interrupt 1 priority bit high Timer 0 interrupt priority bit high External interrupt 0 priority bit high SUDIS24 Figure 26 Interrupt Priority HIGH IPH Register 2003 Sep 11 40 Philips Semiconductors Product data 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM P89C60X2 61 X2 c1 la c3 gt C4 gt c5 S6 e I
17. o 2003 Sep 11 47 Philips Semiconductors Product data 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM P89C60X2 61 X2 AC ELECTRICAL CHARACTERISTICS 56 CLOCK MODE Tamb 0 C to 70 C Vee 5 V 10 Vss 0 V VARIABLE CLOCK 20 MHz CLOCK UNIT 5 Li CE 2 EA E ZE ii 2icrer 65 2teLer 65 pas Ooo EK See 15 i is ES Ed Input instruction float after P 0 5toLcL 20 Address to valid instruction in 2 5toLcL 80 res PSEN low to address float Data Memory ME EE i 2 Ste1c1 90 I N o EG Cee DS am Mao ino 02 adresstovaiddaein A LENTE Cum 023 AE owon orno ran sacos fa 1 Cam 2 39 AdsressvalatoWRioworFD ow faoa fe Cow 3 pata varato Wi vanstio osa fo Five 9 Joseon Vossa fs Je own 3 Data vanto wann sec f fe Paz 82 Dowes Jo fo CAI alo o External Clock Cox E CT E fassa I fe Dao 85 towtime fe Trate fs Foun E Risetim 5 fn Promo 85 frame TO TT Shift Register Poa e __ Serialporciockeycietime Ta fe fs row 84 Output aata setup to clock ising edge ti Jr fs ox oa Output data hola after clock risingedge aro fo fs box 84 Mputdata ol a er clock rising edge p Ta fr txuov 34 Clock rising edge to input data vaid Beat 17 fhs NOTES 1 Parameters are valid over operating temperature range unless otherwise specified 2 Load capacitance for port 0 A
18. pF Under steady state non transient conditions lo must be externally limited as follows Maximum lo per port pin 15 mA Maximum lo per 8 bit port 26 mA Maximum total Io for all outputs 71 mA If lo exceeds the test condition Vo may exceed the related specification Pins are not guaranteed to sink current greater than the listed test conditions 9 ALE is tested to Vop1 except when ALE is off then Voy is the voltage specification 10 Pin capacitance is characterized but not tested Pin capacitance is less than 25 pF Pin capacitance of ceramic package is less than 15 pF except EA is 25 pF 11 To improve noise rejection a nominal 100 ns glitch rejection circuitry has been added to the RST pin and a nominal 15 ns glitch rejection circuitry has been added to the INTO and INT1 pins Previous devices provided only an inherent 5 ns of glitch rejection 8 5 0 62 x FREQ MHz mA 3 5 0 18 x FREQ MHz mA OND 2003 Sep 11 46 Philips Semiconductors Product data 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM P89C60X2 61 X2 AC ELECTRICAL CHARACTERISTICS da CLOCK MODE Tamb 0 C to 70 C Vec 5 V 10 Vss 0 V SYMBOL hi PARAMETER VARIABLE VARIABLE CLOCK 33 MHz CLOCK4 Fe Mao Ja osser tese CS CCA KK TTI 7 EE Cm 31 Adsress vaio ato fr TS Cu 31 seres pol aer ALE ton faa fe un Ja ateomiovaidinsmuetonn Maas Cum Ja aeomoPsenom aes een ST PSENpuse
19. portion is exactly the same as in Mode 1 The transmit portion differs from Mode 1 only in the 9th bit of the transmit shift register Transmission is initiated by any instruction that uses SBUF as a destination register The write to SBUF signal also loads TB8 into the 9th bit position of the transmit shift register and flags the TX Control unit that a transmission is requested Transmission commences at S1P1 of the machine cycle following the next rollover in the divide by 16 counter Thus the bit times are synchronized to the divide by 16 counter not to the write to SBUF signal The transmission begins with activation of SEND which puts the start bit at TxD One bit time later DATA is activated which enables the output bit of the transmit shift register to TxD The first shift pulse occurs one bit time after that The first shift clocks a 1 the stop bit into the 9th bit position of the shift register Thereafter only zeros are clocked in Thus as data bits shift out to the right zeros are clocked in from the left When TB8 is at the output position of the shift register then the stop bit is just to the left of TB8 and all positions to the left of that contain zeros This condition flags the TX Control unit to do one last shift and then deactivate SEND and set TI This occurs at the 11th divide by 16 rollover after write to SUBF Reception is initiated by a detected 1 to 0 transition at RxD For this purpose RxD i
20. sequence determines which request is serviced Thus within each priority level there is a second priority structure determined by the polling sequence as follows Source 1 IEO External Int 0 TFO Timer 0 IE1 External Int 1 TF1 Timer 1 RI TI UART TF2 EXF2 Timer 2 Priority Within Level highest OB lowest Note that the priority within level structure is only used to resolve simultaneous requests of the same priority level The IP and IPH registers contain a number of unimplemented bits User software should not write 1s to these positions since they may be used in other 80C51 Family products How Interrupts Are Handled The interrupt flags are sampled at S5P2 of every machine cycle The samples are polled during the following machine cycle If one of the flags was in a set condition at S5P2 of the preceding cycle the polling cycle will find it and the interrupt system will generate an LCALL to the appropriate service routine provided this hardware generated LCALL is not blocked by any of the following conditions 1 An interrupt of equal or higher priority level is already in progress 2 The current polling cycle is not the final cycle in the execution of the instruction in progress 3 The instruction in progress is RETI or any write to the IE or IP registers Any of these three conditions will block the generation of the LCALL to the interrupt service routine Condition 2 ensures that t
21. to the right zeros are clocked in from the left When the MSB of the data byte is at the output position of the shift register then the 1 that was initially loaded into the 9th position is just to the left of the MSB and all positions to the left of that contain zeros This condition flags the TX Control unit to do one last shift and then deactivate SEND and set TI This occurs at the 10th divide by 16 rollover after write to SBUF Reception is initiated by a detected 1 to 0 transition at RxD For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established When a transition is detected the divide by 16 counter is immediately reset and 1FFH is written into the input shift register Resetting the divide by 16 counter aligns its rollovers with the boundaries of the incoming bit times The 16 states of the counter divide each bit time into 16ths At the 7th 8th and 9th counter states of each bit time the bit detector samples the value of RxD The value accepted is the value that was seen in at least 2 of the 3 samples This is done for noise rejection If the value accepted during the first bit time is not 0 the receive circuits are reset and the unit goes back to looking for another 1 to 0 transition This is to provide rejection of false start bits If the start bit proves valid it is shifted into the input shift register and reception of the rest of the frame will proceed As data bits come in from th
22. to them are pulled high by the internal pull ups and can be used as inputs As inputs port 2 pins that are externally being pulled low will source current because of the internal pull ups See DC Electrical Characteristics 114 Port 2 emits the high order address byte during fetches from external program memory and during accesses to external data memory that use 16 bit addresses MOVX DPTR In this application it uses strong internal pull ups when emitting 1s During accesses to external data memory that use 8 bit addresses MOV Ri port 2 emits the contents of the P2 special function register Some Port 2 pins receive the high order address bits during Flash programming and verification P3 0 P3 7 Port 3 Port 3 is an 8 bit bidirectional I O port with internal pull ups Port 3 pins that have 1s written to them are pulled high by the internal pull ups and can be used as inputs As inputs port 3 pins that are externally being pulled low will source current because of the pull ups See DC Electrical Characteristics 14 Port 3 also serves the special features of the 80C51 family as listed below RxD P3 0 Serial input port TxD P3 1 Serial output port INTO P3 2 External interrupt INT1 P3 3 External interrupt TO P3 4 Timer 0 external input T1 P3 5 Timer 1 external input WR P3 6 External data memory write strobe RD P3 7 External data memory read strobe RST Reset A high on this pin for two machine cycles w
23. 0 INTEGRATED CIRCUITS DATA SHEET P89C60X2 61X2 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM Product data 2003 Sep 11 Supersedes data of 2002 Jul 23 Philips PHILIPS Semiconductors PH I LI DS Philips Semiconductors Product data E 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM P89C60X2 61X2 DESCRIPTION In addition the devices are static designs which offer a wide range The Philips microcontrollers described in this data sheet are of operating frequencies down to zero Two software selectable high performance static 80C51 designs They are manufactured in modes of power reduction idle mode and power down mode an advanced CMOS process and contain a non volatile Flash are available The idle mode freezes the CPU while allowing the program memory that is programmable in parallel via a parallel RAM timers serial port and interrupt system to continue programmer or In System Programmable ISP via boot loader functioning The power down mode saves the RAM contents but They support both 12 clock and 6 clock operation freezes the oscillator causing all other chip functions to be inoperative Since the design is static the clock can be stopped without loss of user data Then the execution can be resumed from the point the clock was stopped The P89C60X2 and P89C61X2 contain 512 bytes RAM and 1024 bytes RAM respectively 32 I O lines three 16 bit counter timers a six source fou
24. 2 Overflow Rate 16 If Timer 2 is being clocked internally the baud rate is Baud Rate fosc Baud Rate 1 165536 RCAP2H RCAP2D Where n 16 in 6 clock mode 32 in 12 clock mode fosc Oscillator Frequency To obtain the reload value for RCAP2H and RCAP2L the above equation can be rewritten as OSC RCAP2H RCAP2L 65536 7 x Baud Fe 2003 Sep 11 28 Product data P89C60X2 61X2 Timer Counter 2 Set up Except for the baud rate generator mode the values given for T2CON do not include the setting of the TR2 bit Therefore bit TR2 must be set separately to turn the timer on See Table 8 for set up of Timer 2 as a timer Also see Table 9 for set up of Timer 2 as a counter Table 8 Timer 2 as a Timer 0 T2ON EXTERNAL CONTROL 2 SN ERNA CONTROL 1 Baud rate generator receive and transmit same baud rate Transmit only Table 9 Timer 2 as a Counter TMOD EXTERNAL CONTROL Note 2 a erma CONTROL Note 1 em f om om Auto Reload NOTES 1 Capture reload occurs only on timer counter overflow 2 Capture reload occurs on timer counter overflow and a 1 to 0 transition on T2EX P1 1 pin except when Timer 2 is used in the baud rate generator mode Philips Semiconductors 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM FULL DUPLEX ENHANCED UART Standard UART operation The serial port is full duplex meaning it can trans
25. 20MHz Internal reset pull down resistor Pin capacitance 0 except EA 1 Typical ratings are not guaranteed The values listed are at room temperature 5 V 2 Capacitive loading on ports O and 2 may cause spurious noise to be superimposed on the Vor s of ALE and ports 1 and 3 The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1 to 0 transitions during bus operations In the worst cases capacitive loading gt 100 pF the noise pulse on the ALE pin may exceed 0 8 V In such cases it may be desirable to qualify ALE with a Schmitt Trigger or use an address latch with a Schmitt Trigger STROBE input lo can exceed these conditions provided that no single output sinks more than 5 mA and no more than two outputs exceed the test conditions 3 Capacitive loading on ports O and 2 may cause the Voy on ALE and PSEN to momentarily fall below the Vcc 0 7 specification when the address bits are stabilizing 4 Pins of ports 1 2 and 3 source a transition current when they are being externally driven from 1 to 0 The transition current reaches its maximum value when Vin is approximately 2 V 5 See Figures 39 through 42 for log test conditions and Figure 38 for Icc vs Frequency 12 clock mode characteristics Active mode Icc MAX Idle mode Icc MAX This value applies to Tamb 0 C to 70 C Load capacitance for port 0 ALE and PSEN 100 pF load capacitance for all other outputs 80
26. 26 Figure 14 Serial Port Control SCON Register fosc Mode 12 clock mode 6 clock mode CIT Mode Reload Value Xx Mode 0 Max 1 67 MHz 3 34 MHz 20 MHz Mode 2 Max 625 k 1250 k 20 MHz Mode 1 3 Max 104 2 k 208 4 k 20 MHz Mode 1 3 19 2k 38 4 k 11 059 MHz 9 6 k 19 2k 11 059 MHz 4 8 k 9 6 k 11 059 MHz 2 4 k 4 8k 11 059 MHz 1 2k 2 4k 11 059 MHz 137 5 275 11 986 MHz 110 220 6 MHz 110 220 12 MHz Figure 15 Timer 1 Generated Commonly Used Baud Rates 4 X 1 1 1 0 0 0 0 0 0 o0oD0o0o0o0o0oo0o0 X X NNNNNNNINX X o More About Mode 0 S6P2 of every machine cycle in which SEND is active the contents Serial data enters and exits through RxD TxD outputs the shift of the transmit shift are shifted to the right one position clock 8 bits are transmitted received 8 data bits LSB first The baud rate is fixed at 1 12 the oscillator frequency 12 clock mode or 1 6 the oscillator frequency 6 clock mode As data bits shift out to the right zeros come in from the left When the MSB of the data byte is at the output position of the shift register then the 1 that was initially loaded into the 9th position is just to the Figure 16 shows a simplified functional diagram of the serial port in left of the MSB and all positions to the left of that contain zeros Mode 0 and associated timing This condition flags the TX Control block to do one last shift and then deactivate SEND and set T1 Both of these actions occur at
27. 51 SFRs Reserved bits see note above Reset value depends on reset source GF 2003 Sep 11 11 Philips Semiconductors 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM FLASH EPROM MEMORY GENERAL DESCRIPTION The P89C60X2 61X2 Flash memory augments EPROM functionality with in circuit electrical erasure and programming The Flash can be read and written as bytes The Chip Erase operation will erase the entire program memory The Block Erase function can erase any Flash block In system programming ISP and standard parallel programming are both available On chip erase and write timing generation contribute to a user friendly programming interface The P89C60X2 61 X2 Flash reliably stores memory contents even after 10 000 erase and program cycles The cell is designed to optimize the erase and programming mechanisms In addition the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling The P89C60X2 61 X2 uses a 5 V Vpp supply to perform the Program Erase algorithms 12 V tolerant FEATURES Flash EPROM internal program memory with Block Erase e Internal 1 kbyte fixed BootROM containing low level in system programming routines and a default serial loader Loader in BootROM allows in system programming via the serial port Up to 64 kbytes external program memory if the internal program memory is disabled E
28. 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM P89C60X2 61 X2 INSTR IN P2 0 P2 7 OR A8 A15 FROM DPF A0 A15 FROM PCH Figure 33 External Data Memory Write Cycle SU00026 lt XLXL gt CLOCK txHax tavxH WRITE TO SBUF gt txHDX txHpv gt 2 TI a TV OC 0 KD CLEAR RI SET RI SU00027 Figure 34 Shift Register Mode Timing Voc 0 5 CC 0 7VCC 0 2VC0C 0 1 tcHoL gt SU00009 Figure 35 External Clock Drive 2003 Sep 11 50 Philips Semiconductors 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM Voc 0 5 0 2VCC 0 9 0 2Vec 0 1 0 45V cc NOTE AC inputs during testing are driven at Vcc 0 5 for a logic 1 and 0 45V for a logic 0 Timing measurements are made at Vj min for a logic 1 and Vi max for a logic 0 SU00717 Figure 36 AC Testing Input Output Product data P89C60X2 61 X2 VLOAD 0 1V A wo TIMING LOAD se REFERENCE Leg POINTS a VLOAD 0 1V VOL 0 1V NOTE For timing purposes a port is no longer floating when a 100mV change from load voltage occurs and begins to float when a 100mV change from the loaded VoH VoL level occurs lop loL gt 20mA SU00718 Figure 37 Float Waveform P89C60X2 61X2 MAXIMUM Icc ACTIVE TYPICAL Icc ACTIVE MAXIMUM IDLE TYPICAL IDLE 24 28 Frequ
29. A 0 Programming and erase voltage 5 V 12 V tolerant Read Programming Erase using ISP Byte Programming 8 us Typical erase times Block Erase 4 kbytes in 3 seconds Full chip erase in 15 seconds Parallel programming with 87C51 compatible hardware interface to programmer 2003 Sep 11 12 Product data P89C60X2 61X2 e Programmable security for the code in the Flash 10 000 minimum erase program cycles for each byte 10 year minimum data retention FLASH PROGRAMMING AND ERASURE There are two methods of erasing or programming of the Flash memory that may be used First the on chip ISP boot loader may be invoked Second the Flash may be programmed or erased using parallel method by using a commercially available EPROM programmer The parallel programming method used by these devices is similar to that used by EPROM 87C51 but it is not identical and the commercially available programmer will need to have support for these devices FLASH MEMORY CHARACTERISTICS Flash User Code Memory Organization The P89C60X2 61X2 contains 64 kbytes Flash user code program memory organized into 4 kbyte blocks see Figure 1 Boot ROM When the microcontroller programs its Flash memory during ISP all of the low level details are handled by code that is contained in a 1 kbyte BootROM BootROM operations include erase block program byte verify byte program security bit etc Clock Mode The clock m
30. C60X2 61 X2 SCON Address 98H Reset Value 00H Bit Addressable VA 6 5 4 3 SMO SM1 SM2 REN TB8 Where SMO SM1 specify the serial port mode as follows SMO SM1 Mode Description Baud Rate shift register fosc 12 12 clock mode or fosc 6 6 clock mode 8 bit UART variable 9 bit UART fosc 64 or fosc 32 12 clock mode or fosc 32 or fosc 16 6 clock mode 9 bit UART variable Enables the multiprocessor communication feature in Modes 2 and 3 In Mode 2 or 3 if SM2 is set to 1 then RI will not be activated if the received 9th data bit RB8 is 0 In Mode 1 if SM2 1 then RI will not be activated if a valid stop bit was not received In Mode 0 SM2 should be 0 Enables serial reception Set by software to enable reception Clear by software to disable reception The 9th data bit that will be transmitted in Modes 2 and 3 Set or clear by software as desired In Modes 2 and 3 is the 9th data bit that was received In Mode 1 it SM2 0 RB8 is the stop bit that was received In Mode 0 RB8 is not used Transmit interrupt flag Set by hardware at the end of the 8th bit time in Mode 0 or at the beginning of the stop bit in the other modes in any serial transmission Must be cleared by software Receive interrupt flag Set by hardware at the end of the 8th bit time in Mode 0 or halfway through the stop bit time in the other modes in any serial reception except see SM2 Must be cleared by software SU016
31. DESCRIPTION eve LB1 MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory LB2 Program verification is disabled LB3 External execution is disabled NOTE 1 The security lock bits are independent 2003 Sep 11 18 Philips Semiconductors 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM OSCILLATOR CHARACTERISTICS Using the oscillator XTAL1 and XTAL2 are the input and output respectively of an inverting amplifier The pins can be configured for use as an on chip oscillator as shown in the logic symbol To drive the device from an external clock source XTAL1 should be driven while XTAL2 is left unconnected However minimum and maximum high and low times specified in the data sheet must be observed Clock Control Register CKCON This device provides control of the 6 clock 12 clock mode by both an SFR bit bit X2 in register CKCON and a Flash bit bit FX2 located in the Security Block When X2 is 0 12 clock mode is activated By setting this bit to 1 the system is switching to 6 clock mode Having this option implemented as SFR bit it can be accessed anytime and changed to either value Changing X2 from 0 to 1 will result in executing user code at twice the speed since all system time intervals will be divided by 2 Changing back from 6 clock to 12 clock mode will slow down running code by a factor of 2 The Flash clock control bit FX2
32. G PRIORITY REQUEST BITS HARDWARE CLEAR VECTOR ADDRESS N L Y T 03H NOTES 1 L Level activated 2 T Transition activated Reduced EMI Mode The AO bit AUXR 0 in the AUXR register when set disables the ALE output unless the CPU needs to perform an off chip memory access AUXR 8EH 7 6 5 4 3 2 1 0 p femm o AUXR 0 AO Turns off ALE output AUXR 1 EXTRAM Controls external data memory access Dual DPTR The dual DPTR structure see Figure 28 enables a way to specify the address of an external data memory location There are two 16 bit DPTR registers that address the external memory and a single bit called DPS AUXR1 bit0 that allows the program code to switch between them New Register Name AUXR1 SFR Address A2H Reset Value xxx000x0B AUXR1 A2H 7 6 5 4 3 2 1 0 Locks dice ls Lee Locke des Where DPS AUXR1 bit0 Switches between DPTRO and DPTR1 Select Reg DPS DPTRO 0 DPTRI 1 The DPS bit status should be saved by software when switching between DPTRO and DPTR1 2003 Sep 11 The GF2 bit is a general purpose user defined flag Note that bit 2 is not writable and is always read as a zero This allows the DPS bit to be quickly toggled simply by executing an INC AUXRI1 instruction without affecting the GF2 bit DPH DPL 83H 82H EXTERNAL DATA MEMORY SU00745A Figure 28 DPTR Instructions The instructions that refer to DPTR refer to the da
33. ITS C T2 1 CONTROL RELOAD TRANSITION DETECTOR T2EX PIN Product data P89C60X2 61 X2 3 gt TIMER 2 INTERRUPT CONTROL n 6 in 6 clock mode n 12 in 12 clock mode EXEN2 Figure 11 Timer 2 in Auto Reload Mode DCEN 0 DOWN COUNTING RELOAD VALUE OVERFLOW SU01623 TOGGLE TR2 RCAP2L RCAP2H n 6 in 6 clock mode n 12 in 12 clock mode UP COUNTING RELOAD VALUE Figure 12 Timer 2 Auto Reload Mode DCEN 1 2003 Sep 11 26 COUNT DIRECTION 1 UP 0 DOWN T2EX PIN SU01624 Philips Semiconductors Product data 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM P89C60X2 61 X2 Timer 1 Overflow n 1 in 6 clock mode n 2 in 12 clock mode Control Transition Detector RCAP2L RCAP2H Control T2EX Pin TN To EXF2 Timer 2 3 1 Interrupt EXEN2 E Note availability of additional external interrupt SU01625 Figure 13 Timer 2 in Baud Rate Generator Mode Baud Rate Generator Mode Modes 1 and 3 Baud Rates Bits TCLK and or RCLK in T2CON Table 6 allow the serial port Oscillator Frequency transmit and receive baud rates to be derived from either Timer 1 or n x 65536 RCAP2H RCAP2L Timer 2 When TCLK 0 Timer 1 is used as the serial port transmit Where baud rate generator When TCLK 1 Timer 2 is used as the serial Far port transmit baud rate generator
34. LE and PSEN 100 pF load capacitance for all other outputs 80 pF 3 Interfacing the microcontroller to devices with float times up to 45 ns is permitted This limited bus contention will not cause damage to Port 0 drivers 4 Parts are tested to 2 MHz but are guaranteed to operate down to 0 Hz 2003 Sep 11 48 Philips Semiconductors 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM EXPLANATION OF THE AC SYMBOLS Each timing symbol has five characters The first character is always t time The other characters depending on their positions indicate the name of a signal or the logical status of that signal The designations are A Address C Clock D Input data H Logic level high I Instruction program memory contents L Logic level low or ALE Product data P89C60X2 61 X2 P PSEN Q Output data R RD signal t Time V Valid W WR signal X No longer a valid logic level Z Float Examples tav Time for address valid to ALE low tip Time for ALE low to PSEN low lt tHL NP E tPLPH lt tuv gt SU00006 Figure 31 External Program Memory Read Cycle A0 A7 FROM RI OR DPL gt tavov gt P2 0 P2 7 OR A8 A15 FROM DPF INSTR IN A0 A15 FROM PCH SU00025 Figure 32 External Data Memory Read Cycle 2003 Sep 11 Philips Semiconductors Product data 80C51
35. MIN _2 20030911 Preliminary data 9397 750 11927 ECN 853 2400 30250 of 25 August 2003 Modifications Added Watchdog Timer feature Added DIP40 package 20020723 Preliminary data 9397 750 10131 Data sheet status Product Definitions 1 Level Data sheet status tatus 2 3 Objective data Development This data sheet contains data from the objective specification for product development Philips Semiconductors reserves the right to change the specification in any manner without notice Il Preliminary data Qualification This data sheet contains data from the preliminary specification Supplementary data will be published at a later date Philips Semiconductors reserves the right to change the specification without notice in order to improve the design and supply the best possible product Ill Product data Production This data sheet contains data from the product specification Philips Semiconductors reserves the right to make changes at any time in order to improve the design manufacturing and supply Relevant changes will be communicated via a Customer Product Process Change Notification CPCN 1 Please consult the most recently issued data sheet before initiating or completing a design 2 The product status of the device s described in this data sheet may have changed since this data sheet was published The latest information is available on the Internet at URL http www semiconductors phil
36. OWN ADDRESS RECEIVED CLEAR SM2 TO RECEIVE DATA BYTES WHEN ALL DATA BYTES HAVE BEEN RECEIVED SET SM2 TO WAIT FOR NEXT ADDRESS SU00045 Figure 22 UART Multiprocessor Communication Automatic Address Recognition 2003 Sep 11 38 Philips Semiconductors 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM Interrupt Priority Structure Interrupt Sources TF2 EXF2 SU01521 Figure 23 Interrupt Sources Interrupts The devices described in this data sheet provide six interrupt sources These are shown in Figure 23 The External Interrupts INTO and INT1 can each be either level activated or transition activated depending on bits ITO and IT1 in Register TCON The flags that actually generate these interrupts are bits IEO and IE1 in TCON When an external interrupt is generated the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transition activated If the interrupt was level activated then the external requesting source is what controls the request flag rather than the on chip hardware The Timer 0 and Timer 1 Interrupts are generated by TFO and TF1 which are set by a rollover in their respective Timer Counter registers except see Timer 0 in Mode 3 When a timer interrupt is generated the flag that generated it is cleared by the on chip hardware when the service routine is vectored to The Serial Por
37. SSUE DATE VERSION JEDEC JEITA PROJECTION 2003 Sep 11 53 Philips Semiconductors Product data 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM P89C60X2 61 X2 DIP40 plastic dual in line package 40 leads 600 mil SOT129 1 seating plane scale DIMENSIONS inch dimensions are derived from the original mm dimensions Ai 2 A Az max A max b bi e eq L M E M H WwW max 1 70 0 53 0 36 52 5 14 1 3 60 15 80 17 42 0 067 0 021 0 014 2 067 0 56 0 14 0 62 0 69 Note 1 Plastic or metal protrusions of 0 25 mm 0 01 inch maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC JEITA PROJECTION SOT 129 1 051G08 MO 015 SC 511 40 E eae ISSUE DATE 2003 Sep 11 54 Philips Semiconductors Product data 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM P89C60X2 61 X2 LQFP44 plastic low profile quad flat package 44 leads body 10 x 10 x 1 4 mm SOT389 1 a A detail X DIMENSIONS mm are the original dimensions Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION PROJECTION ISSUE DATE IEC 2003 Sep 11 55 Philips Semiconductors Product data 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM P89C60X2 61 X2 REVISION HISTORY en
38. Write Function ff subfunction code ss selection code dd data input as needed cs checksum Subfunction Code 04 Set Status Byte to 00h ff 04 ss don t care Example 020000030400F7 set status byte to 00h device executes user code after Reset Subfunction Code 05 Program Security Bits ff 05 ss 00 program security bit 1 inhibit writing to Flash 01 program security bit 2 inhibit Flash verify 02 program security bit 3 disable external memory Example 020000030501F5 program security bit 2 Subfunction Code 06 Program Flash X2 bit 2003 Sep 11 15 Philips Semiconductors Product data 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM P89C60X2 61 X2 RECORD TYPE COMMAND DATA FUNCTION 03 cont Subfunction Code 07 Full Chip Erase Erases all blocks security bits and sets status byte to default values 07 SS don t care dd don t care Example 0100000307F5 full chip erase Subfunction Code 0C Erase 4k blocks 0C ss block code lock lock lock lock lock lock lock lock lock lock lock lock lock shown below Ok 4k OOH 4k 8k 10H 8k 12k 20H 12k 16k 30H 16k 20k 40H 20k 24k 50H 24k 28k 60H 28k 32k 70H 32k 36k 80H 36k 40k 90H 40k 44k AOH 44k 48k BOH 48k 52k COH lock 52k 56k DOH lock 56k 60k EOH lock 15 60k 64k FOH a SON NNN NSN SS 0OJAUDSWNEOP s ss her WNRO s p D b b b b b b b b
39. X Oscillator Frequency Where n 64 in 12 clock mode 32 in 6 clock mode The baud rates in Modes 1 and 3 are determined by the Timer 1 or Timer 2 overflow rate Using Timer 1 to Generate Baud Rates When Timer 1 is used as the baud rate generator T2CON RCLK 0 T2CON TCLK 0 the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD as follows Mode 1 3 Baud Rate 2SMOD n x Timer 1 Overflow Rate Where n 32 in 12 clock mode 16 in 6 clock mode The Timer 1 interrupt should be disabled in this application The Timer itself can be configured for either timer or counter operation and in any of its 3 running modes In the most typical applications it is configured for timer operation in the auto reload mode high nibble of TMOD 0010B In that case the baud rate is given by the formula Mode 1 3 Baud Rate 2SMOD Oscillator Frequency n 12 x 256 TH1 Where n 32 in 12 clock mode 16 in 6 clock mode One can achieve very low baud rates with Timer 1 by leaving the Timer 1 interrupt enabled and configuring the Timer to run as a 16 bit timer high nibble of TMOD 0001B and using the Timer 1 interrupt to do a 16 bit software reload Figure 15 lists various commonly used baud rates and how they can be obtained from Timer 1 Philips Semiconductors Product data 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM P89
40. a small connector needs to be available to interface your application to an external circuit in order to use this feature The Vpp supply should be adequately decoupled and Vpp not allowed to exceed datasheet limits Free ISP software is available from the Embedded Systems Academy FlashMagic 1 Direct your browser to the following page http www esacademy com software flashmagic 2 Download Flashmagic 3 Execute flashmagic exe to install the software Using the In System Programming ISP The ISP feature allows for a wide range of baud rates to be used in your application independent of the oscillator frequency It is also adaptable to a wide range of oscillator frequencies This is accomplished by measuring the bit time of a single bit in a received character This information is then used to program the baud rate in terms of timer counts based on the oscillator frequency The ISP feature requires that an initial character an uppercase U be sent to the P89C60X2 61X2 to establish the baud rate The ISP firmware provides auto echo of received characters Once baud rate initialization has been performed the ISP firmware will only accept Intel Hex type records Intel Hex records consist of ASCII characters used to represent hexadecimal values and are summarized below 2003 Sep 11 NNAAAARRDD DDCC lt crlf gt In the Intel Hex record the NN represents the number of data bytes in the record The P89C60X2 61 X2 w
41. alled Mode 1 In this mode the RI flag will be set if SM2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast address Mode 0 is the Shift Register mode and SM2 is ignored Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses All of the slaves may be contacted by using the Broadcast address Two special Function Registers are used to define the slave s address SADDR and the address mask SADEN SADEN is used to define which bits in the SADDR are to be used and which bits are don t care The SADEN mask can be logically ANDed with the SADDR to create the Given address which the master will use for addressing each of the slaves Use of the Given address allows multiple slaves to be recognized while excluding others The following examples will help to show the versatility of this scheme Slave 0 SADDR 1100 0000 SADEN 1111 1101 Given 1100 00X0 2003 Sep 11 36 Product data P89C60X2 61 X2 Slave 1 SADDR 1100 0000 SADEN 1111 1110 Given 1100 000X In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves Slave 0 requires a 0 in bit 0 and it ignores bit 1 Slave 1 requires a 0 in bit 1 and bit 0 is ignored unique address for Slave 0 would be 1100 0010 since sla
42. b b b b b b b b Example 020000030C20CF erase 4k block 2 Display Device Data or Blank Check Record type 04 causes the contents of the entire Flash array to be sent out the serial port in a formatted display This display consists of an address and the contents of 16 bytes starting with that address No display of the device contents will occur if security bit 2 has been programmed Data to the serial port is initiated by the reception of any character and terminated by the reception of any character General Format of Function 04 05xxxx04sssseeeeffcc Where 05 number of bytes hex in record XXXX required field but value is a don t care 04 Display Device Data or Blank Check function code ssss starting address eeee ending address ff subfunction 00 display data 01 blank check 02 display data in data block valid addresses 0001 OFFFH es checksum Example 1 0500000440004FFF0069 display 4000 4FFF Example 2 0500000400000FFF02E7 display data in data block the data at address 0000 is invalid 2003 Sep 11 16 Philips Semiconductors Product data 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM P89C60X2 61 X2 RECORD TYPE COMMAND DATA FUNCTION Miscellaneous Read Functions General Format of Function 05 02xxxx05ffsscc Where 02 number of bytes hex in record XXXX required field but value is a don t care 05 Miscellaneous Read function code ffss subfunct
43. bit INTn Pin d 6 in 6 clock mode d 12 in 12 clock mode SU01619 Figure 6 Timer Counter 0 1 Mode 2 8 Bit Auto Reload 2003 Sep 11 22 Philips Semiconductors 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM Product data P89C60X2 61 X2 Interrupt Timer 0 Gate bit INTO Pin Control d 6 in 6 clock mode d 12 in 12 clock mode Interrupt Control SU01620 Figure 7 Timer Counter 0 Mode 3 Two 8 Bit Counters TIMER 2 OPERATION Timer 2 Timer 2 is a 16 bit Timer Counter which can operate as either an event timer or an event counter as selected by C T2 in the special function register T2CON see Figure 8 Timer 2 has three operating modes Capture Auto reload up or down counting and Baud Rate Generator which are selected by bits in the T2CON as shown in Table 6 Capture Mode In the capture mode there are two options which are selected by bit EXEN2 in T2CON If EXEN2 0 then timer 2 is a 16 bit timer or counter as selected by C T2 in T2CON which upon overflowing sets bit TF2 the timer 2 overflow bit This bit can be used to generate an interrupt by enabling the Timer 2 interrupt bit in the IE register If EXEN2 1 Timer 2 operates as described above but with the added feature that a 1 to 0 transition at external input T2EX causes the current value in the Timer 2 registers TL2 and TH2 to be captured into registers RCAP2L and RCAP2H respectively
44. cess using MOVX Ri DPTR 0 Internal ERAM access using MOVX Ri DPTR 1 External data memory access Not implemented reserved for future use NOTE User software should not write 1s to reserved bits These bits may be used in future 8051 family products to invoke new features In that case the reset or inactive value of the new bit will be 0 and its active value will be 1 The value read from a reserved bit is indeterminate SU01613 Figure 29 AUXR Auxiliary Register 2003 Sep 11 Philips Semiconductors 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM UPPER 128 BYTES INTERNAL RAM ERAM 256 or 768 BYTES LOWER 128 BYTES INTERNAL RAM Product data P89C60X2 61 X2 SPECIAL EXTERNAL FUNCTION DATA REGISTER MEMORY SU01293 Figure 30 Internal and External Data Memory Address Space with EXTRAM 0 HARDWARE WATCHDOG TIMER ONE TIME ENABLED WITH RESET OUT FOR P89C51RA2 RB2 RC2 RD2xx The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset The WDT consists of a 14 bit counter and the Watchdog Timer reset WDTRST SFR The WDT is disabled at reset To enable the WDT the user must write 01EH and 0E1H in sequence to the WDTRST SFR location OA6H When the WDT is enabled it will increment every machine cycle while the oscillator is running and there is no way to disable the WDT except through reset either hardware reset or WDT overflow
45. d a clock generator simultaneously Note however that the baud rate and the Clock Out frequency will be the same RESET A reset is accomplished by holding the RST pin HIGH for at least two machine cycles 24 oscillator periods in 12 clock and 12 oscillator periods in 6 clock mode while the oscillator is running To insure a reliable power up reset the RST pin must be high long enough to allow the oscillator time to start up normally a few milliseconds plus two machine cycles unless it has been set to 6 clock operation using a parallel programmer LOW POWER MODES Stop Clock Mode The static design enables the clock speed to be reduced down to 0 MHz stopped When the oscillator is stopped the RAM and Special Function Registers retain their values This mode allows step by step utilization and permits reduced system power consumption by lowering the clock frequency down to any value For lowest power consumption the Power Down mode is suggested Idle Mode In idle mode see Table 5 the CPU puts itself to sleep while all of the on chip peripherals stay active The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated The CPU contents the on chip RAM and all of the special function registers remain intact during this mode The idle mode can be terminated either by any enabled interrupt at which time the process is picked up at the interrupt service ro
46. e 1 2003 Sep 11 33 Philips Semiconductors Product data 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM P89C60X2 61 X2 80C51 Internal Bus Zero Detector Stop Bit Start Gen TX Control TX Clock Serial Port Y 1 Interrupt SMOD 0 SMOD is PCON 7 RX Clock Ri 1 to 0 RX Control Transition Detector NA Input Shift Register 9 Bits 80C51 Internal Bus TX Clock Write to SBUF Transmit Stop Bit Gen 16 Reset RX Clock Start Bit Detector i Sample Times N MM Mm Mm IM IM IM IM IM M N Receive Shift fl fl fl fl fl fl fl fl fl f f dr zz q ET Figure 18 Serial Port Mode 2 SU01627 2003 Sep 11 34 Philips Semiconductors Product data 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM P89C60X2 61 X2 Timer 1 Overflow 80C51 Internal Bus Shift TX Control Serial Port Interrupt RX Clock R1 1 to 0 RX Control Transition Detector 80C51 Internal Bus TX Clock Write to SBUF Transmit o A RX 16 Reset fl Clock fl fy fl f f f f N N f N RD s o Xo X02 X03 XT X05 XT XT NG Y Stop di ni mes M SM Mm MM IM Im IM IM IM N MM Receive RI y SU00542 Figure 19 Serial Port Mode 3 2003 Sep 11 35 Philips Semiconductors 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM Enhanced UART op
47. e Timer Counters When Timer 0 is in Mode 3 Timer 1 can be TMOD Address 89H Not Bit Addressable Product data P89C60X2 61 X2 turned on and off by switching it out of and into its own Mode 3 or can still be used by the serial port as a baud rate generator or in fact in any application not requiring an interrupt Reset Value 00H TIMER 1 BIT SYMBOL FUNCTION TMOD 3 GATE TIMER 0 Gating control when set Timer Counter n is enabled only while INTn pin is high and PET TMOD 7 TRn control pin is set when cleared Timer n is enabled whenever TRn control bit is set TMOD 2 CT Timer or Counter Selector cleared for Timer operation input from internal system clock TMOD 6 Set for Counter operation input from Tn input pin M1 OPERATING 8048 Timer TLn serves as 5 bit prescaler 16 bit Timer Counter THn and TLn are cascaded there is no prescaler 8 bit auto reload Timer Counter THn holds a value which is to be reloaded into TLn each time it overflows Timer 0 TLO is an 8 bit Timer Counter controlled by the standard Timer 0 control bits THO is an 8 bit timer only controlled by Timer 1 control bits Timer 1 Timer Counter 1 stopped SU01580 Figure 3 Timer Counter 0 1 Mode Control TMOD Register TLn THn d 6 in 6 clock mode d 12 in 12 clock mode 5 Bits 8 Bits Interr
48. e right 1s shift out to the left When the start bit arrives at the leftmost position in the shift register which in mode 1 is a 9 bit register it flags the RX Control block to do one last shift load SBUF and RB8 and set RI The signal to load SBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated 1 R1 0 and 2 Either SM2 0 or the received stop bit 1 If either of these two conditions is not met the received frame is irretrievably lost If both conditions are met the stop bit goes into RB8 the 8 data bits go into SBUF and RI is activated At this time 2003 Sep 11 31 Product data P89C60X2 61 X2 whether the above conditions are met or not the unit goes back to looking for a 1 to 0 transition in RxD More About Modes 2 and 3 Eleven bits are transmitted through TxD or received through RxD a start bit 0 8 data bits LSB first a programmable 9th data bit and a stop bit 1 On transmit the 9th data bit TB8 can be assigned the value of 0 or 1 On receive the 9the data bit goes into RB8 in SCON The baud rate is programmable to either 1 32 or 1 64 12 clock mode or 1 16 or 1 32 the oscillator frequency 6 clock mode the oscillator frequency in Mode 2 Mode 3 may have a variable baud rate generated from Timer 1 or Timer 2 Figures 18 and 19 show a functional diagram of the serial port in Modes 2 and 3 The receive
49. ency at XTAL1 MHz 12 clock mode SU01675 Figure 38 lcc vs FREQ for 12 clock operation Valid only within frequency specifications 2003 Sep 11 Philips Semiconductors Product data 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM P89C60X2 61 X2 NC CLOCK SIGNAL SU00719 SU00720 Figure 39 Icc Test Condition Active Mode Figure 40 Icc Test Condition Idle Mode All other pins are disconnected All other pins are disconnected Voc 0 5 gt cc 0 7VCC 0 2VC0C 0 1 tcHoL gt SU00009 Figure 41 Clock Signal Waveform for Icc Tests in Active and Idle Modes teLcH tcHcL 5ns SU00016 Figure 42 lcc Test Condition Power Down Mode All other pins are disconnected Vcc 2 V to 5 5 V 2003 Sep 11 52 Philips Semiconductors Product data 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM P89C60X2 61 X2 PLCC44 plastic leaded chip carrier 44 leads SOT187 2 pin 1 index scale DIMENSIONS mm dimensions are derived from the original inch dimensions zp Ze Y max P 16 00 16 00 14 99 14 99 0 021 0 032 i i 695 0 695 0 048 0 013 0 026 0 i 685 0 685 0 042 0 040 9 097 0 007 0 004 0 085 0 085 Note 1 Plastic or metal protrusions of 0 25 mm 0 01 inch maximum per side are not included OUTLINE REFERENCES EUROPEAN I
50. ep 11 Product data P89C60X2 61 X2 LQFP PLCC and DIP packages Dual Data Pointers Three security bits Four interrupt priority levels Six interrupt sources Four 8 bit I O ports Full duplex enhanced UART Framing error detection Automatic address recognition Three 16 bit timers counters TO T1 standard 80C51 and additional T2 capture and compare Programmable clock out pin Watchdog timer Asynchronous port reset Low EMI inhibit ALE 6 clock mode Wake up from Power Down by an external interrupt Philips Semiconductors Product data 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM P89C60X2 61 X2 P89C60X2 ORDERING INFORMATION Type number Package Temperature ee P89C60X2BA 00 PLCC44 plastic leaded chip carrier 44 leads SOT187 2 P89C60X2BN 00 DIP40 plastic dual in line package 40 leads SOT129 1 P89C60X2BBD 00 LQFP44 plastic low profile quad flat package 44 leads SOT389 1 P89C61X2 ORDERING INFORMATION Type number Package Temperature Name Description Version Range C P89C61X2BA 00 PLCC44 plastic lead chip carrier 44 leads SOT187 2 P89C61X2BN 00 DIP40 plastic dual in line package 40 leads SOT129 1 P89C61X2BBD 00 LQFP44 plastic low profile quad flat package 44 leads SOT389 1 0 to 70 PART NUMBER DERIVATION P89C60X2 B 0 C to 70 C A PLCC BD LQFP 9 Flash 0 512 bytes RAM X2 6 clock 64 kbytes FLASH mode a
51. eration In addition to the standard operation modes the UART can perform framing error detect by looking for missing stop bits and automatic address recognition The UART also fully supports multiprocessor communication When used for framing error detect the UART looks for missing stop bits in the communication A missing bit will set the FE bit in the SCON register The FE bit shares the SCON 7 bit with SMO and the function of SCON 7 is determined by PCON 6 SMODO see Figure 20 If SMODO is set then SCON 7 functions as FE SCON 7 functions as SMO when SMODO is cleared When used as FE SCON 7 can only be cleared by software Refer to Figure 21 Automatic Address Recognition Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port This feature is enabled by setting the SM2 bit in SCON In the 9 bit UART modes mode 2 and mode 3 the Receive Interrupt flag RI will be automatically set when the received byte contains either the Given address or the Broadcast address The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data Automatic address recognition is shown in Figure 22 The 8 bit mode is c
52. es This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51 type UART drivers which do not make use of this feature Philips Semiconductors Product data 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM P89C60X2 61 X2 SCON Address 98H Bit Addressable 7 Reset Value 0000 0000B 6 SMO FE SMI SMODO 0 1 Position Function SCON 7 SCON 7 SCON 6 TI RI NOTES SMODO is located at PCON 6 fosc oscillator frequency 2003 Sep 11 Framing Error bit This bit is set by the receiver when an invalid stop bit is detected The FE bit is not cleared by valid frames but should be cleared by software The SMODO bit must be set to enable access to the FE bit Serial Port Mode Bit 0 SMODO must 0 to access bit SMO Serial Port Mode Bit 1 SMO SM1 Mode Description Baud Rate shift register fosc 12 12 clk mode or fosc 6 6 clk mode 8 bit UART variable 9 bit UART fosc 64 or fosc 32 or fosc 16 6 clock mode or fosc 32 12 clock mode 3 9 bit UART variable Enables the Automatic Address Recognition feature in Modes 2 or 3 If SM2 1 then RI will not be set unless the received 9th data bit RB8 is 1 indicating an address and the received byte is a Given or Broadcast Address In Mode 1 if SM2 1 then RI will not be activated unless a valid stop bit was received and the received byte is
53. for a 1 to 0 transition at the RxD input Philips Semiconductors 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM Product data P89C60X2 61 X2 80C51 Internal Bus Zero Detector TX Control TX Clock T1 Serial Port Interrupt RX Clock R1 Receive RX Control Shift RxD P3 0 Alt Output Function TxD P3 1 Alt Output Function RxD P3 0 Alt Input Function 80C51 Internal Bus Sa s1 86 81 s6 St selst s6 st SO st sel si Write to SBUF Send S6P2 Shift RXD Data Out io Xr A 2 X 0 Ke X 0 X 0 X o TxD Shift Clock S3P1 S6P1 selst se st ss st Transmit EE n Write to SCON Clear RI LL piIIII I LE ELCCTIT Shift n n n n n J l J l J l Receive TD Shift Clock LI LIT US LS LITT USF USF Ly TxD Shift Clock l SU00539 Figure 16 Serial Port Mode 0 2003 Sep 11 32 Philips Semiconductors Product data 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM P89C60X2 61 X2 Timer 1 Overflow 80C51 Internal Bus Shift TX Control Serial Port Interrupt RX Clock RI 1 to 0 RX Control Transition Detector 80C51 Internal Bus TX Clock Write to SBUF Send S1P1 Transmit 16 Reset Start A Times N MM Mm Mm IM Im IM IM IM M M gt Receive RI PA SU00540 Figure 17 Serial Port Mod
54. he instruction in progress will be completed before vectoring to any service routine Condition 3 ensures that if the instruction in progress is RETI or any access to IE or IP then at least one more instruction will be executed before any interrupt is vectored to The polling cycle is repeated with each machine cycle and the values polled are the values that were present at S5P2 of the previous machine cycle Note that if an interrupt flag is active but not being responded to for one of the above conditions if the flag is not still active when the blocking condition is removed the denied interrupt will not be serviced In other words the fact that the interrupt flag was once active but not serviced is not remembered Every polling cycle is new Philips Semiconductors Product data 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM P89C60X2 61 X2 Address 0A8H Reset Value 0X000000B Bit Addressable 7 6 5 4 EA ET2 ES Enable Bit 1 enables the interrupt Enable Bit 0 disables it SYMBOL FUNCTION Global disable bit If EA 0 all interrupts are disabled If EA 1 each interrupt can be individually enabled or disabled by setting or clearing its enable bit Not implemented Reserved for future use Timer 2 interrupt enable bit Serial Port interrupt enable bit Timer 1 interrupt enable bit External interrupt 1 enable bit Timer 0 interrupt enable bit External interrupt 0
55. hile the oscillator is running resets the device An internal diffused resistor to Vss permits a power on reset using only an external capacitor to Voc ALE PROG Address Latch Enable Program Pulse Output pulse for latching the low byte of the address during an access to external memory In normal operation ALE is emitted at a constant rate of 1 6 12 clk or 1 3 6 clk Mode the oscillator frequency and can be used for external timing or clocking Note that one ALE pulse is skipped during each access to external data memory This pin is also the program pulse input PROG during Flash programming ALE can be disabled by setting SFR auxiliary 0 With this bit set ALE will be active only during a MOVX instruction Program Store Enable The read strobe to external program memory When the device is executing code from the external program memory PSEN is activated twice each machine cycle except that two PSEN activations are skipped during each access to external data memory PSEN is not activated during fetches from internal program memory External Access Enable Programming Supply Voltage EA must be externally held low to enable the device to fetch code from external program memory locations 0000H to FFFFH If EA is held high the device executes from internal program memory This pin also receives the 5 V 12 V programming supply voltage Vpp during Flash programming If security bit 1 is programmed EA will be internally latched on Reset
56. ill accept up to 16 10H data bytes The AAAA string represents the address of the first byte in the record If there are zero bytes in the record this field is often set to 0000 The RR string indicates the record type A record type of 00 is a data record A record type of 01 indicates the end of file mark In this application additional record types will be added to indicate either commands or data for the ISP facility The maximum number of data bytes in a record is limited to 16 decimal ISP commands are summarized in Table 2 As a record is received by the P89C60X2 61X2 the information in the record is stored internally and a checksum calculation is performed The operation indicated by the record type is not performed until the entire record has been received Should an error occur in the checksum the P89C60X2 61X2 will send an X out the serial port indicating a checksum error If the checksum calculation is found to match the checksum in the record then the command will be executed In most cases successful reception of the record will be indicated by transmitting a character out the serial port displaying the contents of the internal program memory is an exception In the case of a Data Record record type 00 an additional check is made A character will NOT be sent unless the record checksum matched the calculated checksum and all of the bytes in the record were successfully progra
57. imer 2 is in the baud rate generator mode one should not try In many applications itis configured for timer operation C T2 0 to read or write TH2 and TL2 As a baud rate generator Timer 2 is Timer operation is different for Timer 2 when it is being used as a incremented every state time osc 2 or asynchronously from pin T2 baud rate generator under these conditions a read or write of TH2 or TL2 may not be accurate The RCAP2 registers may be read but should not be Usually as a timer it would increment every machine cycle i e 1 6 written to because a write might overlap a reload and cause write the oscillator frequency in 6 clock mode or 1 12 the oscillator and or reload errors The timer should be turned off clear TR2 frequency in 12 clock mode As a baud rate generator it before accessing the Timer 2 or RCAP2 registers increments at the oscillator frequency in 6 clock mode or at 1 2 the oscillator frequency in 12 clock mode Thus the baud rate formula is Table 7 shows commonly used baud rates and how they can be as follows obtained from Timer 2 2003 Sep 11 27 Philips Semiconductors 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM Table 7 Timer 2 Generated Commonly Used Baud Rates Baud Rate 12 clk 6 clk mode mode Timer2 2 RCAP2H RCAP2L Summary Of Baud Rate Equations Timer 2 is in baud rate generating mode If Timer 2 is being clocked through pin T2 P1 0 the baud rate is Timer
58. imer Mode Watchdog Timer Reset 73 cn 008 xxx000x0B me IN oo 00H 00H 0x000000B er ee pes N ermer Fe 8 HK 8 8 pre ms em ex Pro PXG 100000008 Jer ve ert xim Pro ror 0000008 FOT Fr ACI CIN ICI CI CI NE CS RC FFH AB MA OL LU LLC A oo Por Om Go PD TOL oo0000s SS F Rs Rs ov JP 0000008 00H 00H 00H 00H XXXXXXXXB 9F 9E 9D 9C 9B 9A 99 98 sore smi Se TREN 188 R88 11 TA 00H Creare eee 00H TESE RGU TO ERNE TRE OT PA 00H Es ii N pe EL 00H 00H 00H 00H 00H 00H Mo oof Fe a TP DA FA E tee E PA 10 Philips Semiconductors Product data 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM P89C60X2 61 X2 NOTES Special Function Registers SFRs accesses are restricted in the following ways 1 Do not attempt to access any SFR locations not defined 2 Accesses to any defined SFR locations must be strictly for the functions for the SFRs 3 SFR bits labeled 0 or 1 can ONLY be written and read as follows MUST be written with 0 but can return any value when read even if it was written with 0 It is a reserved bit and may be used in future derivatives 0 MUST be written with 0 and will return a 0 when read 1 MUST be written with 1 and will return a 1 when read SFRs are bit addressable SFRs are modified from or added to the 80C
59. ion and selection code 0000 read signature byte manufacturer id 15H 0001 read signature byte device id 1 C2H 0002 read signature byte device id 2 P89C60X2 EFh P89C61X2 FOh 0003 read FX2 bit 0080 read ROM code revision 0700 read security bits 0701 read status byte cc checksum Example 1 020000050001F8 read signature byte device id 1 Example 2 020000050003F6 read FX2 bit bit 7 0 represents 12 clk mode bit 7 represents 6 clk mode Example 3 02000005008079 read ROM code revision 0A Rev A OB Rev B etc Direct Load of Baud Rate General Format of Function 06 02xxxx06hhllec number of bytes hex in record required field but value is a don t care Direct Load of Baud Rate function code high byte of Timer 2 low byte of Timer 2 checksum Example 02000006F500F3 2003 Sep 11 17 Philips Semiconductors Product data 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM P89C60X2 61 X2 Security The security feature protects against software piracy and prevents the contents of the FLASH from being read The Security Lock bits are located in FLASH The P89C60X2 61 X2 has 3 programmable security lock bits that will provide different levels of protection for the on chip code and data see Table 3 Unlike the ROM and OTP versions the security lock bits are independent LB3 includes the security protection of LB1 Table 3 SECURITY LOCK BITS PROTECTION
60. ips com 3 For data sheets describing multiple type numbers the highest level product status determines the data sheet status Definitions Short form specification The data in a short form specification is extracted from a full data sheet with the same type number and title For detailed information see the relevant data sheet or data handbook Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System IEC 60134 Stress above one or more of the limiting values may cause permanent damage to the device These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied Exposure to limiting values for extended periods may affect device reliability Application information Applications that are described herein for any of these products are for illustrative purposes only Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification Disclaimers Life support These products are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully inde
61. le an input high or low should hold for at least 12 oscillator interrupt is determined as shown in the following table periods to ensure sampling If the external interrupt is transition activated the external source has to hold the request pin PRIORITY BITS high for at least one cycle and then hold it low for at least one cycle IPHx Px INTERRUPT PRIORITY LEVEL This is done to ensure that the transition is seen so that interrupt request flag IEx will be set IEx will be automatically cleared by the o o Level 0 lowest priority If the external interrupt is level activated the external source has to 1 0 level hold the request active until the requested interrupt is actually generated Then it has to deactivate the request before the interrupt Level 3 highest priority 2003 Sep 11 41 Philips Semiconductors 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM An interrupt will be serviced as long as an interrupt of equal or higher priority is not already being serviced If an interrupt of equal or higher level priority is being serviced the new interrupt will wait until it is finished before being serviced If a lower priority level Table 10 Interrupt Table Product data P89C60X2 61 X2 interrupt is being serviced it will be stopped and the new interrupt serviced When the new interrupt is finished the lower priority level interrupt that was stopped will be completed SOURCE POLLIN
62. le RET instruction would also have returned more than 5 cycles a maximum of one more cycle to complete the execution to the interrupted program but it would have left the instruction in progress plus 4 cycles to complete the next instruction interrupt control system thinking an interrupt was still in progress if the instruction is MUL or DIV making future interrupts impossible PENN Thus in a single interrupt system the response time is always more External Interrupts than 3 cycles and less than 9 cycles The external sources can be programmed to be level activated or transition activated by setting or clearing bit IT1 or ITO in Register TCON If ITx 0 external interrupt x is triggered by a detected low at the INTx pin If ITx 1 external interrupt x is edge triggered In this mode if successive samples of the INTx pin show a high in one As previously mentioned the derivatives described in this data sheet have a four level interrupt structure The corresponding registers are IE IP and IPH See Figures 24 25 and 26 The IPH Interrupt Priority High register makes the four level interrupt cycle and a low in the next cycle interrupt request flag IEx in TCON structure possible is set Flag bit IEx then requests the interrupt The function of the IPH SFR is simple and when combined with the Since the external interrupt pins are sampled once each machine IP SFR determines the priority of each interrupt The priority of each cyc
63. lly forced set to a value other than zero the factory masked ROM ISP boot into ISP operation loader is invoked The factory default for the Status Byte is FFh Once set to 00h the Status Byte can only be changed back to FFh by a full chip erase operation when using ISP After programming the Flash the status byte should be programmed to zero in order to allow execution of the user s application code beginning at address 0000H 2003 Sep 11 13 Philips Semiconductors 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM RST XTAL2 Product data P89C60X2 61 X2 lt 5 V 12 V tolerant 5 V TxD RxD P89C60X2 P89C61X2 Vss SU01674 Figure 2 In System Programming with a Minimum of Pins In System Programming ISP The In System Programming ISP is performed without removing the microcontroller from the system The In System Programming ISP facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the P89C60X2 61 X2 through the serial port This firmware is provided by Philips and embedded within each P89C60X2 61 X2 device The Philips In System Programming ISP facility has made in circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area The ISP function uses five pins TxD RxD Vss Voc and Vpp see Figure 2 Only
64. mit and receive simultaneously It is also receive buffered meaning it can commence reception of a second byte before a previously received byte has been read from the register However if the first byte still hasn t been read by the time reception of the second byte is complete one of the bytes will be lost The serial port receive and transmit registers are both accessed at Special Function Register SBUF Writing to SBUF loads the transmit register and reading SBUF accesses a physically separate receive register The serial port can operate in 4 modes Mode 0 Serial data enters and exits through RxD TxD outputs the shift clock 8 bits are transmitted received LSB first The baud rate is fixed at 1 12 the oscillator frequency in 12 clock mode or 1 6 the oscillator frequency in 6 clock mode Mode 1 10 bits are transmitted through TxD or received through RxD a start bit 0 8 data bits LSB first and a stop bit 1 On receive the stop bit goes into RB8 in Special Function Register SCON The baud rate is variable Mode 2 11 bits are transmitted through TxD or received through RxD start bit 0 8 data bits LSB first a programmable 9th data bit and a stop bit 1 On Transmit the 9th data bit TB8 in SCON can be assigned the value of 0 or 1 Or for example the parity bit P in the PSW could be moved into TB8 On receive the 9th data bit goes into RB8 in Special Function Register SCON while the stop bit i
65. mmed For a data record an X indicates that the checksum failed to match and an R character indicates that one of the bytes did not properly program It is necessary to send a type 02 record specify oscillator frequency to the P89C60X2 61 X2 before programming data The ISP facility was designed to that specific crystal frequencies were not required in order to generate baud rates or time the programming pulses The user thus needs to provide the P89C60X2 61 X2 with information required to generate the proper timing Record type 02 is provided for this purpose Philips Semiconductors Product data 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM P89C60X2 61 X2 Table 2 Intel Hex Records Used by In System Programming RECORD TYPE COMMAND DATA FUNCTION Program Data innaaaa00dd ddcc Where nn number of bytes hex in record aaaa memory address of first byte in record dd dd data bytes ce checksum Example 10008000AF5F67F0602703E0322CFA92007780C3FD End of File EOF no operation XXXXXXOLCC Where XXXXXX required field but value is a don t care s checksum Example 00000001FF ff 06 ss 02 program FX2 bit dd 80 gt 6 clk mode enabled dd data Example 1 0300000306028072 program FX2 bit enable 6 clk mode 03 Miscellaneous Write Functions nnxxxx03ffssddec Where nn number of bytes hex in record XXXX required field but value is a don t care 03
66. mnify Philips Semiconductors for any damages resulting from such application Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits standard cells and or software described or contained herein in order to improve design and or performance When the product is in full production status Production relevant changes will be communicated via a Customer Product Process Change Notification CPCN Philips Semiconductors assumes no responsibility or liability for the use of any of these products conveys no license or title under any patent copyright or mask work right to these products and makes no representations or warranties that these products are free from patent copyright or mask work right infringement unless otherwise specified Contact information Koninklijke Philips Electronics N V 2003 For additional information please visit All rights reserved Printed in U S A http www semiconductors philips com Fax 31 40 27 24825 Date of release 09 03 For sales offices addresses send e mail to i sales addresses www semiconductors philips com Document order number 9397 750 11927 Lett make things better as PHILIPS Copyright Each Manufacturing Company All Datasheets cannot be modified without permission This datasheet has been download from www AllDataSheet com 100 Free DataSheet Search Site Free Download No Register Fast Search System
67. not change the on chip RAM An external interrupt allows both the SFRs and the on chip RAM to retain their values To properly terminate Power Down the reset or external interrupt should not be executed before Vcc is restored to its normal While the device is in ONCE Mode the Port 0 pins go into a float operating level and must be held active long enough for the state and the other port pins and ALE and PSEN are weakly pulled oscillator to restart and stabilize normally less than 10 ms high The oscillator circuit remains active While the device is in this i EA mode an emulator or test CPU can be used to drive the circuit To terminate Power Down with an external interrupt INTO or INT1 Normal operation is restored when a normal reset is applied must be enabled and configured as level sensitive Holding the pin low restarts the oscillator but bringing the pin back high completes POWER ON FLAG the exit Once the interrupt is serviced the next instruction to be executed after RETI will be the one following the instruction that put the device into Power Down The Power On Flag POF is set by on chip circuitry when the Voc level on the P89C60X2 61 X2 rises from 0 to 5 V The POF bit can be set or cleared by software allowing a user to determine if the Design Consideration reset is the result of a power on or a warm start after powerdown When the idle mode is terminated by a hardware reset the device The Vcc level must remain above
68. nterrupts Long Call to Interrupt Routine Are Polled Interrupt Interrupt Interrupt Vector Address Goes Latched Active nas a A A A i This is the fastest possible response when C2 is the final cycle of an instruction other than RETI or an access to IE or IP U00548 Figure 27 Interrupt Response Timing Diagram The polling cycle LCALL sequence is illustrated in Figure 27 service routine is completed or else another interrupt will be f y ui N generated Note that if an interrupt of higher priority level goes active prior to S5P2 of the machine cycle labeled C3 in Figure 27 then in Response Time accordance with the above rules it will be vectored to during C5 and The INTO and INTT levels are inverted and latched into IE0 and IE1 C6 without any instruction of the lower priority routine having been at S5P2 of every machine cycle The values are not actually polled executed by the circuitry until the next machine cycle If a request is active and conditions are right for it to be acknowledged a hardware Thus the processor acknowledges an interrupt request by executing a gt 3 subroutine call to the requested service routine will be the next a hardware generated LCALL to the appropriate servicing routine In some cases it also clears the flag that generated the interrupt and in instruction to be executed The call itself takes two cycles Thus a other cases it doesn t It never clears the Serial Port flag This has to minimum of th
69. ode feature sets operating frequency to be 1 12 or 1 6 of the oscillator frequency The clock mode configuration bit FX2 is located in the Security Block See Table 1 FX2 when programmed will override the SFR clock mode bit X2 in the CKCON register If FX2 is erased then the SFR bit X2 may be used to select between 6 clock and 12 clock mode Philips Semiconductors Product data 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM P89C60X2 61 X2 Table 1 CLOCK MODE CONFIG BIT FX2 X2 bit in CKCON DESCRIPTION Glock mode Glock mode NOTE 1 Default clock mode after ChipErase is set to 12 clock PROGRAM ADDRESS Each block is 4 kbytes in size SU01673 Figure 1 Flash Memory Configuration Power On Reset Code Execution Hardware Activation of the Boot Loader The P89C60X2 61 X2 contains a special Flash register the STATUS The boot loader can also be executed by holding PSEN LOW BYTE At the falling edge of reset the P89C60X2 61 X2 examines EA greater than V y such as 5 V and ALE HIGH or not connected the contents of the Status Byte If the Status Byte is set to zero at the falling edge of RESET This is the same effect as having a power up execution starts at location 0000H which is the normal non zero status byte This allows an application to be built that will start address of the user s application code When the Status Byte is normally execute the end user s code but can be manua
70. r priority level nested interrupt structure a serial I O port for either multi processor SELECTION TABLE communications I O expansion or full duplex UART and on chip For applications requiring more RAM as well as more on chip oscillator and clock circuits peripherals see the P89C66x and P89C51Rx2 data sheets dalle iL efault Clock of Timers ADC bits ch 2 lt z 5 ee e E E EE A EE ee Pecore ee Te TTT EA E O EE E reo NOTE 1 PC Inter Integrated Circuit Bus CAN Controller Area Network SPI Serial Peripheral Interface PCA Programmable Counter Array ADC Analog to Digital Converter PWM Pulse Width Modulation a Hates External Program N security Optional Clock Rate D R 2003 Sep 11 2 853 2400 30250 Philips Semiconductors 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM FEATURES 80C51 Central Processing Unit 64 kbytes Flash 512 bytes RAM P89C60X2 1024 bytes RAM P89C61X2 Boolean processor Fully static operation In System Programmable ISP Flash memory 12 clock operation with selectable 6 clock operation via software or via parallel programmer Memory addressing capability Up to 64 kbytes ROM and 64 kbytes RAM Power control modes Clock can be stopped and resumed ldle mode Power down mode Two speed ranges 0 to 20 MHz with 6 clock operation 0 to 33 MHz with 12 clock operation 2003 S
71. red auto reloads will occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2 1 When either RCLK 1 or TCLK 1 this bit is ignored and the timer is forced to auto reload on Timer 2 overflow SU01621 Figure 8 Timer Counter 2 T2CON Control Register 2003 Sep 11 24 Philips Semiconductors Product data 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM P89C60X2 61 X2 Contro TR2 Capture Transition Timer 2 Detector Interrupt RCAP2L RCAP2H T2EX Pin oo Control EXEN2 SU01622 n 6 in 6 clock mode n 12 in 12 clock mode Figure 9 Timer 2 in Capture Mode T2MOD Address 0C9H Reset Value XXXX XX00B Not Bit Addressable 7 Symbol Position Function Not implemented reserved for future use T20E T2MOD 1 Timer 2 Output Enable bit DCEN T2MOD 0 Down Count Enable bit When set this allows Timer 2 to be configured as an up down counter User software should not write 1s to reserved bits These bits may be used in future 8051 family products to invoke new features In that case the reset or inactive value of the new bit will be 0 and its active value will be 1 The value read from a reserved bit is indeterminate SU01519 Figure 10 Timer 2 Mode T2MOD Control Register 2003 Sep 11 25 Philips Semiconductors 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM TH2 i 8 B
72. ree complete machine cycles elapse between be done in the user s software It clears an external interrupt flag activation of an external interrupt request and the beginning of IEO or IE1 only if it was transition activated The execution of the first instruction of the service routine Figure 27 hardware generated LCALL pushes the contents of the Program shows interrupt response timings Counter on to the stack but it does not save the PSW and reloads the PC with an address that depends on the source of the interrupt being vectored to as shown in Table 10 A longer response time would result if the request is blocked by one of the 3 previously listed conditions If an interrupt of equal or higher priority level is already in progress the additional wait time obviously Execution proceeds from that location until the RETI instruction is depends on the nature of the other interrupt s service routine If the encountered The RETI instruction informs the processor that this instruction in progress is not in its final cycle the additional wait time interrupt routine is no longer in progress then pops the top two cannot be more the 3 cycles since the longest instructions MUL bytes from the stack and reloads the Program Counter Execution of and DIV are only 4 cycles long and if the instruction in progress is the interrupted program continues from where it left off RETI or an access to IE or IP the additional wait time cannot be Note that a simp
73. riggered either by an overflow or by a 1 to 0 transition at input T2EX This transition also sets the EXF2 bit The Timer 2 interrupt if enabled can be generated when either TF2 or EXF2 are 1 In Figure 12 DCEN 1 which enables Timer 2 to count up or down This mode allows pin T2EX to control the direction of count When a logic 1 is applied at pin T2EX Timer 2 will count up Timer 2 will overflow at OFFFFH and set the TF2 flag which can then generate an interrupt if the interrupt is enabled This timer overflow also causes the 16 bit value in RCAP2L and RCAP2H to be reloaded into the timer registers TL2 and TH2 A logic 0 applied to pin T2EX causes Timer 2 to count down The timer will underflow when TL2 and TH2 become equal to the value stored in RCAP2L and RCAP2H A Timer 2 underflow sets the TF2 flag and causes OFFFFH to be reloaded into the timer registers TL2 and TH2 The external flag EXF2 toggles when Timer 2 underflows or overflows This EXF2 bit can be used as a 17th bit of resolution if needed The EXF2 flag does not generate an interrupt in this mode of operation Philips Semiconductors Product data 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM P89C60X2 61 X2 Table 6 Timer 2 Operating Modes YA SO fimmeese 0 fresca x Tor T2CON Address C8H Reset Value 00H Bit Addressable 7 6 5 0 TF2 EXF2 RCLK CP RL2 Position Name and Significance
74. s ignored The baud rate is programmable to either 1 32 or 1 64 the oscillator frequency in 12 clock mode or 1 16 or 1 32 the oscillator frequency in 6 clock mode Mode 3 11 bits are transmitted through TxD or received through RxD a start bit 0 8 data bits LSB first a programmable 9th data bit and a stop bit 1 In fact Mode 3 is the same as Mode 2 in all respects except baud rate The baud rate in Mode 3 is variable In all four modes transmission is initiated by any instruction that uses SBUF as a destination register Reception is initiated in Mode 0 by the condition RI 0 and REN 1 Reception is initiated in the other modes by the incoming start bit if REN 1 Multiprocessor Communications Modes 2 and 3 have a special provision for multiprocessor communications In these modes 9 data bits are received The 9th one goes into RB8 Then comes a stop bit The port can be programmed such that when the stop bit is received the serial port interrupt will be activated only if RB8 1 This feature is enabled by setting bit SM2 in SCON A way to use this feature in multiprocessor systems is as follows When the master processor wants to transmit a block of data to one of several slaves it first sends out an address byte which identifies the target slave An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte With SM2 1 no slave will be interrupted by a data byte An
75. s sampled at a rate of 16 times whatever baud rate has been established When a transition is detected the divide by 16 counter is immediately reset and 1FFH is written to the input shift register At the 7th 8th and 9th counter states of each bit time the bit detector samples the value of R D The value accepted is the value that was seen in at least 2 of the 3 samples If the value accepted during the first bit time is not 0 the receive circuits are reset and the unit goes back to looking for another 1 to 0 transition If the start bit proves valid it is shifted into the input shift register and reception of the rest of the frame will proceed As data bits come in from the right 1s shift out to the left When the start bit arrives at the leftmost position in the shift register which in Modes 2 and 3 is a 9 bit register it flags the RX Control block to do one last shift load SBUF and RB8 and set RI The signal to load SBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated 1 RI 0 and 2 Either SM2 0 or the received 9th data bit 1 If either of these conditions is not met the received frame is irretrievably lost and RI is not set If both conditions are met the received 9th data bit goes into RB8 and the first 8 data bits go into SBUF One bit time later whether the above conditions were met or not the unit goes back to looking
76. sh 512B 1024B RAM P89C60X2 61 X2 PIN DESCRIPTIONS PINNUMBER MNEMONIE PLCC ee oe T Ta LQFP TYPE ane ne FUNCTION 0 V reference Power Gel This is the power supply voltage for normal idle and power down operation Port 0 Port 0 is an open drain bidirectional I O port Port 0 pins that have 1s written to them float and can be used as high impedance inputs Port 0 is also the multiplexed low order address and data bus during accesses to external program and data memory In this application it uses strong internal pull ups when emitting 1s Port 0 also outputs the code bytes during program verification and received code bytes during Flash programming External pull ups are required during program verification P1 0 P1 7 Port 1 Port 1 is an 8 bit bidirectional I O port with internal pull ups Port 1 pins that have 1s written to them are pulled high by the internal pull ups and can be used as inputs As inputs port 1 pins that are externally pulled low will source current because of the internal pull ups See DC Electrical Characteristics Port 1 also receives the low order address byte during program memory verification Alternate functions for Port 1 include T2 P1 0 Timer Counter 2 external count input clockout see Programmable Clock Out T2EX P1 1 Timer Counter 2 Reload Capture Direction control P2 0 P2 7 Port 2 Port 2 is an 8 bit bidirectional I O port with internal pull ups Port 2 pins that have 1s written
77. t Interrupt is generated by the logical OR of RI and TI Neither of these flags is cleared by hardware when the service routine is vectored to In fact the service routine will normally have to determine whether it was RI or TI that generated the interrupt and the bit will have to be cleared in software All of the bits that generate interrupts can be set or cleared by software with the same result as though it had been set or cleared by hardware That is interrupts can be generated or pending interrupts can be canceled in software Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE Figure 24 IE also contains a global disable bit EA which disables all interrupts at once 2003 Sep 11 39 Product data P89C60X2 61 X2 Priority Level Structure Each interrupt source can also be individually programmed to one of four priority levels by setting or clearing bits in Special Function Registers IP Figure 25 and IPH Figure 26 A lower priority interrupt can itself be interrupted by a higher priority interrupt but not by another interrupt of the same level A high priority level 3 interrupt can t be interrupted by any other interrupt source If two request of different priority levels are received simultaneously the request of higher priority level is serviced If requests of the same priority level are received simultaneously an internal polling
78. ta pointer that is currently selected using the AUXR1 bit 0 register The six instructions that use the DPTR are as follows INC DPTR MOV DPTR data16 MOV A A DPTR MOVX A DPTR Increments the data pointer by 1 Loads the DPTR with a 16 bit constant Move code byte relative to DPTR to ACC Move external RAM 16 bit address to ACC Move ACC to external RAM 16 bit address MOVX O DPTR A JMP A DPTR Jump indirect relative to DPTR The data pointer can be accessed on a byte by byte basis by specifying the low or high byte in an instruction which accesses the SFRs See application note AN458 for more details Philips Semiconductors 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM Expanded Data RAM Addressing The P89C60X2 has internal data memory that is mapped into four separate segments the lower 128 bytes of RAM upper 128 bytes of RAM 128 bytes Special Function Register SFR and 256 bytes expanded RAM ERAM 768 bytes for the P89C61X2 The four segments are 1 The Lower 128 bytes of RAM addresses 00H to 7FH are directly and indirectly addressable 2 The Upper 128 bytes of RAM addresses 80H to FFH are indirectly addressable only 3 The Special Function Registers SFRs addresses 80H to FFH are directly addressable only 4 The 256 768 bytes expanded RAM ERAM 00H 1FFH 2FFH are indirectly accessed by move external instruction MOVX and with the EXTRAM bit cleared see
79. th a divide by 32 prescaler Figure 4 shows the Mode 0 operation Mode 2 operation is the same for Timer 0 as for Timer 1 In this mode the Timer register is configured as a 13 bit register As Mode 3 the count rolls over from all 1s to all Os it sets the Timer interrupt Timer 1 in Mode 3 simply holds its count The effect is the same as flag TFn The counted input is enabled to the Timer when TRn 1 setting TR1 0 and either GATE 0 or INTn 1 Setting GATE 1 allows the Timer to be controlled by external input INTn to facilitate pulse width Timer 0 in Mode 3 establishes TLO and THO as two separate measurements TRn is a control bit in the Special Function Register counters The logic for Mode 3 on Timer 0 is shown in Figure 7 TLO TCON Figure 5 uses the Timer 0 control bits C T GATE TRO and TFO as well as pin INTO THO is locked into a timer function counting machine cycles and takes over the use of TR1 and TF1 from Timer 1 Thus THO now controls the Timer 1 interrupt The 13 bit register consists of all 8 bits of THn and the lower 5 bits of TLn The upper 3 bits of TLn are indeterminate and should be ignored Setting the run flag TRn does not clear the registers 2003 Sep 11 20 Philips Semiconductors 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM Mode 3 is provided for applications requiring an extra 8 bit timer on the counter With Timer 0 in Mode 3 an 80C51 can look like it has thre
80. upt Control SU01618 Figure 4 Timer Counter 0 1 Mode 0 13 Bit Timer Counter 2003 Sep 11 Philips Semiconductors Product data 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM P89C60X2 61 X2 TCON Address 88H Reset Value 00H Bit Addressable TFI TRI SYMBOL FUNCTION TF1 Timer 1 overflow flag Set by hardware on Timer Counter overflow Cleared by hardware when processor vectors to interrupt routine or clearing the bit in software TRI Timer 1 Run control bit Set cleared by software to turn Timer Counter on off TFO Timer 0 overflow flag Set by hardware on Timer Counter overflow Cleared by hardware when processor vectors to interrupt routine or by clearing the bit in software TRO Timer 0 Run control bit Set cleared by software to turn Timer Counter on off IE1 Interrupt 1 Edge flag Set by hardware when external interrupt edge detected Cleared when interrupt processed IT1 Interrupt 1 type control bit Set cleared by software to specify falling edge low level triggered external interrupts IEO Interrupt 0 Edge flag Set by hardware when external interrupt edge detected Cleared when interrupt processed ITO Interrupt 0 Type control bit Set cleared by software to specify falling edge low level triggered external interrupts SU01516 Figure 5 Timer Counter 0 1 Control TCON Register Interrupt Control Reload TRn Timer n gt O Gate
81. utine and continued or by a hardware reset which starts the processor in the same manner as a power on reset Philips Semiconductors Product data 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM P89C60X2 61 X2 Power Down Mode machine cycles before the internal reset algorithm takes control To save even more power a Power Down mode see Table 5 can On chip hardware inhibits access to internal RAM in this event but be invoked by software In this mode the oscillator is stopped and access to the port pins is not inhibited To eliminate the possibility of the instruction that invoked Power Down is the last instruction an unexpected write when Idle is terminated by reset the instruction executed The on chip RAM and Special Function Registers retain following the one that invokes Idle should not be one that writes to a their values down to 2 0 V and care must be taken to return Vcc to port pin or to external memory the minimum specified operating voltages before the Power Down Mode is feared i i ONCE Mode The ONCE On Circuit Emulation Mode facilitates testing and debugging of systems without the device having to be removed from the circuit The ONCE Mode is invoked in the following way 1 Pull ALE low while the device is in reset and PSEN is high 2 Hold ALE low as RST is deactivated Either a hardware reset or external interrupt can be used to exit from Power Down Reset redefines all the SFRs but does
82. vailable 1 1024 bytes RAM 64 kbytes FLASH The following table illustrates the correlation between operating mode power supply and maximum external clock frequency Operating Mode Power Supply Maximum Clock Frequency 6 clock 5Vt10 20 MHz 12 clock 5Vt10 33 MHz 2003 Sep 11 4 Philips Semiconductors Product data 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM P89C60X2 61 X2 BLOCK DIAGRAM 1 ACCELERATED 80C51 CPU 12 CLK MODE 6 CLK MODE 64 KBYTE CODE FLASH FULL DUPLEX ENHANCED UART 512 1024 BYTE DATA RAM TIMER 0 TIMER 1 PORT 3 CONFIGURABLE l Os TIMER 2 PORT 2 CONFIGURABLE l Os WATCHDOG PORT 1 TIMER CONFIGURABLE l Os PORT 0 CONFIGURABLE l Os CRYSTAL OR RESONATOR su01664 2003 Sep 11 5 Philips Semiconductors Product data 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM P89C60X2 61 X2 BLOCK DIAGRAM 2 CPU ORIENTED PROGRAM ADDRESS REGISTER BUFFER LL SFRs PC PSW TIMERS INCRE MENTER PROGRAM COUNTER TIMING AND CONTROL OSCILLATOR DRIVERS DPTR S MULTIPLE gt REGISTER INSTRUCTION SU01671 2003 Sep 11 6 Philips Semiconductors Product data 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM P89C60X2 61 X2 LOGIC SYMBOL LOW PROFILE QUAD FLAT PACK PIN FUNCTIONS ADDRESS AND
83. ve 1 requires a 0 in bit 1 A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0 Both slaves can be selected at the same time by an address which has bit 0 0 for slave 0 and bit 1 0 for slave 1 Thus both could be addressed with 1100 0000 In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0 Slave 0 SADDR 1100 0000 SADEN 1111 1001 Given 1100 OXXO Slave 1 SADDR 1110 0000 SADEN 1111 1010 Given 1110 OXOX Slave 2 SADDR 1110 0000 SADEN 1111 1100 Given 1110 00XX In the above example the differentiation among the 3 slaves is in the lower 3 address bits Slave 0 requires that bit 0 0 and it can be uniquely addressed by 1110 0110 Slave 1 requires that bit 1 0 and it can be uniquely addressed by 1110 and 0101 Slave 2 requires that bit 2 0 and its unique address is 1110 0011 To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100 since it is necessary to make bit 2 1 to exclude slave 2 The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN Zeros in this result are trended as don t cares In most cases interpreting the don t cares as ones the broadcast address will be FF hexadecimal Upon reset SADDR SFR address 0A9H and SADEN SFR address 0B9H are leaded with Os This produces a given address of all don t cares as well as a Broadcast address of all don t car
84. wath ss f ew e1 PSENiow ovalonsiusionn ass Jo Ce fet Mmputinsiweton ig aterpsen fo o i el C E FE 5 az Jo PSENiowioadaressiw fo Data Memory um 32 ROpuse wi T Je mme E WRpusewath CAY e ov Jee R lomiovadsaem Pao Piano 32 paano fo pf fo EE e fe Pury 32 ALE tomo vara daran Soi foo rs ov 82 addresstovalddaem O Siae ros rs ann 32 3 AdcressvaldtoWRioworADiw Ptos fm fn Cow 38 Datavaidtowranston foo fo f wox Jes DataholdaterWR faar e fe Cow 30 Daavaiiowanon __ aa Je fe uz Jee Diowa fo fo fn External Clock Coax 35 rige fm foot TI fv fico fe towtme fm fia fn Gaa fs Risetimw pp T T f oo 8 frame pp 1 Ts oa fea Sanar por cock oyo im fraa po I Ts over oa Ouputdatasetuptocloekisngedge fote fer fe ox Joa Output data how ater cock isingedge fa fo fe Fox Joa Inputdataholdafterclockrsingeage p f fo T f txapv 34 Clock rising edge to input data vaid 1033 167 fns NOTES 1 Parameters are valid over operating temperature range unless otherwise specified 2 Load capacitance for port 0 ALE and PSEN 100 pF load capacitance for all other outputs 80 pF 3 Interfacing the microcontroller to devices with float times up to 45 ns is permitted This limited bus contention will not cause damage to Port 0 drivers 4 Parts are tested to 3 5 MHz but guaranteed to operate down to 0 Hz z C T Z NIS
85. wer dissipation based on package heat transfer limitations not device power consumption NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied 2 This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge Nonetheless it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum 3 Parameters are valid over operating temperature range unless otherwise specified All voltages are with respect to Vgs unless otherwise noted AC ELECTRICAL CHARACTERISTICS Tamb 0 C to 70 C CLOCK FREQUENCY GEE SYMBOL PARAMETER OPERATING MODE POWER SUPPLY UNIT VOLTAGE 2003 Sep 11 45 Philips Semiconductors Product data 80C51 8 bit Flash microcontroller family 64KB Flash 512B 1024B RAM P89C60X2 61 X2 DC ELECTRICAL CHARACTERISTICS Tamb 0 C to 70 C Vec 5 V 10 Vss 0 V 20 33 MHz max CPU clock SYMBOL PARAMETER TEST CONDITIONS Vcc 0 5 Vcc 0 5 0 4 lcc Active mode see Note 5 Idle mode see Note 5 Power down mode or clock stopped Tamb 0 C to 70 C see Figure 42 for conditions Programming and erase mode fosc

PHILIPS P89C60X2/61X2 80C51 8-bit Flash microcontroller family handbook

Contents

Download Pdf Manuals

Related Search

Related Contents