PHILIPS 89C536/89C538 80C51 8-bit microcontroller family 16K/64K/512 FLASH handbook
Contents
1. COMMAND IN DATA POLLING DATA N A COMMAND IN T a COMMAD 40H Figure 22 Automatic Programming Timing Waveform 1998 Apr 24 27 SU00877 Philips Semiconductors 80C51 8 bit microcontroller family 16K 64K 512 FLASH Automatic CHIP ERASE All data in the FLASH memory is erased External erase verification is not required Erasure completion can be verified by DATA polling and toggle bit checking after automatic erase starts Device outputs 0 during erasure and 1 after erasure on Q7 Q0 to Q5 Q6 is for toggle bit see toggle bit DATA polling timing waveform are in high impedance SETUP AUTO CHIP ERASE ERASE COMMAND AUTO CHIP ERASE amp DATA POLLING Preliminary specification 89C536 89C538 COMMANDIN COMMAND IN DATA POLLING COMMAND IN COMMAND IN Figure 23 Automatic Chip Erase Timing Waveform SU00878 TCEPHI1 TDH lt _ _ COMMAND IN FFH FFH Figure 24 Reset Timing Waveform 1998 Apr 24 28 SU00879 Philips Semiconductors 80C51 8 bit microcontroller family 16K 64K 512 FLASH Toggle Bit Data Polling Toggle bit appears in Q6 when program erase is operating DATA polling appears in Q7 during programming or erase Preliminary specificati2. i M Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES VERSION JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE SOT307 2 ege 95 02 04 97 08 01 1998 Apr 24 31 Philips Semiconductors Preliminary specification 80C51 8 bit microcontroller family 16K 64K 512 FLASH 690536 89C538 Data sheet status Data sheet Product Definition 1 status status Objective Development This data sheet contains the design target or goal specifications for product development specification Specification may change in any manner without notice Preliminary Qualification This data sheet contains preliminary data and supplementary data will be published at a later date specification Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product Product Production This data sheet contains final specifications Philips Semiconductors reserves the right to make specification changes at any time without notice in order to improve design and supply the best possible product 1 Please consult the most recently issued datasheet before initiating or completing a design Definitions Short form specification The data in a short form specification is extracted from a full data sheet with the same type numbe
3. SCON Serial Port Control Register Philips Semiconductors Preliminary specification 80C51 8 bit microcontroller family 16K 64K 512 FLASH 690536 690538 Interrupt Priority Structure An interrupt will be serviced as long as an interrupt of equal or The 89C536 538 has a 6 source two level interrupt structure see higher priority is not already being serviced If an interrupt of equal Table 7 There are 2 SFRs associated with the interrupts on the or higher level priority is being serviced the new interrupt will wait 89C536 538 They are the IE and IP See Figures 6 and 7 until it is finished before being serviced If a lower priority level interrupt is being serviced it will be stopped and the new interrupt The function of the IPH SFR is simple and when combined with the serviced When the new interrupt is finished the lower priority level IP SFR determines the priority of each interrupt The priority of each interrupt that was stopped will be completed interrupt is determined as shown in the following table Table 7 Interrupt Table 2 T Transition activated 7 6 5 4 IE OA8H EA ET2 ES Enable Bit 1 enables the interrupt Enable Bit 0 disables it SYMBOL FUNCTION Global disable bit If EA 0 all interrupts are disabled If EA 1 each interrupt can be individually enabled or disabled by setting or clearing its enable bit Not implemented Timer 2 interrupt enable bit Serial P
4. Timer 2 has three operating modes Capture Auto reload and Baud Rate Generator which are selected by bits in the T2CON as shown in Table 3 Capture Mode In the capture mode there are two options which are selected by bit EXEN2 in T2CON If EXEN2 0 then timer 2 is a 16 bit timer or counter as selected by C T2 in T2CON which upon overflowing sets bit TF2 the timer 2 overflow bit This bit can be used to generate an interrupt by enabling the Timer 2 interrupt bit in the IE register SFR table If EXEN2 1 Timer 2 operates as described above but with the added feature that a 1 to 0 transition at external input T2EX causes the current value in the Timer 2 registers TL2 and TH2 to be captured into registers RCAP2L and RCAP2H respectively In addition the transition at T2EX causes bit EXF2 in T2CON to be set and EXF2 like TF2 can generate an interrupt which vectors to the same location as Timer 2 overflow interrupt The Timer 2 interrupt service routine can interrogate TF2 and EXF2 to determine which event caused the interrupt The capture mode is Preliminary specification 89C536 89C538 illustrated in Figure 2 There is no reload value for TL2 and TH2 in this mode Even when a capture event occurs from T2EX the counter keeps on counting T2EX pin transitions or osc 12 pulses Auto Reload Mode In the 16 bit auto reload mode Timer 2 can be configured as either a timer or counter C T2 in T2CON Figure 3 shows the auto
5. 16 bit value in registers RCAP2H and RCAP2L which are preset by software 1998 Apr 24 10 SU00068 Timer 2 in Baud Rate Generator Mode The baud rates in modes 1 and 3 are determined by Timer 2 s overflow rate given below Modes 1 and 3 Baud Rates Timer 2 Pate The timer can be configured for either timer or counter operation In many applications it is configured for timer operation C T2 0 Timer operation is different for Timer 2 when it is being used as a baud rate generator Usually as a timer it would increment every machine cycle i e 1 12 the oscillator frequency As a baud rate generator it increments every state time i e 1 2 the oscillator frequency Thus the baud rate formula is as follows Modes 1 and 3 Baud Rates Oscillator Frequency 32 x 65536 RCAP2H RCAP2L Where RCAP2H RCAP2L The content of RCAP2H and RCAP2L taken as a 16 bit unsigned integer The Timer 2 as a baud rate generator mode shown in Figure 4 is valid only if RCLK and or TCLK 1 in T2CON register Note that a rollover in TH2 does not set TF2 and will not generate an interrupt Thus the Timer 2 interrupt does not have to be disabled when Timer 2 is in the baud rate generator mode Also if the EXEN2 T2 external enable flag is set a 1 to 0 transition in T2EX Timer counter 2 trigger input will set EXF2 T2 external flag but will not cause a reload from RCAP2H RCAP2L to TH2 TL2 T
6. Data is latched on the rising edge of WE or CE whichever occurs first To simplify the following discussion the WE pin is used as the write cycle control pin through the rest of this text All setup and hold times are with respect to the WE signal PGM COMMAND DATA Vpp LOW PULSE P3 4 P2 6 P3 7 P3 1 P3 0 SU00876 Erase Programming Verification Philips Semiconductors Preliminary specification 80C51 8 bit microcontroller family 16K 64K 512 FLASH 6905306 89 0538 Table 8 Pin Description PN SYMBOL FUN 4 P1 0 P1 7 A0 A7 Input Low Order Address Bits EE i rn EE m ees Table 9 Command Definitions FIRST BUS CYCLE SECOND BUS CYCLE COMMAND BUS CYCLES OPERATION ADDRESS DATA OPERATION ADDRESS DATA Setup auto erase auto erase chip Write X 30H Write X 30H Setup auto program program Write X 40H Write PA PD NOTES PA Address of memory location to be programmed PD Data to be programmed at location Command Definitions When low voltage is applied to the Vpp pin the contents of the command register default to 00H Placing high voltage on the Vpp pin enables read write operations Device operations are selected by writing specific data patterns into the command register Table 9 defines these 89C536 538 register commands Table 10 defines the bus operations of 89C536 538 Table 10 READ WRITE Read 2 VppH DATA OUT 3 iis ies i
7. LEADED CHIP CARRIER PIN FUNCTIONS PLASTIC QUAD FLAT PACK PIN FUNCTIONS 1 2 3 4 5 6 7 8 NO INTERNAL CONNECTION Function NIC P1 0 T2 P1 1 T2EX P1 2 ECI P1 3 CEX0 P1 4 CEX1 P1 5 CEX2 P1 6 CEX3 P1 7 CEX4 RST P3 0 RxD NIC P3 1 TxD P3 2 INTO P3 3 INT1 1998 Apr 24 Function P3 4 TO P3 5 T1 P3 6 WR P3 7 RD XTAL2 XTAL1 Vss NIC P2 0 A8 P2 1 A9 P2 2 A10 P2 3 A11 P2 4 A12 P2 5 A13 P2 6 A14 Function P2 7 A15 PSEN ALE PROG NIC EA Vpp P0 7 AD7 P0 6 AD6 P0 5 AD5 P0 4 AD4 P0 3 AD3 P0 2 AD2 P0 1 AD1 P0 0 ADO Voc SU00023 gt OANOahWOND Function P1 5 CEX2 P1 6 CEX3 P1 7 CEX4 RST P3 0 RxD NIC P3 1 TxD P3 2 INTO P3 3 INTT P3 4 TO P3 5 T1 P3 6 WR P3 7 RD XTAL2 XTAL1 NO INTERNAL CONNECTION Function Vss NIC P2 0 A8 P2 1 A9 P2 2 A10 P2 3 A11 P2 4 A12 P2 5 A13 P2 6 A14 P2 7 A15 PSEN ALE PROG NIC EA Vpp P0 7 AD7 Function P0 6 AD6 P0 5 AD5 P0 4 AD4 P0 3 ADS P0 2 AD2 P0 1 AD1 P0 0 ADO Voc NIC P1 0 T2 P1 1 T2EX P1 2 ECI P1 3 CEXO P1 4 CEX1 SU00024 Philips Semiconductors Preliminary specification 80C51 8 bit microcontroller family 16K 64K 512 FLASH 690536 690538 PIN DESCRIPTIONS PIN NUMBER MNEMONIC LCC QFP TYPE NAME AND FUNCTION Vss 1 Ground OV reference 23 44 Power Supply This is the power supply voltage for normal idle and power down operation 43 36 37 30 Port 0 Port 0 is an op
8. and during accesses to external data memory that use 16 bit addresses MOVX DPTR In this application it uses strong internal pull ups when emitting 1s Some Port 2 pins receive the high order address bits during EEPROM programming and verification P3 0 P3 7 Port 3 Port 3 is an 8 bit bidirectional I O port with internal pull ups Port 3 pins that have 1s written to them are pulled high by the internal pull ups and can be used as inputs As inputs port 3 pins that are externally being pulled low will source current because of the pull ups See DC Electrical Characteristics lj Port 3 also serves the special features of the 80C51 family as listed below RxD P3 0 Serial input port TxD P3 1 Serial output port INTO P3 2 External interrupt INT1 P3 3 External interrupt TO P3 4 Timer 0 external input T1 P3 5 Timer 1 external input WR P3 6 External data memory write strobe RD P3 7 External data memory read strobe oo o RST Reset A high on this pin for two machine cycles while the oscillator is running resets the device An internal diffused resistor to Ves permits a power on reset using only an external capacitor to Voc ALE PROG o Address Latch Enable Program Pulse Output pulse for latching the low byte of the address during an access to external memory In normal operation ALE is emitted at a constant rate of 1 6 the oscillator frequency and can be used for external timing or clocking Note that
9. fesem PC ESL usc oEseupimetetore commande A Eu wem PP ERI Eo ourntasaniotme mz o LS E Eom DATA polinatoggie access ims L9 L8 aee rese imemauo cipe 59m 5 Fi waperamwgwmemamwdy 1 3 5 3 NOTES 1 CE and OE must be fixed high during Vpp transition from 5V to 12V or from 12V to 5V 2 tpg is defined as the time at which the output achieves the open circuit condition and data is no longer driven 1998 Apr 24 26 Philips Semiconductors 80C51 8 bit microcontroller family 16K 64K 512 FLASH Timing Waveform Automatic Programming One byte of data is programmed Verifying in fast algorithm and additional programming by external control are not required because these operations are executed automatically by an internal control circuit Programming completion can be verified by DATA polling and toggle bit checking after automatic verify starts Device outputs DATA during programming and DATA after programming on Q7 QO to Q5 Q6 is for toggle bit see toggle bit DATA polling timing waveform are in high impedance SETUP AUTO PROGRAM CE ROSRAM COMMAND AUTO PROGRAM amp DATA POLLING Preliminary specification 89C536 89C538 ADDRESS VALID cux t TCEPH1 ls p pec cm TDH DS lt
10. one ALE pulse is skipped during each access to external data memory This pin is also the program pulse input PROG during EEPROM programming Program Store Enable The read strobe to external program memory When the processor is executing code from the external program memory PSEN is activated twice each machine cycle except that two PSEN activations are skipped during each access to external data memory PSEN is not activated during fetches from internal program memory External Access Enable Programming Supply Voltage EA must be externally held low to enable the device to fetch code from external program memory If EA is held high the device executes from internal program memory This pin also receives the 12V programming supply voltage Vpp during EPROM programming EA is internally latched on Reset Crystal 1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits Crystal 2 Output from the inverting oscillator amplifier NOTE To avoid latch up effect at power on the voltage on any pin at any time must not be higher than Voc 0 5V or Vss 0 5V respectively 1998 Apr 24 5 Philips Semiconductors Preliminary specification 80C51 8 bit microcontroller family 16K 64K 512 FLASH 89C0536 89C538 Table 1 Special Function Registers DIRECT BIT ADDRESS SYMBOL OR ALTERNATIVE PORT FUNCTION RESET SYMBOL DESCRIPTION ADDRESS MSB LSB VALUE Accumulator B register 00H Data Poi
11. reload mode of Timer 2 In this mode there are two options selected by bit EXEN2 in T2CON register If EXEN2 0 then Timer 2 counts up to OFFFFH and sets the TF2 Overflow Flag bit upon overflow This causes the Timer 2 registers to be reloaded with the 16 bit value in RCAP2L and RCAP2H The values in RCAP2L and RCAP2H are preset by software If EXEN2 1 then a 16 bit reload can be triggered either by an overflow or by a 1 to 0 transition at input T2EX This transition also sets the EXF2 bit The Timer 2 interrupt if enabled can be generated when either TF2 or EXF2 are 1 The external flag EXF2 toggles when Timer 2 underflows or overflows This EXF2 bit can be used as a 17th bit of resolution if needed The EXF2 flag does not generate an interrupt in this mode of operation LSB EXF2 RCLK CP RL2 Position Name and Significance T2CON 7 when either RCLK or TCLK 1 T2CON 6 T2CON 5 T2CON 4 T2CON 3 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software TF2 will not be set Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 1 When Timer 2 interrupt is enabled EXF2 1 will cause the CPU to vector to the Timer 2 interrupt routine EXF2 must be cleared by software Receive clock flag When set causes the serial port to use Timer 2 overflow pulses for its receive clock in modes 1 and 3 RCLK 0
12. the rated maxima 3 Parameters are valid over operating temperature range unless otherwise specified All voltages are with respect to Vss unless otherwise noted 1998 Apr 24 15 Philips Semiconductors Preliminary specification 80C51 8 bit microcontroller family 16K 64K 512 FLASH 89C0536 89C538 DC ELECTRICAL CHARACTERISTICS Tamb 0 C to 70 C 5V 10 Vss OV TEST Lus p wc SYMBOL PARAMETER CONDITIONS UNIT pud low a 4 5V lt Vcc lt 5 5V Lm 5 A 2Vcc 0 1 V CC CC 6 Voc 4 5V Output low voltage ports 1 2 3 lor 1 6mA 5 6 Voc 4 5V Vout Output low voltage port 0 ALE PSEN lo 3 2mA 2 Voc 4 5V Von Output high voltage ports 1 2 3 lon 304A V D high voltage port 0 in external bus mode ALE Voc 4 5V OH1 loH 800uA DENM Logical 0 input current ports 1 2 3 Vin 0 4V Logical 1 to 0 transition current ports 1 2 3 ay puel d LI Power supply current pos Figure 16 See note 4 Active mode Voc 5 5V Idle mode FREQ 24 MHz Power down mode or clock stopped Tamb 0 C to 70 C n see Figure 20 for conditions NOTES 1 Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the Vo s of ALE and ports 1 and 3 The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1 to 0 transitions during bus operations In the worst cases capacitive loading gt 100pF the noise pulse on the ALE pin may exceed
13. the setting of the TR2 bit Therefore bit TR2 must be set separately to turn the timer on see Table 5 for set up of Timer 2 as a timer Also see Table 6 for set up of Timer 2 as a counter T2CON INTERNAL CONTROL EXTERNAL CONTROL a 1 c 2 EC T coe E Table 6 Timer 2 as a Counter TMOD INTERNAL CONTROL EXTERNAL CONTROL Note 1 Note 2 Auto Reload o Reload C a ee E NOTES 1 Capture reload occurs only on timer counter overflow 2 Capture reload occurs on timer counter overflow and a 1 to 0 transition on T2EX P1 1 pin except when Timer 2 is used in the baud rate generator mode 1998 Apr 24 11 Philips Semiconductors 80C51 8 bit microcontroller family 16K 64K 512 FLASH Serial Interface The 89C538 536 has a standard 80C51 serial port This serial port can operate in 4 modes Mode 0 Serial data enters and exits through RxD TxD outputs the shift clock 8 bits are transmitted received LSB first The baud rate is fixed at 1 12 the oscillator frequency Mode 1 10 bits are transmitted through TxD or received through RxD a start bit 0 8 data bits LSB first and a stop bit 1 On receive the stop bit goes into RB8 in Special Function Register SCON The baud rate is variable Mode 2 11 bits are transmitted through TxD or received through RxD start bit 0 8 data bits LSB first a programmable 9th data bit and a stop bit 1 On Transmit the 9th data bit TB8 in SCON can be assign
14. 0 8V In such cases it may be desirable to qualify ALE with a Schmitt Trigger or use an address latch with a Schmitt Trigger STROBE input Io can exceed these conditions provided that no single output sinks more than 5mA and no more than two outputs exceed the test conditions 2 Capacitive loading on ports 0 and 2 may cause the Voy on ALE and PSEN to momentarily fall below the Vcc 0 7 specification when the address bits are stabilizing 3 Pins of ports 1 2 and 3 source a transition current when they are being externally driven from 1 to 0 The transition current reaches its maximum value when Viv is approximately 2V 4 See Figures 17 through 20 for Icc test conditions and Figure 15 for limits 5 Load capacitance for port 0 ALE and PSEN 100pF load capacitance for all other outputs 80pF 6 Under steady state non transient conditions lo must be externally limited as follows Maximum lo per port pin 15mA Maximum lo per 8 bit port 26mA Maximum total lo for all outputs 71mA If loj exceeds the test condition Vo may exceed the related specification Pins are not guaranteed to sink current greater than the listed test conditions 7 ALE is tested to Vou except when ALE is off then Voy is the voltage specification 8 Pin capacitance is characterized but not tested Pin capacitance is less than 25pF Pin capacitance of ceramic package is less than 15pF except EA is 25pF 1998 Apr 24 16 Philips Semiconductors Preliminar
15. 66 Figure 2 Timer 2 in Capture Mode CONTROL RELOAD TRANSITION DETECTOR RCAP2L RCAP2H o TIMER 2 INTERRUPT oo CONTROL SU00067 Figure 3 Timer 2 in Auto Reload Mode 1998 Apr 24 9 Philips Semiconductors 80C51 8 bit microcontroller family 16K 64K 512 FLASH NOTE OSC Freq is divided by 2 not 12 oT 0 Control Transition Detector T2EX Pin xez F2 Control is RCAP2L RCAP2H Preliminary specification 89C536 89C538 Timer 1 Overflow Timer 2 Interrupt PR Note availability of additional external interrupt Figure 4 Table 4 Timer 2 Generated Commonly Used Baud Rates o Tme2 o 2 Baud Rate RCAP2L Baud Rate Generator Mode Bits TCLK and or RCLK in T2CON Table 3 allow the serial port transmit and receive baud rates to be derived from either Timer 1 or Timer 2 When TCLK 0 Timer 1 is used as the serial port transmit baud rate generator When TCLK 1 Timer 2 is used as the serial port transmit baud rate generator RCLK has the same effect for the serial port receive baud rate With these two bits the serial port can have different receive and transmit baud rates one generated by Timer 1 the other by Timer 2 Figure 4 shows the Timer 2 in baud rate generation mode The baud rate generation mode is like the auto reload mode in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the
16. DATA SAHEET 89C536 89C538 80C51 8 bit microcontroller family 16K 64K 512 FLASH Preliminary specification 1998 Apr 24 Supersedes data of 1997 Dec 02 IC20 Data Handbook PHILIPS Philips Semiconductors Philips Semiconductors Preliminary specification LSE SS 80C51 8 bit microcontroller family 16K 64K 512 FLASH uude dues DESCRIPTION FEATURES The 89C536 89C538 are Single Chip 8 Bit Microcontrollers 80C51 Central Processing Unit manufactured in advanced CMOS process and are derivatives of the 80C51 microcontroller family All the devices have the same 16k x 8 89C536 or 64k x 8 89C538 FLASH EPROM Program instruction set as the 80C51 Memory The devices also have four 8 bit I O ports three 16 bit timer event 9 512 x 8 RAM externally expandable to 64k x 8 Data Memory counters a multi source two priority level nested interrupt T structure UART and on chip oscillator and timing circuits For Three 16 bit counter timers systems that require extra data memory capability up to 64k bytes Up to 3 external interrupt request inputs each can be expanded using standard TTL compatible memories and logic 6 interrupt sources with 2 priority levels The 89C536 89C538 contain a non volatile FLASH program 9 Four 8 bit I O ports memory 16k bytes in the 89C536 and 64k bytes in the 89C538 o The devices have 512 bytes of RAM data memory Ful dupiex UNIS 9 Power control modes Idle mode Power down mod
17. an be accessed by either direct or indirect addressing The Upper 128 bytes can be accessed by indirect addressing only The Upper 128 bytes occupy the same address space as the SFRs That means they have the same address but are physically separate from SFR space When an instruction accesses an internal location above address 7FH the CPU knows whether the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction Instructions that use direct addressing access SFR space For example MOV OAOH data accesses the SFR at location OAOH which is P2 Instructions that use indirect addressing access the Upper 128 bytes of data RAM UPPER 128 BYTES INTERNAL RAM ERAM 256 BYTES LOWER 128 BYTES INTERNAL RAM Figure 8 1998 Apr 24 Preliminary specification 89C536 89C538 For example MOV RO data where RO contains OAOH accesses the data byte at address OAOH rather than P2 whose address is OAOH The ERAM can be accessed by indirect addressing and MOVX instructions This part of memory is physically located on chip logically occupies the first 256 bytes of external data memory The ERAM is indirectly addressed using the MOVX instruction in combination with any of the registers RO R1 of the selected bank or DPTR An access to ERAM will not affect ports PO P3 6 WR and P3 7 RD P2 SFR is output during external addressing For example MOVX RO data whe
18. bv P2 0 P2 7 OR A8 A15 FROM DPF A0 A15 FROM PCH Figure 10 External Data Memory Read Cycle 1998 Apr 24 INSTR IN SU00025 Philips Semiconductors Preliminary specification 80C51 8 bit microcontroller family 16K 64K 512 FLASH 890536 890538 lt lt tWHLH gt INSTR IN P2 0 P2 7 OR A8 A15 FROM DPF A0 A15 FROM PCH Figure 11 External Data Memory Write Cycle SU00026 lt XLXL E CLOCK txHax tovxH WRITE TO SBUF gt txHDx txupv lt gt SET TI er d KK XQ XR RA ADK RU CDK AD CLEAR RI SET RI SU00027 Figure 12 Shift Register Mode Timing 0 7VCC 0 2VCC 0 1 lcHcL gt SU00009 Figure 13 External Clock Drive 1998 Apr 24 19 Philips Semiconductors Preliminary specification 80C51 8 bit microcontroller family 16K 64K 512 FLASH 89C0536 89C538 Voc 0 5 V 0 1V TIMING 0 2VCC 0 9 LOAD 7 VLOAD REFERENCE POINTS a 0 45V 0 2Vcc 0 1 VLOAD 0 1V VOL 0 1V NOTE NOTE AC inputs during testing are driven at Vcc 0 5 for a logic 1 and 0 45V for a logic 0 For timing purposes a port is no longer floating when a 100mV change from Timing measurements are made at Vj min for a logic 1 and Vj max for a logic 0 load voltage occurs and begins to float when a 100mV change from the loaded Vou Voy level occurs lop loL 2 20mA SU00717 SU00718 Figure 14 AC Testing Input Output Fig
19. causes Timer 1 overflow to be used for the receive clock Transmit clock flag When set causes the serial port to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3 TCLK 0 causes Timer 1 overflows to be used for the transmit clock Timer 2 external enable flag When set allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port EXEN2 0 causes Timer 2 to ignore events at T2EX TR2 T2CON 2 C T2 T2CON 1 Timer or counter select Timer 2 0 Internal timer OSC 12 Start stop control for Timer 2 A logic 1 starts the timer 1 External event counter falling edge triggered CP RL2 T2CON 0 Capture Reload flag When set captures will occur on negative transitions at T2EX if EXEN2 1 When cleared auto reloads will occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2 1 When either RCLK 1 or TCLK 1 this bit is ignored and the timer is forced to auto reload on Timer 2 overflow Figure 1 Table 3 Timer 2 Operating Modes SU00866 Timer Counter 2 T2CON Control Register 16 bit Auto reload 16 bit Capture Baud rate generator 1998 Apr 24 Philips Semiconductors Preliminary specification 80C51 8 bit microcontroller family 16K 64K 512 FLASH 89C0536 89C538 TL2 8 bits Capture Transition Timer 2 Detector Interrupt RCAP2L RCAP2H T2EX Pin SU000
20. e with wakeup from power down using external interrupt 9 44 pin PLCC and QFP packages ORDERING INFORMATION 6 FREQ DRAWING PART NUMBER MEMORY SIZE TEMPERATURE RANGE C AND PACKAGE MHz NUMBER P89C536NBA A 16k bytes 0 to 70 44 pin Plastic Leaded Chip Carrier SOT187 2 P89C536NBB B 16k bytes 0 to 70 44 pin Plastic Quad Flat Package SOT307 2 P89C538NBA A 64k bytes 0 to 70 44 pin Plastic Leaded Chip Carrier SOT187 2 P89C538NBB B 64k bytes 0 to 70 44 pin Plastic Quad Flat Package SOT307 2 1998 Apr 24 2 Philips Semiconductors Preliminary specification 80C51 8 bit microcontroller family 16K 64K 512 FLASH 89C0536 89C538 BLOCK DIAGRAM m A vd B REGISTER PROGRAM ADDRESS REGISTER K N BUFFER PC INCRE MENTER PROGRAM COUNTER DPTR S MULTIPLE 8 INSTRUCTION REGISTER PORT3 LATCH PORT 3 DRIVERS SU00854 LOGIC SYMBOL PROGRAMMING INFORMATION Programmers are provided by Company Phone Number Internet Address Advin 1 800 627 2456 ADDRESS AND BP Microsystem 1 800 225 2102 http www bpmicro com DATA BUS Data I O 1 206 881 6444 http www data io com HiLo A YII i SM r ADDRESS BUS AAAA VVVY SECONDARY FUNCTIONS i SU00830 1998 Apr 24 3 Philips Semiconductors Preliminary specification 80C51 8 bit microcontroller family 16K 64K 512 FLASH 690536 690538 PLASTIC
21. ed the value of 0 or 1 Or for example the parity bit P in the PSW could be moved into TB8 On receive the 9th data bit goes into RB8 in Special Function Register SCON while the stop bit is ignored The baud rate is programmable to either 1 32 or 1 64 the oscillator frequency SCON Address 98H Bit Addressable Preliminary specification 89C536 89C538 Mode 3 11 bits are transmitted through TxD or received through jRxD a start bit 0 8 data bits LSB first a programmable 9th data bit and a stop bit 1 In fact Mode 3 is the same as Mode 2 in all respects except baud rate The baud rate in Mode 3 is variable In all four modes transmission is initiated by any instruction that uses SBUF as a destination register Reception is initiated in Mode 0 by the condition RI 0 and REN 1 Reception is initiated in the other modes by the incoming start bit if REN 1 Serial Port Control Register The serial port control and status register is the Special Function Register SCON shown in Figure 5 This register contains not only the mode selection bits but also the 9th data bit for transmit and receive TB8 and RB8 and the serial port interrupt bits TI and RI Additional details of serial port operation may be found in the 80C51 Family Hardware Description found in the Philips 80C51 Based 8 Bit Microcontroller Data Handbook IC20 Reset Value 0000 0000B SMO SM1 Bit 7 6 Func
22. en drain bidirectional I O port Port 0 pins that have 1s written to them float and can be used as high impedance inputs Port 0 is also the multiplexed low order address and data bus during accesses to external program and data memory In this application it uses strong internal pull ups when emitting 1s Port 0 also outputs the code bytes during program verification and received code bytes during EEPROM programming External pull ups are required during program verification P1 0 P1 7 Port 1 Port 1 is an 8 bit bidirectional I O port with internal pull ups Port 1 pins that have 1s written to them are pulled high by the internal pull ups and can be used as inputs As inputs port 1 pins that are externally pulled low will source current because of the internal pull ups See DC Electrical Characteristics Ij Port 1 also receives the low order address byte during program memory verification Alternate functions for Port 1 include T2 P1 0 Timer Counter 2 external count input T2EX P1 1 Timer Counter 2 Reload Capture P2 0 P2 7 Port 2 Port 2 is an 8 bit bidirectional I O port with internal pull ups Port 2 pins that have 1s written to them are pulled high by the internal pull ups and can be used as inputs As inputs port 2 pins that are externally being pulled low will source current because of the internal pull ups See DC Electrical Characteristics lj Port 2 emits the high order address byte during fetches from external program memory
23. h time the device returns to the Read mode no program verify command is required but data can be read out if OE is active low Reset Command A reset command is provided as a means to safely abort the erase or program command sequences Following either set up command erase or program with two consecutive writes of FFH Preliminary specification 89C536 89C538 will safely abort the operation Memory contents will not be altered Should program fail or erase fail happen two consecutive writes of FFH will reset the device to abort the operation A valid command must then be written to place the device in the desired state Write Operation Status Toggle Bit DQ6 The 89C536 538 features a Toggle Bit as a method to indicate to the host system that the Auto Program Erase algorithms are either in progress or completed While the Automatic Program or Erase algorithm is in progress successive attempts to read data from the device will result in DQ6 toggling between one and zero Once the Automatic Program or Erase algorithm is completed DQ6 will stop toggling and valid data will be read The toggle bit is valid after the rising edge of the second WE pulse of the two write pulse sequences Data Polling D07 The 89C536 538 also features DATA Polling as a method to indicate to the host system that the Automatic Program or Erase algorithms are either in progress or completed While the Automatic Programming algorithm is in operat
24. herefore when Timer 2 is in use as a baud rate generator T2EX can be used as an additional external interrupt if needed Philips Semiconductors 80C51 8 bit microcontroller family 16K 64K 512 FLASH When Timer 2 is in the baud rate generator mode one should not try to read or write TH2 and TL2 As a baud rate generator Timer 2 is incremented every state time osc 2 or asynchronously from pin T2 under these conditions a read or write of TH2 or TL2 may not be accurate The RCAP2 registers may be read but should not be written to because a write might overlap a reload and cause write and or reload errors The timer should be turned off clear TR2 before accessing the Timer 2 or RCAP2 registers Table 4 shows commonly used baud rates and how they can be obtained from Timer 2 Summary Of Baud Rate Equations Timer 2 is in baud rate generating mode If Timer 2 is being clocked through pin T2 P1 0 the baud rate is Timer 2 Overflow Rate Baud Rate 16 Table 5 Timer 2 as a Timer Preliminary specification 89C536 89C538 If Timer 2 is being clocked internally the baud rate is z fosc Baud Rate i37 x 65536 RCAP2H RCAPAL Where fosc Oscillator Frequency To obtain the reload value for RCAP2H and RCAP2L the above equation can be rewritten as f OSC RCAP2H RCAP2L 65536 s X Baid sas Timer Counter 2 Set up Except for the baud rate generator mode the values given for T2CON do not include
25. i i aas NOTES Vppy is the programming voltage specified for the device Read operation with VPP Vppy may access array data if write command is preceded or silicon ID codes With Vpp at high voltage the standby current equals Icc lpp standby Refer to Table 38 for valid Data In during a write operation X can be Vi or Vip oS RON 1998 Apr 24 23 Philips Semiconductors 80C51 8 bit microcontroller family 16K 64K 512 FLASH Set Up Automatic Chip Erase Erase Commands The automatic chip erase does not require the device to be entirely pre programmed prior to executing the Automatic set up erase command and automatic chip erase command Upon executing the Automatic chip erase command the device automatically will program and verify the entire memory for an all zero data pattern When the device is automatically verified to contain an all zero pattern a self timed chip erase and verify begins The erase and verify operations are complete when the data on DQ7 is 1 at which time the device returns to the standby mode The system is not required to provide any control or timing during these operations When using the Automatic Chip Erase algorithm note that the erase automatically terminates when adequate erase margin has been achieved for the memory array no erase verify command is required The margin voltages are internally generated in the same manner as when the standard erase verify command is used The Au
26. icrocontroller family 16K 64K 512 FLASH 6905306 89 0538 Command programming Data programming Erase Operation DC CHARACTERISTICS Tamb 0 C to 70 C Voc 5V 10 Vpp 12 0V 5 SYMBOL PARAMETER CONDITION Input Leakage Current Vin GND to Voc Output Leakage Current Voyt GND to Voc Standby Vcc Current CE Viy CE Vcc 0 3 V lcc1 Read Operating Vcc Current lout 0 mA f 1 MHz loca lout 0 mA F 11MHz lcca Program In Programming lcca Erase In Erase In Program Verify In erase Verify Vpp 12 6 V In Programming In Erase In Program Verify 1 Voc must be applied before Vpp and removed after Vpp 2 Vpp must not exceed 14V including overshoot 3 An influence may be had upon device reliability if the device is installed or removed while Vpp 12V 4 Do not alter Vpp from Vi to 12V or 12V to Vij when CE Vi_ 5 Vy min 0 5V for pulse width x 20ns 6 If Vi is over the specified maximum value programming operation cannot be guaranteed 7 All currents are in RMS unless otherwise noted Sampled not 10095 tested 1998 Apr 24 25 Philips Semiconductors Preliminary specification 80C51 8 bit microcontroller family 16K 64K 512 FLASH 6905306 89 0538 AC CHARACTERISTICS Tamb 0 C to 70 C Voc 5V 10 Vpp 12V 5 faddessscupime S dT ECL Eos pWAsewme LESE Eo pA teiiime LS ECL ose OE setup tme verore DATA potingon f o ooo 5 Rus
27. in order to improve design and or performance Philips Semiconductors assumes no responsibility or liability for the use of any of these products conveys no license or title under any patent copyright or mask work right to these products and makes no representations or warranties that these products are free from patent copyright or mask work right infringement unless otherwise specified Philips Semiconductors Copyright Philips Electronics North America Corporation 1998 811 East Arques Avenue All rights reserved Printed in U S A P O Box 3409 Sunnyvale California 94088 3409 Date of release 05 98 Telephone 800 234 7381 Document order number 9397 750 03876 Lett make things beter ee amp PHILIPS Copyright Each Manufacturing Company All Datasheets cannot be modified without permission This datasheet has been download from www AllDataSheet com 100 Free DataSheet Search Site Free Download No Register Fast Search System www AllDataSheet com
28. ion an attempt to read the device will produce the complement data of the data last written to DQ7 Upon completion of the Automatic Program algorithm an attempt to read the device will produce the true data last written to DQ7 The Data Polling feature is valid after the rising edge of the second WE pulse of the two write pulse sequences While the Automatic Erase algorithm is in operation DQ7 will read 0 until the erase operation is completed Upon completion of the erase operation the data on DQ7 will read 1 The DATA Polling feature is valid after the rising edge of the second WE pulse of two writes pulse sequences The DATA Polling feature is active during Automatic Program Erase algorithms Write Operation The data to be programmed into Flash should be inverted when programming In other words to program the value 00 FF should be applied to port PO System Considerations During the switch between active and standby conditions transient current peaks are produced on the rising and falling edges of Chip Enable The magnitude of these transient current peaks is dependent on the output capacitance loading of the device Ata minimum a 0 1uF ceramic capacitor high frequency low inherent inductance should be used on each device between Vcc and GND and between Vpp and GND to minimize transient effects eo vwe LL SL Vr v 1998 Apr 24 Philips Semiconductors Preliminary specification 80C51 8 bit m
29. long enough to allow the oscillator time to start up normally a few milliseconds plus two machine cycles At power on the voltage on Vcc and RST must come up at the same time for a proper start up Ports 1 2 and 3 will asynchronously be driven to their reset condition when a voltage above Viu min is applied to RESET LOW POWER MODES Idle Mode In the idle mode see Table 2 the CPU puts itself to sleep while all of the on chip peripherals stay active The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated The CPU contents the on chip RAM and all of the special function registers remain intact during this mode The idle mode can be terminated either by any enabled interrupt at which time the process is picked up at the Preliminary specification 89C536 89C538 interrupt service routine and continued or by a hardware reset which starts the processor in the same manner as a power on reset Power Down Mode To save even more power a Power Down mode see Table 2 can be invoked by software In this mode the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed The on chip RAM and Special Function Registers retain their values down to 2 0V and care must be taken to return Vcc to the minimum specified operating voltages before the Power Down Mode is terminated Either a hardware reset or external interr
30. ng Algorithm The 89C536 538 automatic Programming algorithm requires the user to only write a program set up command and a program command program data and address The device automatically times the programming pulse width provides the program verify and counts the number of sequences A status bit similar to DATA polling and a status bit toggling between consecutive read cycles provide feedback to the user as to the status of the programming operation AUTOMATIC ERASE ALGORITHM The 89C536 538 Automatic Erase algorithm requires the user to only write an erase set up command and erase command The device will automatically pre program and verify the entire array Then the device automatically times the erase pulse width provides the erase verify and counts the number of sequences A status bit similar to DATA polling and a status bit toggling between consecutive read cycles provide feedback to the user as to the status of the erase operation Commands are written to the command register Register contents Serve as inputs to an internal state machine which controls the erase and programming circuitry During write cycles the command register internally latches address and data needed for the programming and erase operations For system design simplification the 89C536 538 is designed to support either WE or CE controlled writes During a system write cycle addresses are latched on the falling edge of WE or CE whichever occurs last
31. nter 2 bytes Data Pointer High 00H Data Pointer Low 00H AF AE AD AC AB AA A9 A8 P2 Port 2 FFH P3 Port 3 FFH PCON Power Control 00xx0000B PSW Program Status Word RS1 RSO 00H RACAP2H Timer 2 Capture High 00H RACAP2L Timer 2 Capture Low 00H SBUF Serial Data Buffer XXXXXXXXB SCON Serial Control SP Stack Pointer TCON Timer Control T2CON Timer 2 Control THO Timer High 0 TH1 Timer High 1 TH2 Timer High 2 TLO Timer Low 0 TL1 Timer Low 1 TL2 Timer Low 2 TMOD Timer Mode SFRsare bit addressable SFRs are modified from or added to the 80C51 SFRs Reserved bits 1998 Apr 24 6 Philips Semiconductors 80C51 8 bit microcontroller family 16K 64K 512 FLASH OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output respectively of an inverting amplifier The pins can be configured for use as an on chip oscillator To drive the device from an external clock source XTAL1 should be driven while XTAL2 is left unconnected There are no requirements on the duty cycle of the external clock signal because the input to the internal clock circuitry is through a divide by two flip flop However minimum and maximum high and low times specified in the data sheet must be observed RESET A reset is accomplished by holding the RST pin high for at least two machine cycles 24 oscillator periods while the oscillator is running To insure a good power on reset the RST pin must be high
32. on 89C536 89C538 ON oe c 1 TOGGLE BIT ee No Ru OE DURING P E 07 DURING P H signer Ne No 7 H H Z 4 eee ae EL uc DATA DATA DATA GH Z GH Z DATA POLLING PROGRAM ERASE COMPLETE DATA POLLING 00 05 1998 Apr 24 Figure 25 Toggle Bit Data Polling Timing Waveform 29 SU00880 Philips Semiconductors Preliminary specification 80C51 8 bit microcontroller family 16K 64K 512 FLASH 690536 89C538 PLCC44 plastic leaded chip carrier 44 leads SOT187 2 Zeit ees UN OUUUUUU AA AA ED pin 1 index detail X scale DIMENSIONS millimetre dimensions are derived from the original inch dimensions 17 65 17 65 17 40 17 40 0 021 0 032 3 0 695 0 695 0 013 0 026 i i 0 685 0 685 0 004 0 085 Note 1 Plastic or metal protrusions of 0 01 inches maximum per side are not included OUTLINE REFERENCES EUROPEAN ISSUE DATE 460 sse SOT187 2 112E10 MO 047AC 07 12 18 1998 Apr 24 30 Philips Semiconductors 80C51 8 bit microcontroller family 16K 64K 512 FLASH Preliminary specification 89C536 89C538 QFP44 plastic quad flat package 44 leads lead length 1 3 mm body 10 x 10 x 1 75 mm SOT307 2 N Me did l pin 1 index DIMENSIONS mm are the original dimensions
33. ort interrupt enable bit Timer 1 interrupt enable bit External interrupt 1 enable bit Timer 0 interrupt enable bit External interrupt O enable bit SUO00571 Figure 6 IE Registers 7 6 5 IP 0B8H PT2 PS Priority Bit 1 assigns higher priority Priority Bit 0 assigns lower priority SYMBOL FUNCTION Not implemented reserved for future use Not implemented reserved for future use Timer 2 interrupt priority bit Serial Port interrupt priority bit Timer 1 interrupt priority bit External interrupt 1 priority bit Timer 0 interrupt priority bit External interrupt 0 priority bit SU00572 Figure 7 IP Registers 1998 Apr 24 13 Philips Semiconductors 80C51 8 bit microcontroller family 16K 64K 512 FLASH Expanded Data RAM Addressing The 89C536 538 has internal data memory that is mapped into four separate segments the lower 128 bytes of RAM upper 128 bytes of RAM 128 bytes Special Function Register SFR and 256 bytes expanded RAM ERAM The four segments are 1 The Lower 128 bytes of RAM addresses 00H to 7FH are directly and indirectly addressable 2 The Upper 128 bytes of RAM addresses 80H to FFH are indirectly addressable only 3 The Special Function Registers SFRs addresses 80H to FFH are directly addressable only 4 The 256 bytes expanded RAM ERAM 00H FFH are indirectly accessed by move external instruction MOVX The Lower 128 bytes c
34. r and title For detailed information see the relevant data sheet or data handbook Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System IEC 134 Stress above one or more of the limiting values may cause permanent damage to the device These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied Exposure to limiting values for extended periods may affect device reliability Application information Applications that are described herein for any of these products are for illustrative purposes only Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification Disclaimers Life support These products are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application Right to make changes Philips Semiconductors reserves the right to make changes without notice in the products including circuits standard cells and or software described or contained herein
35. re RO contains 0AOH accesses the ERAM at address 0A0H rather than external memory An access to external data memory locations higher than FFH i e 0100H to FFFFH will be performed with the MOVX DPTR instructions in the same way as in the standard 80C51 so with PO and P2 as data address bus and P3 6 and P3 7 as write and read timing signals Refer to Figure 8 External data memory cannot be accessed using the MOVX with RO or R1 This will always access the ERAM The stack pointer SP may be located anywhere in the 256 bytes RAM lower and upper RAM internal data memory The stack may not be located in the ERAM SPECIAL EXTERNAL FUNCTION DATA REGISTER MEMORY SU00868 Internal and External Data Memory Address Space Philips Semiconductors Preliminary specification 80C51 8 bit microcontroller family 16K 64K 512 FLASH 69C5306 89 0538 ABSOLUTE MAXIMUM RATINGS 2 3 NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied 2 This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge Nonetheless it is suggested that conventional precautions be taken to avoid applying greater than
36. tcLoL 133 o Jwa m tavxH txHax input data hold ater ook rising ege o Jof fm Pf oaas 167 ms 13 13 13 3 XHDX 12 12 12 12 XHDV 2 1 Clock rising edge to input data valid z o m 4 1 Parameters are valid over operating temperature range unless otherwise specified 2 Load capacitance for port 0 ALE and PSEN 100pF load capacitance for all other outputs 80pF 3 Interfacing the microcontroller to devices with float times up to 45ns is permitted This limited bus contention will not cause damage to Port 0 drivers 1998 Apr 24 17 Philips Semiconductors 80C51 8 bit microcontroller family 16K 64K 512 FLASH EXPLANATION OF THE AC SYMBOLS Each timing symbol has five characters The first character is always t time The other characters depending on their positions indicate the name of a signal or the logical status of that signal The designations are A Address C Clock D Input data H Logic level high Instruction program memory contents L Logic level low or ALE Preliminary specification 89C536 89C538 P PSEN Q Output data R RD signal t Time V Valid W WR signal X No longer a valid logic level Z Float Examples tay Time for address valid to ALE low tLLPL Time for ALE low to PSEN low SU00006 Figure 9 External Program Memory Read Cycle gt tav
37. time Auto Erase and auto program DATA polling Toggle bit 9 100 minimum erase program cycles Advanced CMOS FLASH EPROM memory technology GENERAL DESCRIPTION The 89C536 538 FLASH EPROM memory augments EPROM functionality with In circuit electrical erasure and programming The 89C536 538 uses a command register to manage this functionality The FLASH EPROM reliably stores memory contents even after 100 erase and program cycles The cell is designed to optimize the erase and programming mechanisms In addition the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling The 89C536 538 uses a 12 0V 5 Vpp supply to perform the Auto Program Erase algorithms Automatic Programming The 89C536 538 is byte programmable using the Automatic Programming algorithm The Automatic Programming algorithm does not require the system to time out or verify the data programmed The typical room temperature chip programming time of the 89C536 538 is less than 5 seconds 89C536 538 Figure 21 1998 Apr 24 Preliminary specification 89C536 89C538 Automatic Chip Erase The device may be erased using the automatic Erase algorithm The automatic Erase algorithm automatically programs the entire array prior to electrical erase The timing and verification of electrical erase are controlled internal to the device Automatic Programmi
38. tion Serial Port Mode Bit 0 Serial Port Mode Bit 1 SMO SM1 Mode 0 0 0 0 1 1 1 0 2 1 1 3 Description shift register 8 bit UART 9 bit UART 9 bit UART Baud Rate fosc 12 variable fosc 64 or fosc 32 variable Enables the Automatic Address Recognition feature in Modes 2 or 3 If SM2 1 then RI will not be set unless the received 9th data bit RB8 is 1 indicating an address and the received byte is a Given or Broadcast Address In Mode 1 if SM2 1 then RI will not be activated unless a valid stop bit was received and the received byte is a Given or Broadcast Address In Mode 0 SM2 should be 0 Enables serial reception Set by software to enable reception Clear by software to disable reception The 9th data bit that will be transmitted in Modes 2 and 3 Set or clear by software as desired In modes 2 and 3 the 9th data bit that was received In Mode 1 if SM2 0 RB8 is the stop bit that was received In Mode 0 RB8 is not used TI Transmit interrupt flag Set by hardware at the end of the 8th bit time in Mode 0 or at the beginning of the stop bit in the other modes in any serial transmission Must be cleared by software RI Receive interrupt flag Set by hardware at the end of the 8th bit time in Mode 0 or halfway through the stop bit time in the other modes in any serial reception except see SM2 Must be cleared by software NOTE fosc oscillator frequency Figure 5 1998 Apr 24 SU00867
39. tomatic set up erase command is a command only operation that stages the device for automatic electrical erasure of all bytes in the array Automatic set up erase is performed by writing 30H to the command register To command automatic chip erase the command 30H must be written again to the command register The automatic chip erase begins on the rising edge of the WE and terminates when the data on DQ7 is 1 and the data on DQ6 stops toggling for two consecutive read cycles at which time the device returns to the standby mode Set Up Automatic Program Program Commands The Automatic Set up Program is a command only operation that stages the devices for automatic programming Automatic Set up Program is performed by writing 40H to the command register Once the Automatic Set up Program operation is performed the next WE pulse causes a transition to an active programming operation Addresses are internally latched on the falling edge of the WE pulse Data is internally latched on the rising edge of the WE pulse The rising edge of WE also begins the programming operation The system is not required to provide further controls or timings The device will automatically provide an adequate internally generated program pulse and verify margin The automatic programming operation is completed when the data read on DQ6 stops toggling for two consecutive read cycles and the data on DQ7 and DQ6 are equivalent to data written to these two bits at whic
40. upt can be used to exit from Power Down Reset redefines all the SFRs but does not change the on chip RAM An external interrupt allows both the SFRs and the on chip RAM to retain their values To properly terminate Power Down the reset or external interrupt should not be executed before Vcc is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize normally less than 10ms With an external interrupt INTO and INT1 must be enabled and configured as level sensitive Holding the pin low restarts the oscillator but bringing the pin back high completes the exit Once the interrupt is serviced the next instruction to be executed after RETI will be the one following the instruction that put the device into Power Down Design Consideration 9 To eliminate the possibility of an unexpected write when Idle is terminated by reset the instruction following the one that invokes Idle should not be one that writes to a port pin or to memory Table 2 External Pin Status During Idle and Power Down Mode PROGRAM MEMORY Dm p omma o EC Som Toe PORT 0 PORT 3 Power down External 1998 Apr 24 Philips Semiconductors 80C51 8 bit microcontroller family 16K 64K 512 FLASH TIMER 2 OPERATION Timer 2 Timer 2 is a 16 bit Timer Counter which can operate as either an event timer or an event counter as selected by C T2 in the special function register T2CON see Figure 1
41. ure 15 Float Waveform MAX ACTIVE MODE ACTIVE MODE i MAX IDLE MODE 1 TYP IDLE MODE 0 4 8 12 16 20 24 28 32 36 FREQ AT XTAL1 MHz SU00886 Figure 16 Icc vs FREQ Valid only within frequency specifications of the device under test 1998 Apr 24 20 Philips Semiconductors 80C51 8 bit microcontroller family 16K 64K 512 FLASH SU00719 Figure 17 Icc Test Condition Active Mode All other pins are disconnected Moc 0b5 sz cc 0 7VCC 0 2Vcc 0 1 Preliminary specification 89C536 89C538 NC CLOCK SIGNAL SU00720 Figure 18 Icc Test Condition Idle Mode All other pins are disconnected lcHcL gt SUO00009 Figure 19 Clock Signal Waveform for Icc Tests in Active and Idle Modes tcrcH tcHcL 5ns SU00016 1998 Apr 24 Figure 20 Icc Test Condition Power Down Mode All other pins are disconnected Vcc 2V to 5 5V 21 Philips Semiconductors 80C51 8 bit microcontroller family 16K 64K 512 FLASH FLASH EPROM PROGRAM MEMORY FEATURES 9 16K 89C536 or 64K 89C538 or electrically erasable internal program Up to 64 Kilobyte external program memory if the internal program memory is switched off EA 0 Programming and erasing voltage 12V 5 Command register architecture Byte Programming 10 us typical Auto chip erase 5 seconds typical including preprogramming
42. y specification 80C51 8 bit microcontroller family 16K 64K 512 FLASH 6905306 89 0538 AC ELECTRICAL CHARACTERISTICS Tamb 0 C to 70 C Voc 5V 1096 Vgs 0V1 2 VARIABLE CLOCK 33MHz CLOCK SYMBOL l tcicL PARAMETER C2 Co Oscillator frequency Speed versions N 33MHz ALE pulse width 2tci cL 40 Address valid to ALE low tetoL 25 Address hold after ALE low tetoL 25 ALE low to valid instruction in ALE low to PSEN low totcL 25 PSEN pulse width PSEN low to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float E HLL rm r 4tcicL 65 v lt tpxix tpxiz taviv tpLaz Data Memory 10 11 RD pulse width 6tcLcL 100 10 11 R pulse width 6tcLcL 100 10 11 RD low to valid data in 10 11 Data hold after RD 10 11 Data float after RD 10 11 ALE low to valid data in Btccc 150 90 ns 10 11 Address to valid data in Stcrci 165 105 ms 10 11 ALE low to RD or WR low Stci ci 50 10 11 Address valid to WR low or RD low 4c 75 4 Jm 10 11 Data valid to WR transition duon 30 9 s 10 11 Data hold after WR Quo 1 5 n tRLAz 10 11 RD low to address float S twuLH 10 11 RD or WR high to ALE high icicL 25 i tRLRH twi WH tRLDV RHDX tRHDZ tLLDv tavbv tLLWL tavwL tavwx twHax tavwH XLXL Output data setup to clock rising edge 10
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PHILIPS 89C536/89C538 80C51 8 bit microcontroller family 16K/64K/512 FLASH handbook