PHILIPS 89C51/89C52/89C54/89C58 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash handbook
Contents
1. Priority Bit 1 assigns higher priority Priority Bit 0 assigns lower priority SYMBOL FUNCTION Not implemented reserved for future use Not implemented reserved for future use PT2 Timer 2 interrupt priority bit PS Serial Port interrupt priority bit PT1 Timer 1 interrupt priority bit PX1 External interrupt 1 priority bit PTO Timer 0 interrupt priority bit PXO External interrupt O priority bit SU00572 Figure 11 IP Registers 7 6 5 4 IPH B7H 5 PT2H PSH Priority Bit 1 assigns higher priority Priority Bit 0 assigns lower priority SYMBOL FUNCTION Not implemented reserved for future use Not implemented reserved for future use Timer 2 interrupt priority bit high Serial Port interrupt priority bit high Timer 1 interrupt priority bit high External interrupt 1 priority bit high Timer 0 interrupt priority bit high External interrupt 0 priority bit high 8U01058 Figure 12 IPH Registers 18 www dzsc Philips Semiconductors 80C51 8 bit microcontroller family 4K 8K 16K 32K Flash Reduced EMI Mode The AO bit AUXR 0 in the AUXR register when set disables the ALE output Reduced EMI Mode AUXR 8EH 7 6 5 4 3 2 1 0 e xp ee ee EN ee e AUXR 0 AO Turns off ALE output Dual DPTR The dual DPTR structure see Figure 13 is a way by which the chip will specify the address of an external data memory location There are two 12. Function P2 7 A15 PSEN ALE NIC EA Vpp P0 7 AD7 P0 6 AD6 P0 5 AD5 P0 4 AD4 P0 3 AD3 P0 2 AD2 P0 1 AD1 P0 0 ADO Vcc SU01062 Function P0 6 AD6 P0 5 AD5 P0 4 AD4 P0 3 AD3 P0 2 AD2 PO 1 AD1 P0 0 ADO Voc NIC P1 0 1 P1 1 1 P1 2 P1 3 P1 4 SU01064 Philips Semiconductors 80C51 8 bit microcontroller family 4K 8K 16K 32K Flash PIN DESCRIPTIONS PIN NUMBER mnemonic BIP Lec ar Vss 20 22 16 P1 0 P2 0 P3 0 Ww P1 7 P2 7 P3 7 ww dzsc Product specification 89C51 89C52 89C54 89C58 TYPE NAME AND FUNCTION I O I I I I O O I Ground 0 V reference Power Supply This is the power supply voltage for normal idle and power down operation Port 0 Port 0 is an open drain bidirectional I O port Port 0 pins that have 1s written to them float and can be used as high impedance inputs Port 0 is also the multiplexed low order address and data bus during accesses to external program and data memory In this application it uses strong internal pull ups when emitting 1s Port 1 Port 1 is an 8 bit bidirectional I O port with internal pull ups Port 1 pins that have 1s written to them are pulled high by the internal pull ups and can be used as inputs As inputs port 1 pins that are externally pulled low will source current because of the internal pull ups See DC Electrical Characteristics lj Alternate function for Port 1 T2 P1 0 Timer Counter2 extern
3. Bit 7 Symbol Function Not implemented reserved for future use T20E Timer 2 Output Enable bit DCEN Down Count Enable bit When set this allows Timer 2 to be configured as an up down counter User software should not write 1s to reserved bits These bits may be used in future 8051 family products to invoke new features In that case the reset or inactive value of the new bit will be 0 and its active value will be 1 The value read from a reserved bit is indeterminate SU00729 Figure 3 Timer 2 Mode T2MOD Control Register 3X HE 10 Www dzsc Philips Semiconductors Product specification 80C51 8 bit microcontroller family 4K 8K 16K 32K Flash 89C51 89C52 89C54 89C58 TL2 TH2 8 BITS 8 BITS CONTROL RELOAD TRANSITION DETECTOR RCAP2L RCAP2H T2EX PIN m oo o TIMER 2 INTERRUPT CONTROL SU00067 Figure 4 Timer 2 in Auto Reload Mode DCEN 0 DOWN COUNTING RELOAD VALUE TOGGLE OVERFLOW oo TF2 INTERRUPT CONTROL TR2 DIRECTION 0 DOWN RCAP2L RCAP2H UP COUNTING RELOAD VALUE T2EX PIN SU00730 Figure 5 Timer 2 Auto Reload Mode DCEN 1 mS s Www dzsc Philips Semiconductors Product specification 80C51 8 bit microcontroller family 4K 8K 16K 32K Flash 89C51 89C52 89C54 89C58 Timer 1 Overflow NOTE OSC Freq is divided by 2 not 12 TO Control Transi
4. Philips Semiconductors Product specification 80C51 8 bit microcontroller family 4K 8K 16K 32K Flash 89C51 89C52 89C54 89C58 DC ELECTRICAL CHARACTERISTICS Tamb 0 C to 70 C or 40 C to 85 C 5 V 10 Vgs 0 V TEST SYMBOL PARAMETER CONDITIONS V Input low voltage 4 5 V lt Vcc lt 5 5 V V Input high voltage ports 0 1 2 3 EA Po V l Vind Input high voltage XTAL1 RST 8 Voc 4 5 V Output low voltage ports 1 2 3 lor 1 6 mA IL IH OL OH EA 7 8 Voc 4 5 V Vout Output low voltage port 0 ALE PSEN lor 3 2 mA 3 Vec 4 5 V V Output high voltage ports 1 2 3 lon 30 pA V Output high voltage port 0 in external bus mode Voc 4 5 V OH ALE9 PSEN3 lou 3 2 mA Logical 0 input current ports 1 2 3 Vin 0 4 V 1 dens jus 6 Vin 2 0 V Logical 1 to 0 transition current ports 1 2 3 See Note 4 Input leakage current port 0 0 45 lt Vin lt Voc 0 3 oo 9 m loc Power supply current see Figure 21 See Note 5 Active mode see Note 5 Idle mode see Note 5 Power down mode or clock stopped see Figure 25 Tamb 0 C to 70 C for conditions Tamb 40 C to 85 C RRST Internal reset pull down resistor Cio Pin capacitance except EA NOTES 1 Typical ratings are not guaranteed The values listed are at room temperature 5 V 2 Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the Vo s of ALE and ports 1 and 3 The noise is
5. 1 and 0 45V for a logic 0 For timing purposes a port is no longer floating when a 100mV change from Timing measurements are made at Vj min for a logic 1 and Vir max for a logic 0 load voltage occurs and begins to float when a 100mV change from the loaded Vou Voy level occurs lop loL 2 20MA SU00717 SU00718 Figure 19 AC Testing Input Output Figure 20 Float Waveform Icc MAX ACTIVE MODE lec MAX ACTIVE MODE TYP Icc MAX IDLE M Icc IDLE MODE TYP 24 28 Frequency at XTAL1 MHz SU01056 Figure 21 Icc vs FREQ Valid only within frequency specifications of the device under test 25 www dzsc Philips Semiconductors Product specification 80C51 8 bit microcontroller family 4K 8K 16K 32K Flash 89C51 89C52 89C54 89C58 NC CLOCK SIGNAL SU00719 SU00720 Figure 22 Icc Test Condition Active Mode Figure 23 Icc Test Condition Idle Mode All other pins are disconnected All other pins are disconnected Voc 0 5 ec 0 7VCC 0 2VC0C 0 1 lcHcL gt SU00009 Figure 24 Clock Signal Waveform for Icc Tests in Active and Idle Modes teLcH tcHcL 5ns SU00016 Figure 25 lcc Test Condition Power Down Mode All other pins are disconnected Vcc 2V to 5 5V X HE 26 Www dzsc Philips Semiconductors Product specification 80C51 8 bit microcontroller family 4K 8K 16K 32K Flash 89C51
6. 89C52 89C54 89C58 Security The security feature protects against software piracy and prevents the contents of the FLASH from being read The Security Lock bits are located in FLASH The 89C51 89C52 89C54 89C58 has 3 programmable security lock bits that will provide different levels of protection for the on chip code and data see Table 8 Unlike the ROM and OTP versions the security lock bits are independent LB3 includes the security protection of LB1 Table 8 SECURITY LOCK BITS PROTECTION DESCRIPTION eve LB1 MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory LB2 Program verification is disabled LB3 External execution is disabled NOTE 1 The security lock bits are independent 27 www dzsc Philips Semiconductors Product specification 80C51 8 bit microcontroller family 4K 8K 16K 32K Flash 89C51 89C52 89C54 89C58 PLCC44 plastic leaded chip carrier 44 leads SOT187 2 iii GUI Ped ep kak ANo pin 1 index detail X 0 5 10 mm scale DIMENSIONS millimetre dimensions are derived from the original inch dimensions A A k Zp ze UNIT A TA 4 bo b DM EM e ep eg Hp H k Tl L viw D E min 3 max p 1 p E b E max P Y max max p 4 57 0 53 0 81 16 66 16 66 16 00 16 0
7. P1 1 pin except when Timer 2 is used in the baud rate generator mode ax HE 13 Www dzsc Philips Semiconductors 80C51 8 bit microcontroller family 4K 8K 16K 32K Flash Enhanced UART The UART operates in all of the usual modes that are described in the first section of Data Handbook IC20 80C51 Based 8 Bit Microcontrollers In addition the UART can perform framing error detect by looking for missing stop bits and automatic address recognition The UART also fully supports multiprocessor communication as does the standard 80C51 UART When used for framing error detect the UART looks for missing stop bits in the communication A missing bit will set the FE bit in the SCON register The FE bit shares the SCON 7 bit with SMO and the function of SCON 7 is determined by PCON 6 SMODO see Figure 7 If SMODO is set then SCON 7 functions as FE SCON 7 functions as SMO when SMODO is cleared When used as FE SCON 7 can only be cleared by software Refer to Figure 8 Automatic Address Recognition Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port This feature is enabled by setting the SM2 bit in SCON In the 9 bit UART modes mode 2 and mode 3 the Receive Interrupt
8. and all of the special function registers remain intact during this mode The idle mode can be terminated either by any enabled interrupt at which time the process is picked up at the interrupt service routine and continued or by a hardware reset which starts the processor in the same manner as a power on reset Power Down Mode To save even more power a Power Down mode see Table 2 can be invoked by software In this mode the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed The on chip RAM and Special Function Registers retain their values down to 2 0 V and care must be taken to return Voc to the minimum specified operating voltages before the Power Down Mode is terminated Either a hardware reset or external interrupt can be used to exit from Power Down Reset redefines all the SFRs but does not change the on chip RAM An external interrupt allows both the SFRs and the on chip RAM to retain their values To properly terminate Power Down the reset or external interrupt should not be executed before Vcc is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize normally less than 10ms With an external interrupt INTO and INT1 must be enabled and configured as level sensitive Holding the pin low restarts the oscillator but bringing the pin back high completes the exit Once the interrupt is serviced the next instruction t
9. and low times specified in the data sheet must be observed RESET A reset is accomplished by holding the RST pin high for at least two machine cycles 24 oscillator periods while the oscillator is running To insure a good power on reset the RST pin must be high long enough to allow the oscillator time to start up normally a few milliseconds plus two machine cycles At power on the voltage on Vcc and RST must come up at the same time for a proper start up Ports 1 2 and 3 will asynchronously be driven to their reset condition when a voltage above Vj min is applied to RESET The value on the EA pin is latched when RST is deasserted and has no further effect Philips Semiconductors 80C51 8 bit microcontroller family 4K 8K 16K 32K Flash LOW POWER MODES Stop Clock Mode The static design enables the clock speed to be reduced down to 0 MHZ stopped When the oscillator is stopped the RAM and Special Function Registers retain their values This mode allows step by step utilization and permits reduced system power consumption by lowering the clock frequency down to any value For lowest power consumption the Power Down mode is suggested Idle Mode In the idle mode see Table 2 the CPU puts itself to sleep while all of the on chip peripherals stay active The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated The CPU contents the on chip RAM
10. as on the 80C51 An interrupt will be serviced as long as an interrupt of equal or higher priority is not already being serviced If an interrupt of equal or higher level priority is being serviced the new interrupt will wait until it is finished before being serviced If a lower priority level interrupt is being serviced it will be stopped and the new interrupt serviced When the new interrupt is finished the lower priority level interrupt that was stopped will be completed SOURCE POLLING PRIORITY REQUEST BITS HARDWARE CLEAR VECTOR ADDRESS IEO N UT Y TIS TPO IE1 TF1 ce __ tmee __ NOTES 1 L Level activated 2 T Transition activated 7 6 5 4 IE OA8H EA ET2 ES Enable Bit 1 enables the interrupt Enable Bit 0 disables it SYMBOL FUNCTION Global disable bit If EA 0 all interrupts are disabled If EA 1 each interrupt can be individually enabled or disabled by setting or clearing its enable bit Not implemented Reserved for future use Timer 2 interrupt enable bit Serial Port interrupt enable bit Timer 1 interrupt enable bit External interrupt 1 enable bit Timer 0 interrupt enable bit External interrupt 0 enable bit SU00571 Figure 10 IE Registers HE 17 Www dzsc Philips Semiconductors Product specification 80C51 8 bit microcontroller family 4K 8K 16K 32K Flash 89C51 89C52 89C54 89C58 7 6 5 IP 0B8H PT2 PS
11. value on the EA pin is latched when RST is released and any subsequent changes have no effect This pin also receives the 12 00 V programming supply voltage Vpp during FLASH programming Crystal 1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits Crystal 2 Output from the inverting oscillator amplifier Philips Semiconductors Product specification 80C51 8 bit microcontroller family 4K 8K 16K 32K Flash 89C51 89C52 89C54 89C58 Table 1 89C51 89C52 89C54 89C58 Special Function Registers DIRECT BIT ADDRESS SYMBOL OR ALTERNATIVE PORT FUNCTION RESET ACC Accumulator AUXR Auxiliary XXXXXXXOB AUXR1 Auxiliary 1 xxxx00x0B B B register 00H DPTR Data Pointer 2 bytes DPH Data Pointer High 00H DPL Data Pointer Low 00H Interrupt Enable Interrupt Priority High a rr roe xx000000B pot Porto mE me Tuer p pug Tr pn FFH PSW Program Status Word RACAP2H Timer 2 Capture High 00H RACAP2L Timer 2 Capture Low 00H SADDR Slave Address 00H SADEN Slave Address Mask 00H SBUF Serial Data Buffer XXXXXXXXB 9F 9E 9D 9C 9B 9A 99 98 scor Seria Contro Eworc sw owe ren 75 ee TO Ar oon SP Stack Pointer TCON Timer Control TFO CA C9 THO Timer High 0 00H THI Timer High 1 00H TH2 Timer High 2 00H TLO Timer Low 0 00H TL1 Timer Low 1 00H TL2 Timer Low 2 00H Timer Mode MO 004 SFRs are bit addressable SFRs are modified from or added t
12. 0 17 65 17 65 1 22 1 44 mm 449 031 0 25 305 933 0686 654 4651 127 1499 1499 17 40 17 40 1 07 951 4 02 18 018 0 10 216 2 16 459 inches 0180 929 9 01 0 12 9 021 0 032 0 656 0 656 0g 0 880 0 630 0 695 0 895 0 048 o 510 087 0 007 0 007 9 0041 0 085 0 085 0 165 12 9 013 0 026 o 650 0 650 0 590 0 590 0 685 0 685 0 042 0 040 0 i i Note 1 Plastic or metal protrusions of 0 01 inches maximum per side are not included SOT187 2 112610 MO 047AC OUTLINE REFERENCES EUROPEAN ISSUE DATE ETIG sse 97 12 16 TX HE 28 www dzsc Philips Semiconductors 80C51 8 bit microcontroller family 4K 8K 16K 32K Flash DIP40 plastic dual in line package 40 leads 600 mil m seating plane 0 5 TE Se T scale DIMENSIONS inch dimensions are derived from the original mm dimensions Product specification 89C51 89C52 89C54 89C58 SOT129 1 A Ay A2 UNIT b b c p g e e L M M 23 max min max 1 1 E H max 170 0 53 036 5250 141 3 60 1580 17 42 mm 47 051 40 444 oaa 023 5150 137 254 1924 305 1524 15 90 0254 225 l 0 067 0 021 0 014 2 067 0 56 0 14 0 62 0 69 inches 0 19 0 020 016 Soas aag ooog 2028 010 60 eis oso oez 001 0089 Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included OUTLINE REF
13. 16 k 32 k 256 Idle mode Serial In System Programmable devices Powerdown mode 89C51RC Programmable clock out 32 k 512 Yes Second DPTR register 89C51RD Asynchronous port reset 1024 Yes Low EMI inhibit ALE 3 16 bit timers Wake up from power down by an external interrupt ORDERING INFORMATION MEMORY SIZE MEMORY SIZE MEMORY SIZE MEMORY SIZE TERE ERATORE L AND PACKAGE RANGE MHz preme ei rene era Es pere ES 1 Contact Philips Sales for availability 2 SOT not assigned for this package outline PART NUMBER DERIVATION DEVICE NUMBER P89CXX OPERATING FREQUENCY MAX V TEMPERATURE RANGE B PACKAGE AA BB PN P89C51 FLASH AA PLCC P89C52 FLASH B 0 C to 70 C BB PQFP P89C54 FLASH E F 40 C to 85 C PN PDIP DRLRANMER FI ACH 433 IS N 2 853 2148 22592 www dzsc Philips Semiconductors Product specification 80C51 8 bit microcontroller family 4K 8K 16K 32K Flash 89C51 89C52 89C54 89C58 BLOCK DIAGRAM RAM ADDR REGISTER B REGISTER PROGRAM ADDRESS REGISTER SFRs TIMERS PROGRAM COUNTER DPTR S MULTIPLE TIMING AND CONTROL INSTRUCTION REGISTER SU01066 Www dzsc Philips Semiconductors 80C51 8 bit microcontroller family 4K 8K 16K 32K Flash LOGIC SYMBOL ADDRESS AND DATA BUS A vi i SECONDARY FUNCTIONS PIN CONF
14. 51 89C52 89C54 89C58 P PSEN Q Output data R RD signal t Time V Valid W WR signal X No longer a valid logic level Z Float Examples tav Time for address valid to ALE low tip Time for ALE low to PSEN low SU00006 Figure 14 External Program Memory Read Cycle gt tavpv P2 0 P2 7 OR A8 A15 FROM DPF INSTR IN A0 A15 FROM PCH SU00025 Figure 15 External Data Memory Read Cycle E Www dzsc Philips Semiconductors Product specification 80C51 8 bit microcontroller family 4K 8K 16K 32K Flash 89C51 89C52 89C54 89C58 r tWHLH gt INSTR IN P2 0 P2 7 OR A8 A15 FROM DPF A0 A15 FROM PCH Figure 16 External Data Memory Write Cycle SU00026 lt XLXL E CLOCK txHax tavxH WRITE TO SBUF gt txHDX txHpv gt Ri TI CDK ADK ADK QU DK KAD ce CLEAR RI SET RI SU00027 Figure 17 Shift Register Mode Timing 0 7VCC 0 2VC0C 0 1 lcHcL gt SU00009 Figure 18 External Clock Drive HE Www dzsc Philips Semiconductors Product specification 80C51 8 bit microcontroller family 4K 8K 16K 32K Flash 89C51 89C52 89C54 89C58 Voc 0 5 cc TIMING REFERENCE m POINTS a 0 2VCC 0 9 VLOADHO 1V e VLOAD a 0 2VCC 0 1 VLOAD 0 1V VOL 0 1V 0 45V NOTE NOTE AC inputs during testing are driven at Vcc 0 5 for a logic
15. 6 bit DPTR registers that address the external memory and a single bit called DPS AUXR1 bitO that allows the program code to switch between them New Register Name AUXR1 SFR Address A2H Reset Value xxxx00x0B AUXR1 A2H 7 6 5 4 3 2 1 0 fo o os Where DPS AUXR1 bit0 Switches between DPTRO and DPTR1 Select Reg DPS DPTRO 0 DPTRI 1 The DPS bit status should be saved by software when switching between DPTRO and DPTRI The GFO bit is a general purpose user defined flag Note that bit 2 is not writable and is always read as a zero This allows the DPS bit to be quickly toggled simply by executing an INC AUXR1 instruction without affecting the GF2 bit Www dzsc 19 Product specification 89C51 89C52 89C54 89C58 DPH 83H DPL 82H EXTERNAL DATA MEMORY SU00745A Figure 13 DPTR Instructions The instructions that refer to DPTR refer to the data pointer that is currently selected using the AUXR1 bit 0 register The six instructions that use the DPTR are as follows INC DPTR MOV DPTR data16 MOV A A DPTR MOVX A DPTR Increments the data pointer by 1 Loads the DPTR with a 16 bit constant Move code byte relative to DPTR to ACC Move external RAM 16 bit address to ACC Move ACC to external RAM 16 bit address MOVX DPTR A JMP A DPTR Jump indirect relative to DPTR The data pointer can be accessed on a byte by byte basis by specifyin
16. 89C54 89C58 Slave 1 SADDR 1100 0000 SADEN 1111 1110 Given 1100 000X In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves Slave 0 requires a 0 in bit 0 and it ignores bit 1 Slave 1 requires a 0 in bit 1 and bit 0 is ignored A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1 A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0 Both slaves can be selected at the same time by an address which has bit 0 0 for slave 0 and bit 1 0 for slave 1 Thus both could be addressed with 1100 0000 In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0 Slave 0 SADDR 1100 0000 SADEN 1111 1001 Given 1100 OXXO Slave 1 SADDR 1110 0000 SADEN 1111 1010 Given 1110 OXOX Slave 2 SADDR 1110 0000 SADEN 1111 1100 Given 1110 00XX In the above example the differentiation among the 3 slaves is in the lower 3 address bits Slave 0 requires that bit 0 0 and it can be uniquely addressed by 1110 0110 Slave 1 requires that bit 1 0 and it can be uniquely addressed by 1110 and 0101 Slave 2 requires that bit 2 0 and its unique address is 1110 0011 To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100 since it is necessary to make bit 2 1 to exclude slave 2 The Broadcast Address for each slave is created by taking the logical OR of SADDR and SAD
17. EN Zeros in this result are trended as don t cares In most cases interpreting the don t cares as ones the broadcast address will be FF hexadecimal Upon reset SADDR SFR address 0A9H and SADEN SFR address 0B9H are leaded with Os This produces a given address of all don t cares as well as a Broadcast address of all don t cares This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51 type UART drivers which do not make use of this feature Philips Semiconductors Product specification 80C51 8 bit microcontroller family 4K 8K 16K 32K Flash 89C51 89C52 89C54 89C58 SCON Address 98H Reset Value 0000 0000B Bit Addressable SMO FE SM1 Bit 7 6 SMODO 0 1 Function TI RI NOTE Framing Error bit This bit is set by the receiver when an invalid stop bit is detected The FE bit is not cleared by valid frames but should be cleared by software The SMODO bit must be set to enable access to the FE bit Serial Port Mode Bit 0 SMODO must 0 to access bit SMO Serial Port Mode Bit 1 SMO SM1 Mode Description Baud Rate 0 0 0 shift register fosc 12 0 1 1 1 1 8 bit UART variable 0 2 9 bit UART fosc 64 or fosc 32 al 3 9 bit UART variable Enables the Automatic Address Recognition feature in Modes 2 or 3 If SM2 1 then RI will not be set unless the received 9th data bit RB8 is 1 indicating an address and the rec
18. ERENCES EUROPEAN VERSION PROJECTION ISSUE DATE IEC JEDEC EIAJ 92 4447 SOT129 1 051608 MO 015AJ EH B REN Www dzsc Philips Semiconductors Product specification 80C51 8 bit microcontroller family 4K 8K 16K 32K Flash 89C51 89C52 89C54 89C58 QFP44 plastic quad flat package 44 leads 393010 05 A DETAL 15 1 Q sla m BASE PLANE SEATING PLANE EN www dzsc Philips Semiconductors Product specification 80C51 8 bit microcontroller family 4K 8K 16K 32K Flash 89C51 89C52 89C54 89C58 Data sheet status Data sheet Product Definition 1 status status Objective Development This data sheet contains the design target or goal specifications for product development specification Specification may change in any manner without notice Preliminary Qualification This data sheet contains preliminary data and supplementary data will be published at a later date specification Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product Product Production This data sheet contains final specifications Philips Semiconductors reserves the right to make specification changes at any time without notice in order to improve design and supply the best possible product 1 Please consult the most recently issued datasheet before initiating or completing
19. Framing Error Detection RECEIVED ADDRESS DO TO D7 PROGRAMMED ADDRESS COMPARATOR IN UART MODE 2 OR MODE 3 AND SM2 1 INTERRUPT IF REN 1 RB8 1 AND RECEIVED ADDRESS PROGRAMMED ADDRESS WHEN OWN ADDRESS RECEIVED CLEAR SM2 TO RECEIVE DATA BYTES WHEN ALL DATA BYTES HAVE BEEN RECEIVED SET SM2 TO WAIT FOR NEXT ADDRESS SU00045 Figure 9 UART Multiprocessor Communication Automatic Address Recognition c 16 www dzsc Philips Semiconductors 80C51 8 bit microcontroller family 4K 8K 16K 32K Flash Interrupt Priority Structure The 89C51 89C52 89C54 89C58 have a 6 source four level interrupt structure There are 3 SFRs associated with the four level interrupt They are the IE IP and IPH See Figures 10 11 and 12 The IPH Interrupt Priority High register makes the four level interrupt structure possible The IPH is located at SFR address B7H The structure of the IPH register and a description of its bits is shown in Figure 12 The function of the IPH SFR is simple and when combined with the IP SFR determines the priority of each interrupt The priority of each interrupt is determined as shown in the following table PRIORITY BITS pax ex INTERRUPT PRIORITY LEVEL oo 0 Level 0 lowest priority o 3 feet 1 es Level 3 highest priority Table 7 Interrupt Table Product specification 89C51 89C52 89C54 89C58 There are four interrupt levels rather than two
20. IGURATIONS vvvvY PORT2 iR SM r ADDRESS BUS SU00830 Dual In Line Package Pin Functions T2 P1 0 T2EX P1 1 P1 2 P1 5 P1 6 P1 7 RST RxD P3 0 TxD P3 1 INTO P3 2 INT1 P3 3 TO P3 4 T1 P3 5 WR P3 6 RD P3 7 XTAL2 XTAL1 Vss DUAL IN LINE PACKAGE SU01063 Voc P0 0 ADO PO 1 AD1 P0 2 AD2 P0 3 AD3 P0 4 AD4 P0 5 AD5 P0 6 AD6 P0 7 AD7 EA Vpp P2 7 A15 P2 6 A14 P2 5 A13 P2 4 A12 P2 3 A11 P2 2 A10 P2 1 A9 P2 0 A8 Product specification 89C51 89C52 89C54 89C58 Ceramic and Plastic Leaded Chip Carrier Pin Functions 5 Function NIC P1 0 T2 P1 1 T2EX P1 2 P1 3 P1 4 P1 5 P1 6 P1 7 RST P3 0 RxD NIC P3 1 TxD P3 2 INTO P3 3 INTT ONOaAhWND 18 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 NO INTERNAL CONNECTION Plastic Quad Flat Pack Pin Functions 5 Function P1 5 P1 6 P1 7 RST P3 0 RxD NIC P3 1 TxD P3 2 INTO P3 3 INTT P3 4 T0 P3 5 T1 P3 6 WR P3 7 RD XTAL2 XTAL1 1 2 3 4 5 6 8 12 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 NO INTERNAL CONNECTION Function P3 4 T0 P3 5 T1 P3 6 WR P3 7 RD XTAL2 XTAL1 Vss NIC P2 0 A8 P2 1 A9 P2 2 A10 P2 3 A11 P2 4 A12 P2 5 A13 P2 6 A14 Function Vss NIC P2 0 A8 P2 1 A9 P2 2 A10 P2 3 A11 P2 4 A12 P2 5 A13 P2 6 A14 P2 7 A15 PSEN ALE NIC EA Vpp P0 7 AD7
21. U INTEGRATED CIRCUITS DATA SFIEET 89C51 89C52 89C54 89C58 80C51 8 bit microcontroller family 4K 8K 16K 32K Flash Product specification 1999 Oct 27 Replaces Datasheets 89C51 of 1999 Apr 01 and 89C52 89C54 89C58 of 1999 Apr 01 PHILIPS Philips Semiconductors Product specification SSS E E LL SE 80C51 8 bit microcontroller family 4K 8K 16K 32K Flash 89C51 89C52 89C54 89C58 DESCRIPTION FEATURES The 89C51 89C52 89C54 89C58 contain a non volatile FLASH e 80C51 Central Processing Unit program memory that is parallel programmable For devices that are serial programmable In System Programmable ISP with a boot 9 On chip FLASH Program Memory loader see the 89C51RC 89C51RD datasheet Speed up to 33 MHz Both families are Single Chip 8 bit Microcontrollers manufactured in advanced CMOS process and are derivatives of the 80C51 microcontroller family All the devices have the same instruction set RAM expandable externally to 64 k bytes as the 80C51 Full static operation 4 level priority interrupt SELECTION TABLE FOR FLASH DEVICES 6 interrupt sources ROM EPROM RAM Size Programmable Hardware Four 8 bit I O ports Memory Size X by 8 Timer Counter Watchdog X by 8 X by 8 PCA Timer Full duplex enhanced UART Multi Time Programmable MTP devices Framing error detection 89C51 Automatic address recognition 4k 128 Power control modes 89C52 54 58 Clock can be stopped and resumed 8 k
22. a design Definitions Short form specification The data in a short form specification is extracted from a full data sheet with the same type number and title For detailed information see the relevant data sheet or data handbook Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System IEC 134 Stress above one or more of the limiting values may cause permanent damage to the device These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied Exposure to limiting values for extended periods may affect device reliability Application information Applications that are described herein for any of these products are for illustrative purposes only Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification Disclaimers Life support These products are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application Right to make changes Philips Semiconducto
23. al count input clockout see Programmable Clock Out T2EX P1 1 Timer Counter2 reload capture direction control Port 2 Port 2 is an 8 bit bidirectional I O port with internal pull ups Port 2 pins that have 1s written to them are pulled high by the internal pull ups and can be used as inputs As inputs port 2 pins that are externally being pulled low will source current because of the internal pull ups See DC Electrical Characteristics lj Port 2 emits the high order address byte during fetches from external program memory and during accesses to external data memory that use 16 bit addresses MOVX DPTR In this application it uses strong internal pull ups when emitting 1s During accesses to external data memory that use 8 bit addresses MOV Ri port 2 emits the contents of the P2 special function register Port 3 Port 3 is an 8 bit bidirectional I O port with internal pull ups Port 3 pins that have 1s written to them are pulled high by the internal pull ups and can be used as inputs As inputs port 3 pins that are externally being pulled low will source current because of the pull ups See DC Electrical Characteristics lj Port 3 also serves the special features of the 89C51 89C52 89C54 89C58 as listed below RxD P3 0 Serial input port TxD P3 1 Serial output port INTO P3 2 External interrupt INT1 P3 3 External interrupt TO P3 4 Timer 0 external input T1 P3 5 Timer 1 external input WR P3 6 External d
24. ansmit clock in modes 1 and 3 TCLK 0 causes Timer 1 overflows to be used for the transmit clock T2CON 3 Timer 2 external enable flag When set allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port EXEN2 0 causes Timer 2 to ignore events at T2EX TR2 T2CON 2 C T2 T2CON 1 Timer or counter select Timer 2 0 Internal timer OSC 12 Start stop control for Timer 2 A logic 1 starts the timer 1 External event counter falling edge triggered CP RL2 T2CON 0 Capture Reload flag When set captures will occur on negative transitions at T2EX if EXEN2 1 When cleared auto reloads will occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2 1 When either RCLK 1 or TCLK 1 this bit is ignored and the timer is forced to auto reload on Timer 2 overflow Www dzsc SU00728 Figure 1 Timer Counter 2 T2CON Control Register Philips Semiconductors Product specification 80C51 8 bit microcontroller family 4K 8K 16K 32K Flash 89C51 89C52 89C54 89C58 Table 3 Timer 2 Operating Modes RCLK TCLK CP RL2 Baud rate generator off Ul Capture Transition Timer 2 Detector Interrupt RCAP2L RCAP2H T2EX Pin Control SU00066 Figure 2 Timer 2 in Capture Mode T2MOD Address 0C9H Reset Value XXXX XX00B Not Bit Addressable
25. at a port transmit baud rate generator RCLK has the same effect for the rollover in TH2 does not set TF2 and will not generate an interrupt serial port receive baud rate With these two bits the serial port can Thus the Timer 2 interrupt does not have to be disabled when have different receive and transmit baud rates one generated by Timer 2 is in the baud rate generator mode Also if the EXEN2 Timer 1 the other by Timer 2 T2 external enable flag is set a 1 to 0 transition in T2EX Timer counter 2 trigger input will set EXF2 T2 external flag but will not cause a reload from RCAP2H RCAP2L to TH2 TL2 Therefore when Timer 2 is in use as a baud rate generator T2EX can be used as an additional external interrupt if needed Figure 6 shows the Timer 2 in baud rate generation mode The baud rate generation mode is like the auto reload mode in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16 bit value in registers RCAP2H and RCAP2L which are preset by software 12 www dzsc Philips Semiconductors 80C51 8 bit microcontroller family 4K 8K 16K 32K Flash When Timer 2 is in the baud rate generator mode one should not try to read or write TH2 and TL2 As a baud rate generator Timer 2 is incremented every state time osc 2 or asynchronously from pin T2 under these conditions a read or write of TH2 or TL2 may not be accurate The RCAP2 registers may be read but should not be written to beca
26. ata memory write strobe RD P3 7 External data memory read strobe Reset A high on this pin for two machine cycles while the oscillator is running resets the device An internal diffused resistor to Vss permits a power on reset using only an external capacitor to Vcc Address Latch Enable Output pulse for latching the low byte of the address during an access to external memory In normal operation ALE is emitted at a constant rate of 1 6 the oscillator frequency and can be used for external timing or clocking Note that one ALE pulse is skipped during each access to external data memory ALE can be disabled by setting SFR auxiliary 0 With this bit set ALE will be active only during a MOVX instruction Program Store Enable The read strobe to external program memory When executing code from the external program memory PSEN is activated twice each machine cycle except that two PSEN activations are skipped during each access to external data memory PSEN is not activated during fetches from internal program memory External Access Enable Programming Supply Voltage EA must be externally held low to enable the device to fetch code from external program memory locations 0000H to the maximum internal memory boundary If EA is held high the device executes from internal program memory unless the program counter contains an address greater than OFFFH for 4 k devices 1FFFH for 8 k devices 3FFFH for 16 k devices and 7FFFH for 32 k devices The
27. due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1 to 0 transitions during bus operations In the worst cases capacitive loading gt 100pF the noise pulse on the ALE pin may exceed 0 8V In such cases it may be desirable to qualify ALE with a Schmitt Trigger or use an address latch with a Schmitt Trigger STROBE input lo can exceed these conditions provided that no single output sinks more than 5 mA and no more than two outputs exceed the test conditions 3 Capacitive loading on ports 0 and 2 may cause the Voy on ALE and PSEN to momentarily fall below the Vcc 0 7 specification when the address bits are stabilizing 4 Pins of ports 1 2 and 3 source a transition current when they are being externally driven from 1 to 0 The transition current reaches its maximum value when Viv is approximately 2 V 5 See Figures 22 through 25 for Icc test conditions and Figure 21 for Icc vs Freq Active mode lec max 0 9 x FREQ 20 mA Idle mode IEC MAX 0 37 x FREQ 1 0 mA This value applies to Tamp 0 C to 70 C Load capacitance for port 0 ALE and PSEN 100pF load capacitance for all other outputs 80 pF Under steady state non transient conditions lor must be externally limited as follows Maximum lo per port pin 15 mA NOTE This is 85 C specification Maximum lo per 8 bit port 26 mA Maximum total Io for all outputs 71mA If loj exceeds the test condition Vo may exceed th
28. e related specification Pins are not guaranteed to sink current greater than the listed test conditions 9 ALE is tested to VoH except when ALE is off then Voy is the voltage specification 10 Pin capacitance is characterized but not tested Pin capacitance is less than 25 pF Pin capacitance of ceramic package is less than 15 pF except EA is 25 pF liL ITL lu oN HE 21 Www dzsc Philips Semiconductors Product specification 80C51 8 bit microcontroller family 4K 8K 16K 32K Flash 89C51 89C52 89C54 89C58 AC ELECTRICAL CHARACTERISTICS Tamb 0 C to 70 C or 40 C to 85 C Voc 5 V 10 Vas 0V1 2 8 3 5 Oscillator frequency Speed versions l 4J U 33 MHz TAVLL tLLAX Address hold after ALE low LL um 4 fateomtovaidinsmetonn ee 8 fm un a A amp EbwePsNOw to fs fa Dmm e PSENpuse wii ae H fe my PSENIowi val insiusioni fee 39 fm ex e _ inputinstuctionho arerPseN o po fe az 4 fiputinstuetontieatater sen __ tas 3 fe Cow 24 faseresstovandinsmuetonn Ste __ 70 ss war 74 PSENTowtoadtressfioa __ 0 __ 0 e Data Memory mm 15 16 ROpusewom See 8 y wu 19 16 W pusewan tese H moy 18 16 Roewevadomam Sea fm fm mox 1516 baant 0 aoz 116 paatoa fo __ fm uo 15 16 AtElowiovalidiam C EE 99 fm wo 15 16 AGdressto vali daan a __ 9 fm
29. eived byte is a Given or Broadcast Address In Mode 1 if SM2 1 then RI will not be activated unless a valid stop bit was received and the received byte is a Given or Broadcast Address In Mode 0 SM2 should be 0 Enables serial reception Set by software to enable reception Clear by software to disable reception The 9th data bit that will be transmitted in Modes 2 and 3 Set or clear by software as desired In modes 2 and 3 the 9th data bit that was received In Mode 1 if SM2 0 RB8 is the stop bit that was received In Mode 0 RB8 is not used Transmit interrupt flag Set by hardware at the end of the 8th bit time in Mode 0 or at the beginning of the stop bit in the other modes in any serial transmission Must be cleared by software Receive interrupt flag Set by hardware at the end of the 8th bit time in Mode 0 or halfway through the stop bit time in the other modes in any serial reception except see SM2 Must be cleared by software SMODO is located at PCON6 fosc oscillator frequency 8U00043 Www dzsc Figure 7 SCON Serial Port Control Register 15 Philips Semiconductors Product specification 80C51 8 bit microcontroller family 4K 8K 16K 32K Flash 89C51 89C52 89C54 89C58 OTOT OOOO DATA BYTE ONLY IN STOP MODE 2 3 BIT SET FE BIT IF STOP BIT IS 0 FRAMING ERROR SMO TO UART MODE CONTROL Dm IeI9I19I191 I epe e ee e e 0 SCON 7 SMO 1 SCON 7 FE SU01191 Figure 8 UART
30. er Counter which can operate as either an event timer or an event counter as selected by C T2 in the special function register T2CON see Figure 1 Timer 2 has three operating modes Capture Auto reload up or down counting and Baud Rate Generator which are selected by bits in the T2CON as shown in Table 3 Capture Mode In the capture mode there are two options which are selected by bit EXEN2 in T2CON If EXEN2 0 then timer 2 is a 16 bit timer or counter as selected by C T2 in T2CON which upon overflowing sets bit TF2 the timer 2 overflow bit This bit can be used to generate an interrupt by enabling the Timer 2 interrupt bit in the IE register If EXEN2 1 Timer 2 operates as described above but with the added feature that a 1 to 0 transition at external input T2EX causes the current value in the Timer 2 registers TL2 and TH2 to be captured into registers RCAP2L and RCAP2H respectively In addition the transition at T2EX causes bit EXF2 in T2CON to be set and EXF2 like TF2 can generate an interrupt which vectors to the same location as Timer 2 overflow interrupt The Timer 2 interrupt service routine can interrogate TF2 and EXF2 to determine which event caused the interrupt The capture mode is illustrated in Figure 2 There is no reload value for TL2 and TH2 in this mode Even when a capture event occurs from T2bEX the counter keeps on counting T2EX pin transitions or osc 12 pulses Auto Reload Mode Up or Down Coun
31. flag RI will be automatically set when the received byte contains either the Given address or the Broadcast address The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data Automatic address recognition is shown in Figure 9 The 8 bit mode is called Mode 1 In this mode the RI flag will be set if SM2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast address Mode 0 is the Shift Register mode and SM2 is ignored Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses All of the slaves may be contacted by using the Broadcast address Two special Function Registers are used to define the slave s address SADDR and the address mask SADEN SADEN is used to define which bits in the SADDR are to b used and which bits are don t care The SADEN mask can be logically ANDed with the SADDR to create the Given address which the master will use for addressing each of the slaves Use of the Given address allows multiple slaves to be recognized while excluding others The following examples will help to show the versatility of this scheme Slave 0 SADDR 1100 0000 SADEN 1111 1101 Given 1100 00X0 Www dzsc 14 Product specification 89C51 89C52
32. g the low or high byte in an instruction which accesses the SFRs See application note AN458 for more details Philips Semiconductors Product specification 80C51 8 bit microcontroller family 4K 8K 16K 32K Flash 89C51 89C52 89C54 89C58 ABSOLUTE MAXIMUM RATINGS 2 3 PARAMETER RATING UNIT Operating temperature under bias 0 to 70 or 40 to 85 Storage temperature range 65 to 150 Voltage on EA Vpp pin to Vss Voltage on any other pin to Vss Maximum lo per I O pin Power dissipation based on package heat transfer limitations not device power consumption NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied 2 This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge Nonetheless it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum 3 Parameters are valid over operating temperature range unless otherwise specified All voltages are with respect to Vss unless otherwise noted AC ELECTRICAL CHARACTERISTICS Tamb 0 C to 70 C or 40 C to 85 C CLOCK FREQUENCY SYMBOL PARAMETER 3 f UNIT 3X HE 20 Www dzsc
33. lternate functions It can be programmed 1 to input the external clock for Timer Counter 2 or 2 to output a 50 duty cycle clock ranging from 61Hz to 4MHz at a 16MHz operating frequency To configure the Timer Counter 2 as a clock generator bit C T2 in T2CON must be cleared and bit T20E in T2MOD must be set Bit TR2 T2CON 2 also must be set to start the timer The Clock Out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers RCAP2H RCAP2L as shown in this equation Oscillator Frequency 4 x 65536 RCAP2H RCAP2L Where RCAP2H RCAP2L the content of RCAP2H and RCAP2L taken as a 16 bit unsigned integer In the Clock Out mode Timer 2 roll overs will not generate an interrupt This is similar to when it is used as a baud rate generator It is possible to use Timer 2 as a baud rate generator and a clock generator simultaneously Note however that the baud rate and the Clock Out frequency will be the same External Pin Status During Idle and Power Down Mode MODE PROGRAM MEMORY ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3 ae mem 1 7 ba pae om ata ide em 7 TT Fee Daa Address Om Pomerdomn mema ba pae om Daa Powerdown Enema o o Fox b Data Daa Www dzsc Philips Semiconductors 80C51 8 bit microcontroller family 4K 8K 16K 32K Flash TIMER 2 OPERATION Timer 2 Timer 2 is a 16 bit Tim
34. mn 19 6 _ AdcressvaiatoWRioworRDIow aars __ m_ Dow 16 16 Data valdio WA vasto too 0 Cox 15 16 paanodate Wi to __ Cam e Devi w ngs roon 8 fe mar 15 16 RDlowtoaderessfot 9 fo gt oe 3 Meme mm mme T_T Dao 38 fromme pm eco fa Dao e Reme Jf T e LL Te we 18 me pp 8 T_T fa Shift Register O Shift Register fou 17 Serial port clock cycle time ter __ ao __ ne Clock rising edge to input data valid 10tcLer 133 1 Parameters are valid over operating temperature range unless otherwise specified 2 Load capacitance for port 0 ALE and PSEN 100 pF load capacitance for all other outputs 80 pF 3 Interfacing the microcontroller to devices with float times up to 45 ns is permitted This limited bus contention will not cause damage to Port 0 drivers 4 Parts are guaranteed to operate down to 0 Hz 4X HE 22 Www dzsc Philips Semiconductors 80C51 8 bit microcontroller family 4K 8K 16K 32K Flash EXPLANATION OF THE AC SYMBOLS Each timing symbol has five characters The first character is always T time The other characters depending on their positions indicate the name of a signal or the logical status of that signal The designations are A Address C Clock D Input data H Logic level high Instruction program memory contents L Logic level low or ALE Product specification 89C
35. o be executed after RETI will be the one following the instruction that put the device into Power Down Table 2 Product specification 89C51 89C52 89C54 89C58 Design Consideration When the idle mode is terminated by a hardware reset the device normally resumes program execution from where it left off up to two machine cycles before the internal reset algorithm takes control On chip hardware inhibits access to internal RAM in this event but access to the port pins is not inhibited To eliminate the possibility of an unexpected write when Idle is terminated by reset the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory ONCE Mode The ONCE On Circuit Emulation Mode facilitates testing and debugging of systems without the device having to be removed from the circuit The ONCE Mode is invoked by 1 Pull ALE low while the device is in reset and PSEN is high 2 Hold ALE low as RST is deactivated While the device is in ONCE Mode the Port 0 pins go into a float state and the other port pins and ALE and PSEN are weakly pulled high The oscillator circuit remains active While the device is in this mode an emulator or test CPU can be used to drive the circuit Normal operation is restored when a normal reset is applied Programmable Clock Out A 50 duty cycle clock can be programmed to come out on P1 0 This pin besides being a regular I O pin has two a
36. o the 80C51 SFRs Reserved bits Ducem d22 42 lt 73 el source 8 E Www dzsc 2 dk Philips Semiconductors 80C51 8 bit microcontroller family 4K 8K 16K 32K Flash FLASH EPROM MEMORY General Description The 89C51 89C52 89C54 89C58 FLASH reliably stores memory contents even after 100 erase and program cycles The cell is designed to optimize the erase and programming mechanisms In addition the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling Features FLASH EPROM internal program memory with Chip Erase Up to 64 k byte external program memory if the internal program memory is disabled EA 0 Programmable security bits 100 minimum erase program cycles for each byte 10 year minimum data retention Programming support available from many popular vendors Www dzsc Product specification 89C51 89C52 89C54 89C58 OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output respectively of an inverting amplifier The pins can be configured for use as an on chip oscillator To drive the device from an external clock source XTAL1 should be driven while XTAL2 is left unconnected There are no requirements on the duty cycle of the external clock signal because the input to the internal clock circuitry is through a divide by two flip flop However minimum and maximum high
37. rs reserves the right to make changes without notice in the products including circuits standard cells and or software described or contained herein in order to improve design and or performance Philips Semiconductors assumes no responsibility or liability for the use of any of these products conveys no license or title under any patent copyright or mask work right to these products and makes no representations or warranties that these products are free from patent copyright or mask work right infringement unless otherwise specified Philips Semiconductors Copyright Philips Electronics North America Corporation 1999 811 East Arques Avenue All rights reserved Printed in U S A P O Box 3409 Sunnyvale California 94088 3409 Date of release 10 99 Telephone 800 234 7381 Document order number 9397 750 06613 Lett make things better BEM S PHILIPS Www dzsc
38. s the 16 bit value in RCAP2L and RCAP2H to be reloaded into the timer registers TL2 and TH2 When a logic 0 is applied at pin T2EX this causes Timer 2 to count down The timer will underflow when TL2 and TH2 become equal to the value stored in RCAP2L and RCAP2H Timer 2 underflow sets the TF2 flag and causes OFFFFH to be reloaded into the timer registers TL2 and TH2 The external flag EXF2 toggles when Timer 2 underflows or overflows This EXF2 bit can be used as a 17th bit of resolution if needed The EXF2 flag does not generate an interrupt in this mode of operation LSB EXF2 RCLK CP RL2 Position Name and Significance T2CON 7 when either RCLK or TCLK 1 T2CON 6 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software TF2 will not be set Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 1 When Timer 2 interrupt is enabled EXF2 1 will cause the CPU to vector to the Timer 2 interrupt routine EXF2 must be cleared by software EXF2 does not cause an interrupt in up down counter mode DCEN 1 T2CON 5 Receive clock flag When set causes the serial port to use Timer 2 overflow pulses for its receive clock in modes 1 and 3 RCLK 0 causes Timer 1 overflow to be used for the receive clock T2CON 4 Transmit clock flag When set causes the serial port to use Timer 2 overflow pulses for its tr
39. ter In the 16 bit auto reload mode Timer 2 can be configured as either a timer or counter C T2 in T2CON then programmed to count up or down The counting direction is determined by bit DCEN Down Counter Enable which is located in the T2MOD register see Product specification 89C51 89C52 89C54 89C58 Figure 3 When reset is applied the DCEN 0 which means Timer 2 will default to counting up If DCEN bit is set Timer 2 can count up or down depending on the value of the T2EX pin Figure 4 shows Timer 2 which will count up automatically since DCEN 0 In this mode there are two options selected by bit EXEN2 in T2CON register If EXEN2 0 then Timer 2 counts up to OFFFFH and sets the TF2 Overflow Flag bit upon overflow This causes the Timer 2 registers to be reloaded with the 16 bit value in RCAP2L and RCAP2H The values in RCAP2L and RCAP2H are preset by software means If EXEN2 1 then a 16 bit reload can be triggered either by an overflow or by a 1 to 0 transition at input T2EX This transition also sets the EXF2 bit The Timer 2 interrupt if enabled can be generated when either TF2 or EXF2 are 1 In Figure 5 DCEN 1 which enables Timer 2 to count up or down This mode allows pin T2EX to control the direction of count When a logic 1 is applied at pin T2EX Timer 2 will count up Timer 2 will overflow at OFFFFH and set the TF2 flag which can then generate an interrupt if the interrupt is enabled This timer overflow also cause
40. tion Detector RCAP2L RCAP2H T2EX Pin TN To EXF2 Timer2 i Interrupt Control EXEN2 E Note availability of additional external interrupt SUO00068 Figure 6 Timer 2 in Baud Rate Generator Mode Table 4 Timer 2 Generated Commonly Used The baud rates in modes 1 and 3 are determined by Timer 2 s Baud Rates overflow rate given below Baud Rate RCAP2H RCAP2L The timer can be configured for either timer or counter operation In many applications it is configured for timer operation C T2 0 Timer operation is different for Timer 2 when it is being used as a baud rate generator Usually as a timer it would increment every machine cycle i e 1 12 the oscillator frequency As a baud rate generator it increments every state time i e 1 2 the oscillator frequency Thus the baud rate formula is as follows Modes 1 and 3 Baud Rates Oscillator Frequency 32 x 65536 RCAP2H RCAP2L Where RCAP2H RCAP2L The content of RCAP2H and RCAP2L taken as a 16 bit unsigned integer Baud Rate Generator Mode Bits TCLK and or RCLK in T2CON Table 4 allow the serial port transmit and receive baud rates to be derived from either Timer 1 or Timer 2 When TCLK 0 Timer 1 is used as the serial port transmit The Timer 2 as a baud rate generator mode shown in Figure 6 is baud rate generator When TCLK 1 Timer 2 is used as the serial valid only if RCLK and or TCLK 1 in T2CON register Note th
41. use a write might overlap a reload and cause write and or reload errors The timer should be turned off clear TR2 before accessing the Timer 2 or RCAP2 registers Table 4 shows commonly used baud rates and how they can be obtained from Timer 2 Summary Of Baud Rate Equations Timer 2 is in baud rate generating mode If Timer 2 is being clocked through pin T2 P1 0 the baud rate is _ Timer 2 Overflow Rate Baud Rate 16 Table 5 Timer 2 as a Timer Product specification 89C51 89C52 89C54 89C58 If Timer 2 is being clocked internally the baud rate is fosc Baud Rate i37 x 65536 RCAP2H RCAPAL Where fosc Oscillator Frequency To obtain the reload value for RCAP2H and RCAP2L the above equation can be rewritten as fosc RCAP2H RCAP2L 65536 s x Baud sas Timer Counter 2 Set up Except for the baud rate generator mode the values given for T2CON do not include the setting of the TR2 bit Therefore bit TR2 must be set separately to turn the timer on see Table 5 for set up of Timer 2 as a timer Also see Table 6 for set up of Timer 2 as a counter T2CON INTERNAL CONTROL EXTERNAL CONTROL 1 2 KE 3 Table 6 Timer 2 as a Counter TMOD INTERNAL CONTROL EXTERNAL CONTROL Note 1 Note 2 Auto Reload o Reload a et NOTES 1 Capture reload occurs only on timer counter overflow 2 Capture reload occurs on timer counter overflow and a 1 to 0 transition on T2EX
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PHILIPS 89C51/89C52/89C54/89C58 80C51 8 bit microcontroller family 4K/8K/16K/32K Flash handbook