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FAIRCHILD 74LCX16373 Low Voltage 16-Bit Transparent Latch with 5V Tolerant Inputs Outputs datasheet

1. 0 30 Fed ORION EXON EXO DETAIL E TYP 0 015 0 025 45 x 0 39 0 63 9036 0 108 SEATING PLANE l l eaz SEE DETAIL E ATN ye v 1 Upale Uti aeara aya nayat itt Ly FNC 0 635 0 25 a 8 TYP MS48A REV E 48 Lead Small Shrink Outline Package SSOP JEDEC MO 118 0 300 Wide Package Number MS48A 9 www fairchildsemi com ELEILXO IHL 74LCX16373 Low Voltage 16 Bit Transparent Latch with 5V Tolerant Inputs and Outputs Physical Dimensions inches millimeters unless otherwise noted Continued t 12 500 10 4 eae svi z 48 3 30 25 4a 4330 25 B s 2 qi Gi 5 3 O x 2 S HOA i 1 6 1 24 a oz e B A 7 3 19 74 PIN 1 IDENT ALL LEAD TIPS Bll ee 050 LAND PATTERN RECOMMENDATION Alaae 1 2 MAX ALL LEAD TIPS o 90t0 13 SEE URINGA im 5 id HHHP CRA Lf i 2J f L 0 09 0 20 0 50 k 0 17 0 27 01040 05 0 13 A BO C ae 12 00 TOP amp BOTTON DIMENSIONS ARE IN MILLIMETERS R0 16 GAGE PLANE RO 31 0 25 a p t 84 NOTES ii 1 A CONFORMS TO JEDEC REGISTRATION MO 183 VARIATION ED C DATE 4 97 0 8040 10 SEATING PLANE B DIMENSIONS ARE IN
2. 5 5V Note 7 2 3 3 6 20 pA Aloc Increase in Icc per Input Vin Voc 0 6V 2 3 3 6 500 uA Note 7 Outputs disabled or 3 STATE only AC Electrical Characteristics Ta 40 C to 85 C Rq 5009 Symbol Parameter Vece 3 3V 0 3V Vec 2 7V Vec 2 5V 0 2V Units C 50 pF C 50 pF C 30 pF Min Max Min Max Min Max teu Propagation Delay 5 5 4 5 5 9 1 5 6 5 tein In to On 5 5 4 5 5 9 15 65 a tPHL Propagation Delay 3 5 5 5 6 4 1 5 6 6 tai LE to On 5 55 5 6 4 15 66 i tpz Output Enable Time 1 5 6 1 5 6 5 1 5 7 9 tpzH 5 6 1 5 6 5 1 5 7 9 i tpz Output Disable Time 5 6 0 5 6 3 1 5 7 2 tpHz 5 6 0 5 6 3 1 5 7 2 Be ts Setup Time to LE 2 5 2 5 3 0 ns ty Hold Time to LE 5 5 2 0 ns tw LE Pulse Width 3 0 3 0 3 5 ns tosHL Output to Output Skew Note 8 1 0 a tosiy 1 0 Note 8 Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device The specification applies to any outputs switching in the same direction either HIGH to LOW tosHL or LOW to HIGH tog_ Parameter guaranteed by design Dynamic Switching Characteristics Vec Ta 25 C Symbol Parameter Conditions Units V Typical VoLP Quiet Output Dynamic Peak VoL C 50 pF Vin 3 3V Vi OV 3 3 0 8 7 CL 30 pF Viy 2 5V Vi OV 25 0 6 Vov Quiet Output Dynamic Valley Vo C 50 pF Viy 3 3V Vi OV 3 3 0 8 7 CL 30
3. 2V Vmi 1 5V 1 5V Vcc 2 Vmo 1 5V 1 5V Voc 2 Vy VoL 0 3V VoL 0 3V VoL 0 15V Vy Voy 0 3V Voy 0 3V Vou 0 15V www fairchildsemi com Schematic Diagram Generic for LCX Family input stage input stage Enable bud www fairchildsemi com ELEILXO IHL 74LCX16373 Physical Dimensions inches millimeters unless otherwise noted Z 0 10 B B 55 HH TN 08 7 0 10 Ala 04 0 75 bar 0 it B PIN ONE w 6 4 ja oO a re lt Bottom View NOTES A THIS PACKAGE CONFORMS TO JEDEC MO0 205 B ALL DIMENSIONS IN MILLIMETERS C LAND PATTERN RECOMMENDATION NSMD Non Solder Mask Defined 35MM DIA PADS WITH A SOLDERMASK OPENING OF 45MM CONCENTRIC TO PADS D DRAWING CONFORMS TO ASME Y14 5M 1994 BGA54ArevD 54 Ball Fine Pitch Ball Grid Array FBGA JEDEC MO 205 5 5mm Wide Package Number BGA54A www fairchildsemi com 8 Physical Dimensions inches millimeters unless otherwise noted Continued 0 620 0 630 15 75 16 00 25 0 398 0 417 LEAD 1 10 10 10 60 IDENT 0 01 0 0 25 0 291 0 299 7 40 7 59 _ cal 0 005 0 009 0 13 0 22 GAUGE Te ee 0 02040 003 0 635 0 010 j 0 0 51 0 08 0 25 0 020 0 040 TYP pfe 0 008 0 012 1 0 51 1 01 0 21
4. pF Viy 2 5V Vi OV 2 5 0 6 Capacitance Symbol Parameter Conditions Typical Units Cin Input Capacitance Voc Open V OV or Vec 7 pF Cout Output Capacitance Voc 3 3V Vi OV or Voc 8 pF Cpp Power Dissipation Capacitance Vec 3 3V V OV or Vcc f 10 MHz 20 pF www fairchildsemi com ELEILXO IHL 74LCX16373 AC LOADING and WAVEFORMS ecereric for Lcx Family tone PHL tPzH gt tpuz teats tPLz FIGURE 1 AC Test Circuit C includes probe and jig capacitance Test Switch PLH tPHL Open tezi tpiz 6V at Vec 3 3 0 3V and 2 7V Vec X 2 at Voc 2 5 0 2V tPzH PHZ GND DATA Vec Vmi IN GND tpxx toxx DATA Waveform for Inverting and Non Inverting Functions CONTROL TE Yee IN _ GND trec pe CLOCK Vmi teu foun OUTPUT Vino Vino Propagation Delay Pulse Width and t Waveforms OUTPUT a Vee CONTROL mi ais teze tez DATA OUT Vro vx VoL 3 STATE Output Low Enable and Disable Times for Logic OUTPUT T Vec CONTROL mi END tPzH thz v DATA m Woe OUT mo us 3 STATE Output High Enable and Disable Times for Logic DATA IN ts CONTROL INPUT ts MR rec OR Vmi CLEAR Setup Time Hold Time and Recovery Time for Logic y 90 90 oH 10 Vor trise and tfan FIGURE 2 Waveforms Input Characteristics f 1MHZz t t 3ns Symbol Vcc 3 3V 0 3V 2 7V 2 5V 0
5. MILLIMETERS 1 00 C DIMENSIONS ARE EXCLUSIVE OF BURRS MOLD FLASH AND TIE BAR EXTRUSIONS D DIMENSIONS AND TOLERANCES PER ANSI Y14 5M 1982 DETAIL A MTD48REVC 48 Lead Thin Shrink Small Outline Package TSSOP JEDEC MO 153 6 1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems 2 A critical component in any component of a life support which a are intended for surgical implant into the body or b support or sustain life and c whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be rea sonably expected to result in a significant injury to the user device or system whose failure to perform can be rea sonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness www fairchildsemi com www fairchildsemi com 10
6. OO 74LCX163739 O U Se FAIRCHILD SSE SEMICONDUCTOR 74LCX16373 February 1994 Revised May 2005 Low Voltage 16 Bit Transparent Latch with 5V Tolerant Inputs and Outputs General Description The LCX16373 contains sixteen non inverting latches with 3 STATE outputs and is intended for bus oriented applica tions The device is byte controlled The flip flops appear transparent to the data when the Latch Enable LE is HIGH When LE is LOW the data that meets the setup time is latched Data appears on the bus when the Output Enable OE is LOW When OE is HIGH the outputs are in a high impedance state The LCX16373 is designed for low voltage 2 5V or 3 3V Voc applications with capability of interfacing to a 5V signal environment The LCX16373 is fabricated with an advanced CMOS tech nology to achieve high speed operation while maintaining CMOS low power dissipation Features E 5V tolerant inputs and outputs E 2 3V 3 6V Vcc specifications provided E 5 4 ns tpp max Vcc 3 3V 20 uA Iog max E Power down high impedance inputs and outputs E Supports live insertion withdrawal Note 1 E 24 mA output drive Vcc 3 0V E Uses patented noise EMI reduction circuitry E Latch up performance exceeds 500 mA E ESD performance Human body model gt 2000V Machine model gt 200V E Also packaged in plastic Fine Pitch Ball Grid Array FBGA Note 1 To ensure the high impedance state during power up or down OE shoul
7. d be tied to Vcc through a pull up resistor the minimum value or the resistor is determined by the current sourcing capability of the driver Ordering Code Order Number Package Number Package Description 74LCX16373G BGA54A 54 Ball Fine Pitch Ball Grid Array FBGA JEDEC MO 205 5 5mm Wide Note 2 Note 3 74LCX16373MEA MS48A 48 Lead Small Shrink Outline Package SSOP JEDEC MO 118 0 300 Wide Note 3 74LCX16373MTD MTD48 48 Lead Thin Shrink Small Outline Package TSSOP JEDEC MO 153 6 1mm Wide Note 3 Note 2 Ordering code G indicates Trays Note 3 Devices also available in Tape and Reel Specify by appending the suffix letter X to the ordering code Logic Symbol ols l4 l5 by l ly ho h1 hz h3 h4 h5 OE LE Oo Q 0z 03 04 Os Os Oy Os Og Oro 1 2 3 44 NS 2005 Fairchild Semiconductor Corporation DS012002 www fairchildsemi com s ndjno pue s nduj juesIjOL AG YUM 49427 JUSIedsUBIL Hg 91 B6eyOA MOT ELE9LXO TPZ 74LCX16373 Connection Diagrams Pin Assignment for SSOP and TSSOP 1 2 3 4 5 6 7 8 9 Os 12345 6 JHGFEODCBA Top Thru View Pin Descriptions Pin Names Description OE Output Enable Input Active LOW LE Latch Enable Input lo lis Inputs Oo O45 Outputs NC No Connect FBGA Pin Assignments 1 2 3 4 5 6 A Oo NC OE LE NC
8. impedance mode but this does not interfere with entering new data into the latches V ry Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays www fairchildsemi com ELEILXOTVL 74LCX16373 Absolute Maximum Ratingsvnote 4 Symbol Parameter Value Conditions Units Voc Supply Voltage 0 5 to 7 0 Vv VI DC Input Voltage 0 5 to 7 0 V Vo DC Output Voltage 0 5 to 7 0 Output in 3 STATE v 0 5 to Voc 0 5 Output in HIGH or LOW State Note 5 lik DC Input Diode Current 50 Vi lt GND mA lox DC Output Diode Current 50 Vo lt GND alk 50 Vo gt Vec lo DC Output Source Sink Current 50 mA loc DC Supply Current per Supply Pin 100 mA lenp DC Ground Current per Ground Pin 100 mA TsTG Storage Temperature 65 to 150 C Recommended Operating Conditions note 6 Symbol Parameter Min Max Units Vec Supply Voltage Operating 2 0 3 6 y Data Retention 1 5 3 6 VI Input Voltage 0 5 5 V Vo Output Voltage HIGH or LOW State 0 Voc v 3 STATE 0 5 5 lon lo Output Current Vec 3 0V 3 6V 24 Vec 2 7V 3 0V 12 mA Vec 2 3V 2 7V 8 Ta Free Air Operating Temperature 40 85 C AVAV Input Edge Rate Viy 0 8V 2 0V Vcc 3 0V 0 10 ns V Note 4 The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed The device
9. lo B O O NC NC P Ip c O4 O3 Vcc Vcc Ig l4 D Os Os GND GND i ls E Og O GND GND lg F Oio Og GND GND tg ho G O12 On Vec Ycee l4 lho H Oy Os NC NC hs la J Ois NC OE LE NC lis Truth Tables Inputs Outputs LE OE Ip l Op 07 X H X Z H L L L H L H H L L x Oo Inputs Outputs LE OE Ig lis Os 015 X H X Z H L L L H L H H L L x Oo H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance Oo Previous Op before HIGH to LOW transition of Latch Enable www fairchildsemi com Functional Description The LCX16373 contains sixteen D type latches with 3 STATE standard outputs The device is byte controlled with each byte functioning identically but independent of the other Control pins can be shorted together to obtain full 16 bit operation The following description applies to each byte When the Latch Enable LE input is HIGH data on the Ip enters the latches In this condition the latches are transparent i e a latch output will change state each time Logic Diagrams its input changes When LE is LOW the latches store information that was present on the inputs a setup time preceding the HIGH to LOW transition of LE The 3 STATE standard outputs are controlled by the Output Enable OE input When OE is LOW the standard out puts are in the 2 state mode When OE is HIGH the stan dard outputs are in the high
10. should not be operated at these limits The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings The Recom mended Operating Conditions table will define the conditions for actual device operation Note 5 l Absolute Maximum Rating must be observed Note 6 Unused inputs must be held HIGH or LOW They may not float DC Electrical Characteristics Vec Ta 40 C to 85 C Symbol Parameter Conditions Units V Min Max Vin HIGH Level Input Voltage 2 3 2 7 AZ v 2 7 3 6 2 0 ViL LOW Level Input Voltage 2 3 2 7 0 7 v 2 7 3 6 0 8 VoH HIGH Level Output Voltage lop 100 pA 2 3 3 6 Voc 0 2 lon 8 mA 2 3 18 lon 12 mA 27 2 2 v lon 18 mA 3 0 2 4 lon 24 MA 3 0 2 2 VoL LOW Level Output Voltage lo 100 pA 2 3 3 6 0 2 loL 8 mA 2 3 0 6 lol 12 mA 2 7 0 4 v loL 16 mA 3 0 0 4 loL 24 mA 3 0 0 55 l Input Leakage Current 0 lt V lt 5 5V 2 3 3 6 5 0 uA loz 3 STATE Output Leakage 0 lt Vo lt 5 5V pass 450 nA Vi Vin Or Vit lofFF Power Off Leakage Current Vi or Vo 5 5V 0 10 uA www fairchildsemi com 4 DC Electrical Characteristics Continued Vec Ta 40 C to 85 C Symbol Parameter Conditions Units V Min Max loc Quiescent Supply Current Vi Vcc or GND 2 3 3 6 20 3 6V lt Vj Vo lt

FAIRCHILD 74LCX16373 Low Voltage 16-Bit Transparent Latch with 5V Tolerant Inputs Outputs datasheet

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