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FAIRCHILD 74LCX16245 Low Voltage 16-Bit Bidirectional Transceiver with 5V Tolerant Inputs Outputs handbook

1. Symbol Parameter Min Max Units Voc Supply Voltage Operating 2 0 3 6 v Data Retention 1S 3 6 VI Input Voltage 0 5 5 V Vo Output Voltage HIGH or LOW State 0 Voc y 3 STATE 0 5 5 lon lo Output Current Voc 3 0V 3 6V 24 Voc 2 7V 3 0V 12 mA Voc 2 3V 2 7V 8 Ta Free Air Operating Temperature 40 85 C AVAV Input Edge Rate Viy 0 8V 2 0V Vcc 3 0V 0 10 ns V Note 4 The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings The Recom mended Operating Conditions table will define the conditions for actual device operation Note 5 l Absolute Maximum Rating must be observed Note 6 Unused inputs or I O s must be held HIGH or LOW They may not float DC Electrical Characteristics Vec Ta 40 C to 85 C l Symbol Parameter Conditions Units V Min Max Vin HIGH Level Input Voltage 2 3 2 7 Ae v 2 7 3 6 2 0 Vit LOW Level Input Voltage 2 3 2 7 0 7 V 2 7 3 6 0 8 VoH HIGH Level Output Voltage oH 100 pA 2 3 3 6 Vcc 0 2 oH 8 mA 2 3 1 8 oH 12 mA 2 7 2 2 v oH 18 mA 3 0 2 4 oH 24 mA 3 0 2 2 VoL LOW Level Output Voltage oL 100 pA 2 3 3 6 0 2 oL 8mA 2 3 0 6 oL 12 mA 2 7 0 4 v oL 16 mA 3 0 0 4 oL
2. OE NC Ao B Bo B NC NC Ay Ao c B4 B3 Vcc Vcc As A4 D Bg Bs GND GND As Ag E Bg B7 GND GND A7 Ag F Bio Bg GND GND Ag Aio G Bio Bit Vcc Veo An A12 H B44 Bis NC NC A43 A14 J Bys NC T R OE NC Ais Truth Tables Inputs Outputs OE T R L Bus Bo B7 Data to Bus A A7 L H Bus Ag A7 Data to Bus By B7 x HIGH Z State on Ag A7 By By Inputs Outputs OE T R2 L L Bus Bg B45 Data to Bus Ag A415 L H Bus Ag A45 Data to Bus Bg By5 H X HIGH Z State on Ag A45 Bg By5 H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance ETO Note Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays www fairchildsemi com Absolute Maximum Ratingsvnote 4 Symbol Parameter Value Conditions Units Voc Supply Voltage 0 5 to 7 0 V VI DC Input Voltage 0 5 to 7 0 V Vo DC Output Voltage 0 5 to 7 0 Output in 3 STATE v 0 5 to Voc 0 5 Output in HIGH or LOW State Note 5 lik DC Input Diode Current 50 Vi lt GND mA lox DC Output Diode Current 50 Vo lt GND m 50 Vo gt Vcc lo DC Output Source Sink Current 50 mA loc DC Supply Current per Supply Pin 100 mA lenb DC Ground Current per Ground Pin 100 mA Tstg Storage Temperature 65 to 150 C Recommended Operating Conditions note 6
3. 0 620 0 630 15 75 16 00 25 0 398 0 417 LEAD 1 10 10 10 60 IDENT 0 01 0 0 25 291 0 299 7 40 7 59 moo 0 005 0 009 T 13 0 22 S Les 0 025 1p GAUGE PLANE 0 02040 003 0 635 0 010 o 0 51 0 08 0 25 k 020 0 040 TYP pff 0 008 0 012 1 0 51 1 01 0 21 0 30 Oo o 003 0 08 D DETAIL E TYP 0 015 0 025 0 096 0 108 45 To 39 0 63 SEATING PLANE 2 44 2 74 SEE DETAIL ae v gt gt ena ee Lo TI of A Spare HE L 9 025 TYP 0 10 MIN ves 0 635 0 25 0 8 TYP MS48A REV E 48 Lead Small Shrink Outline Package SSOP JEDEC MO 118 0 300 Wide Package Number MS48A www fairchildsemi com 8 Physical Dimensions inches millimeters unless otherwise noted Continued t 12 50 0 10 i 4 aa e z 48 3 30 25 4a 43 30 25 B ci 3 8 qi a 3 wo 3J O 2 2 HEAT i i e on a BEE H 3 QUUUUE PIN 1 IDENT ALL LEAD TIPS all ere 0 50 LAND PATTERN RECOMMENDATION Ajaile 1 2 MAX ALL LEAD TIPS o 90t9 13 ae i 3 HHHP HHHHHHE I i z L 0 09 0 20 o 50 te 0 17 0 27 0100 0
4. 24 mA 3 0 0 55 l Input Leakage Current 0 lt V lt 5 5V 2 3 3 6 5 0 uA loz 3 STATE I O Leakage 0 lt Vo lt 5 5V 2 3 3 6 5 0 uA Vi Vin or Vit loff Power Off Leakage Current Vi or Vo 5 5V 0 10 LA 3 www fairchildsemi com SVZ9LXD1bZ 74LCX16245 DC Electrical Characteristics continued Vec Ta 40 C to 85 C Symbol Parameter Conditions Units V Min Max loc Quiescent Supply Current Vi Vcc or GND 2 3 3 6 20 3 6V lt Vi Vo lt 5 5V Note 7 2 3 3 6 20 nA Alce Increase in Icc per Input Vin Voc 0 6V 2 3 3 6 500 uA Note 7 Outputs disabled or 3 STATE only AC Electrical Characteristics Ta 40 C to 85 C R 5009 Symbol Saramet Vec 3 3V 0 3V Vec 2 7V Vec 2 5V 0 2V Units C 50 pF C 50 pF C 30 pF Min Max Min Max Min Max PHL Propagation Delay 1 5 4 5 1 5 5 2 1 5 5 4 PLH An to Bn or By to An 1 5 4 5 1 5 5 2 1 5 5 4 PZL Output Enable Time 1 5 6 5 1 5 7 2 1 5 8 5 PZH 1 5 6 5 1 5 7 2 1 5 8 5 1 PLZ Output Disable Time 1 5 6 4 1 5 6 9 1 5 7 7 PHZ 1 5 6 4 1 5 6 9 1 5 7 7 ii OSHL Output to Output Skew 1 0 Ss Note 8 1 0 j Dynamic Switching Characteristics Note 8 Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device The specification applies to any outputs switching in the same direction eithe
5. 5 0 13 A BO CO a 12 00 TOP amp BOTTOM DIMENSIONS ARE IN MILLIMETERS R0 16 GAGE PLANE RO 31 ez t 84 f NOTES ii 1 A CONFORMS TO JEDEC REGISTRATION MO 153 VARIATION ED lt a DATE 4 97 0 6040 10 SEATING PLANE B DIMENSIONS ARE IN MILLIMETERS 1 00 C DIMENSIONS ARE EXCLUSIVE OF BURRS MOLD FLASH AND TIE BAR EXTRUSIONS D DIMENSIONS AND TOLERANCES PER ANSI Y14 5M 1982 DETAIL A MTD48REVC 48 Lead Thin Shrink Small Outline Package TSSOP JEDEC MO 153 6 1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems 2 A critical component in any component of a life support sjndjno pue s nduj JuesajOL AG YUM 13A OSUVLIL EUOI DO IPIG 49 94 HLY MOT GHZOLXD TPZ which a are intended for surgical implant into the body or b support or sustain life and c whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be rea sonably expected to result in a signific
6. O O 74LCX162456X 0 0 EMM FAIRCHILD SESE SEMICONDUCTOR 74LCX16245 February 1994 Revised May 2005 Low Voltage 16 Bit Bidirectional Transceiver with 5V Tolerant Inputs and Outputs General Description The LCX16245 contains sixteen non inverting bidirectional buffers with 3 STATE outputs and is intended for bus ori ented applications The device is designed for low voltage 2 5V or 3 3V Vcc applications with capability of interfac ing to a 5V signal environment The device is byte con trolled Each byte has separate control inputs which could be shorted together for full 16 bit operation The T R inputs determine the direction of data flow through the device The OE inputs disable both the A and B ports by placing them in a high impedance state The LCX16245 is fabricated with an advanced CMOS tech nology to achieve high speed operation while maintaining CMOS low power dissipation Features E 5V tolerant inputs and outputs E 2 3V 3 6V Vcc specifications provided E 4 5 ns tpp max Voc 3 3V 20 uA Iog max E Power down high impedance inputs and outputs E Supports live insertion withdrawal Note 1 E 24 mA output drive Vcc 3 0V E Uses patented noise EMI reduction circuitry E Latch up performance exceeds 500 mA E ESD performance Human body model gt 2000V Machine model gt 200V E Also packaged in plastic Fine Pitch Ball Grid Array FBGA Note 1 To ensure the high impedance state during power up
7. ROL INPUT ts MR rec OR Vmi CLEAR Setup Time Hold Time and Recovery Time for Logic Vou 90 90 10 10 Vor tise and tran FIGURE 2 Waveforms Input Characteristics f 1MHz t ty 3ns Symbol Vcc 3 3V 0 3V 2 7V 2 5V 0 2V Vmi 1 5V 1 5V Voc 2 Vimo 1 5V 1 5V Voc 2 Vy Vor 0 3V Vor 0 3V Vor 0 15V Vy Vou 0 3V Vou 0 3V Vou 0 15V www fairchildsemi com SvVZ9LXD1vZ 74LCX16245 Schematic Diagram Generic for LCX Family input stage www fairchildsemi com Physical Dimensions inches millimeters unless otherwise noted 7 0 10 B Ba 5 5 A 0 8 A 0 4 0 8 gt 0 10 Ala 0 75 bar I oO iL B PIN ONE w 6 4 O a 1 lt Bottom View Jf 0 15 NOTES A THIS PACKAGE CONFORMS TO JEDEC MO0 205 B ALL DIMENSIONS IN MILLIMETERS C LAND PATTERN RECOMMENDATION NSMD Non Solder Mask Defined 35MM DIA PADS WITH A SOLDERMASK OPENING OF 45MM CONCENTRIC TO PADS D DRAWING CONFORMS TO ASME Y14 5M 1994 BGA54ArevD 54 Ball Fine Pitch Ball Grid Array FBGA JEDEC MO 205 5 5mm Wide Package Number BGA54A 7 www fairchildsemi com SvVZ9LXD1vZ 74LCX16245 Physical Dimensions inches millimeters unless otherwise noted Continued
8. ant injury to the user device or system whose failure to perform can be rea sonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness www fairchildsemi com www fairchildsemi com Copyright Each Manufacturing Company All Datasheets cannot be modified without permission This datasheet has been download from www AllDataSheet com 100 Free DataSheet Search Site Free Download No Register Fast Search System www AllDataSheet com
9. or down OE should be tied to Vcc through a pull up resistor the minimum value or the resistor is determined by the current sourcing capability of the driver Ordering Code Order Number Package Number Package Description 74LCX16245G BGA54A 54 Ball Fine Pitch Ball Grid Array FBGA JEDEC MO 205 5 5mm Wide Note 2 Note 3 74LCX16245MEA MS48A 48 Lead Small Shrink Outline Package SSOP JEDEC MO 118 0 300 Wide Note 3 74LCX16245MTD MTD48 48 Lead Thin Shrink Small Outline Package TSSOP JEDEC MO 153 6 1mm Wide Note 3 Note 2 Ordering code G indicates Trays Note 3 Devices also available in Tape and Reel Specify by appending the suffix letter X to the ordering code Logic Symbol Ag Al Ap Az Ag As Ag Ay Ag Ag Aig Ary Ara Ays Ag Ais 2005 Fairchild Semiconductor Corporation DS012001 www fairchildsemi com sjndjno pue s nduj JuesajOL AG YUM 13A OSULIL EUOI DO IPIG 49 94 HLA MOT GHZILXD TPZ 74LCX16245 Connection Diagrams Pin Assignment for SSOP and TSSOP JHGFEODCBA 1 2345 6 Top Thru View Logic Diagrams T R Pin Descriptions Pin Names Description OE Output Enable Input TR Transmit Receive Input Ao Ai5 Side A Inputs or 3 STATE Outputs Bo Bi5 Side B Inputs or 3 STATE Outputs NC No Connect FBGA Pin Assignments 1 2 3 4 5 6 A Bo NC T R
10. r HIGH to LOW togy _ or LOW to HIGH tos Parameter guaranteed by design Vec Ta 25 C Symbol Parameter Conditions Units V Typical VoLP Quiet Output Dynamic Peak VoL C 50 pF Vip 3 3V Vi OV 3 3 0 8 v C 30 pF Vip 2 5V Viu OV 2 5 0 6 Votv Quiet Output Dynamic Valley VoL C 50 pF Vin 3 3V Vi OV 3 3 0 8 4 C 30 pF Vip 2 5V Viu OV 2 5 0 6 Capacitance Symbol Parameter Conditions Typical Units Cin Input Capacitance Vec Open V OV or Vec 7 pF Cio Input Output Capacitance Vec 3 3V Vi OV or Vec 8 pF Cpp Power Dissipation Capacitance Voc 3 3V V OV or Vec f 10 MHz 20 pF www fairchildsemi com AC LOADING and WAVEFORMS ceneric for Lcx Family FIGURE 1 AC Test Circuit C includes probe and jig capacitance Test Switch teLH PHL Open tpz tpiz 6V at Voc 3 3 0 3V Voc x2 at Vec 2 5 0 2V tPZH PHZ GND P pxx DATA Waveform for Inverting and Non Inverting Functions CONTROL a Yee IN GND trec pe CLOCK Vmi teu foun OUTPUT Vino Via Propagation Delay Pulse Width and t Waveforms OUTPUT Ta Yee CONTROL mi ate teze tpez DATA OUT Vro vx VoL 3 STATE Output Low Enable and Disable Times for Logic OUTPUT a Yee CONTROL mi ENE tPzH thz v DATA m yn OUT mo i 3 STATE Output High Enable and Disable Times for Logic DATA IN ts CONT

FAIRCHILD 74LCX16245 Low Voltage 16-Bit Bidirectional Transceiver with 5V Tolerant Inputs Outputs handbook

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