Texas lnstruments bq2050 handbook
Contents
1. OFh Read SAEH7 SAEH6 SAEH5 SAEH4 SAEH3 SAEH2 SAEH1 SAEHO ister Scaled available SAEL lenergy low byte regis 10h Read SAEL7 SAEL6 SAEL5 SAEL4 SAEL3 SAEL2 SAEL1 SAELO ter RST Reset register 39h Write RST 0 0 0 0 0 0 0 Note n u not used 11 bq2050 The capacity inaccurate flag CI is used to warn the user that the battery has been charged a substantial number of times since LMD has been updated The CI flag is asserted on the 64th charge after the last LMD update or when the bq2050 is reset The flag is cleared after an LMD update The CI values are FLGS1 Bits 7 6 5 4 3 2 1 0 z z CI S p S Where Cl is 0 When LMD is updated with a valid full dis charge 1 After the 64th valid charge action with no LMD updates or the bq2050 is reset The valid discharge flag VDQ is asserted when the bq2050 is discharged from NAC LMD The flag remains set until either LMD is updated or one of three actions that can clear VDQ occurs The self discharge count register SDCR has exceeded the maximum acceptable value 4096 counts for an LMD update A valid charge action sustained at Vsro gt Vsrq for at least 256 NAC counts m The EDV1 flag was set at a temperature below 0 C The VDQ values are FLGS1 Bits 4 3 VDQ Where VDQ is 0 SDCR gt 4096 subse2. 2 4V VSB 256 VSB Register Bits 4 3 VSB4 VSB3 7 VSB7 6 VSB6 5 VSB5 2 VSB2 VSB1 VSBO Voltage Threshold Register VTS The end of discharge threshold voltages EDV1 and EDVF can be set using the VTS register address OCh The read write VTS register sets the EDV1 trip point EDVF is set 50mV below EDV1 The default value in the VTS register is A2h representing EDV1 1 52V and EDVF 1 47V EDV1 2 4V VTS 256 14 VTS Register Bits 4 3 VTS4 VTS3 1 VTS1 7 VTS7 6 VTS6 5 VTS5 2 VTS2 0 VTSO Compensated Available Charge Registers CACH CACL The read only CACH high byte register address 0Dh and the read only CACL low byte register address OEh represent the available charge compensated for discharge rate and temperature CACH and CACL use piece wise corrections as outlined in Tables 3A 3B 4A and 4B and will vary as conditions change The NAC and LMD registers are not affected by the discharge rate and temperature Scaled Available Energy Registers SAEH SAEL The read only SAEH high byte register address 0Fh and the read only SAEL low byte register address 10h are used to scale battery voltage and CAC to a value which can be translated to watt hours remaining under the present conditions SAEL and SAEH may be converted to mWh using the formula on page 7 Reset Register
3. 2 1 0 ADO AD6 AD5 AD4 AD3 AD2 AD1 LSB 10 Primary Status Flags Register FLGS1 The read only FLGS1 register address 01h contains the primary bq2050 flags The charge status flag CHGS is asserted when a valid charge rate is detected Charge rate is deemed valid when Vsro gt Vsrq A Vsro of less than Vsrq or discharge activity clears CHGS The CHGS values are FLGS1 Bits 7 6 5 4 3 2 1 0 CHGS Where CHGS is 0 Either discharge activity detected or Vsro lt VsrQ 1 Vsro gt Vsrq The battery replaced flag BRP is asserted whenever the bq2050 is reset either by application of Vcc or by a serial port command BRP is reset when either a valid charge action increments NAC to be equal to LMD or a valid charge action is detected after the EDV1 flag is as serted BRP 1 signifies that the device has been reset The BRP values are FLGS1 Bits 7 6 5 4 3 2 1 0 BRP Where BRP is 0 Battery is charged until NAC LMD or dis charged until the EDV1 flag is asserted 1 _bq2050 is reset bq2050 Table 7 bq2050 Command and Status Registers Loc Read Control Field Symbol Register Name hex Write 7 msB __6 5 4 3 2 1 o LSB CMDR Command register 00h Write W R AD6 AD5 AD4 AD3 AD2 AD1 ADO FLGS1 a status flags 01h Read CHGS BRP nu CI VDQ nu EDV1 EDVF TMP Temperature re
4. FLGS2 Bits 1 0 0 0 40 C lt T lt 50 C 1 6 5 43 1 0 0 1 50 C lt T lt 60 C DRA DRL DRO y enj iin 1 0 L 0 60 C lt T lt 70 C The discharge rate flags DR2 0 are bits 6 4 1 0 1 1 70 C lt T lt 80 C 1 1 0 0 T gt 80 C DR2 DR1 DRO Discharge Rate 0 0 0 DRATE lt 0 5C 0 1 0 5C lt DRATE lt 2C TMPGG Gas Gauge Bits 0 1 DRATE gt 2C OVLD 1 7 6 5 4 3 2 1 0 They are used to determine the current discharge re gime as follows GG3 GG2 GG1 GGO FLGS2 Bits Nominal Available Charge Registers 7 6 5 4 3 2 1 0 NACH NACL e lie i coil et ce 1 ee cle The read write NACH high byte register address 03h and the read only NACL low byte register address 17h are the main gas gauging register for the bq2050 The NAC registers are incremented during charge actions and decre mented during discharge and self discharge actions The correction factors for charge discharge efficiency are applied automatically to NAC NACH and NACL are set to 0 dur ing a bq2050 reset Writing to the NAC registers affects the available charge counts and therefore affects the bq2050 gas gauge opera tion Do not write the NAC registers to a value greater than LMD Battery Identification Register BATID The read write BATID register address 04h is avail able for use by the system to determine the type of bat tery pack The BATID contents are retained as long as Vcc is greater than 2V The contents of BATID have no effect on
5. RDQ Internal pulldown 500 KQ VsR Sense resistor input 0 3 2 0 V Ne ue peas ge RSR SR input impedance 10 MQ 200mV lt VsR lt Vcc Vin Logic input high Vcc 0 2 V___ PROGi PROGe Vin Logic input low Vss 0 2 V__ PROGi PROG Viz Logic input Z float float V PROG1 PROG6 VOLSL SEGx output low low Voc 0 1 V Mabe a lt 1 75mA VoLsH SEGx output low high Vcc 0 4 V a lt 11 0mA VoutcL LCOM output high low Vcc Vcc 0 3 V_ Vcc 8V Iontcom 5 25mA VoutcH LCOM output high high Vcc Vcc 0 6 V Vcc 6 5V Iontcom 33 0mA lin PROG 1 input high current 1 2 uA Vproa Vcc 2 IL PROG1 input low current 1 2 uA Vprog Vcc 2 IomLcom LCOM source current 33 mA At Vonucn Vcc 0 6V Tots SEG sink current 11 0 mA At Vors 0 4V Tou Open drain sink current 5 0 mA no Vss 0 8V VoL Open drain output low 0 5 V IoL lt 5mA DQ VIHDQ DQ input high 2 5 V DQ VILDQ DQ input low 0 8 V DQ Remoa Sot palp or pildosi 2o Ko PROGIPROG RrLoar Float state external impedance 5 MQ PROG PROGe Note All voltages relative to Vss 17 bq2050 Serial Communication Timing Specification TA Topr Symbol Parameter Minimum Typical Maximum Unit Notes tcycH Cycle time host to bq2050 3 ms See note tcycB Cycle time bq2050 to host 3 6 ms tsTRH Start hold host to bq2050 5 ns tsTRB Start ho
6. RST The reset register address 39h enables a software controlled reset of the device By writing the RST regis ter contents from 00h to 80h a bq2050 reset is per formed Setting any bit other than the most significant bit of the RST register is not allowed and results in im proper operation of the bq2050 Resetting the bq2050 sets the following a LMD PFC a CPI VDQ NACH and NACL 0 m Cland BRP 1 Note Self discharge is disabled when PROGs H Display The bq2050 can directly display capacity information using low power LEDs If LEDs are used the program pins should be resistively tied to Vcc or Vss for a pro gram high or program low respectively The bq2050 displays the battery charge state in relative mode In relative mode the battery charge is represented as a percentage of the LMD Each LED segment repre sents 20 of the LMD The capacity display is also adjusted for the present bat tery temperature The temperature adjustment reflects the available capacity at a given temperature but does not affect the NAC register The temperature adjust ments are detailed in the CACH and CACL register de scriptions When DISP is tied to Vcc the SEGi 5 outputs are inac tive When DISP is left floating the display becomes ac tive whenever the bq2050 detects a charge in progress Vsro gt Vsrq When pulled low the segment outputs be come active for a period of four seconds 0 5 seconds The segme
7. Vcc 3 0 6 5V Vss System ground bq2050 Pin Descriptions LCOM SEG SEG5 PROG PROG2 PROG PROG4 PROG5 PROGe N C LED common output Open drain output switches Vcc to source current for the LEDs The switch is off dur ing initialization to allow reading of the soft pull up or pull down program resistors LCOM is also high impedance when the dis play is off LED display segment outputs dual func tion with PROG1 PROGe Each output may activate an LED to sink the current sourced from LCOM Programmed full count selection inputs dual function with SEG1 SEG2 These three level input pins define the pro grammed full count PFC thresholds de scribed in Table 2 Power gauge rate selection inputs dual function with SEG3 SEGa These three level input pins define the scale factor described in Table 2 Self discharge rate selection dual func tion with SEGs This three level input pin defines the selfdischarge and battery compensation fac tors as shown in Table 1 Capacity initialization selection This three level pin defines the battery state of charge at reset as shown in Table 1 No connect SR DISP SB RBI DQ REF Vcc Vss Sense resistor input The voltage drop Vsr across the sense re sistor Rs is monitored and integrated over time to interpret charge and discharge activ ity The SR input is tied between the nega tive terminal of the battery and the sense re
8. break communication are given in the serial communi cation timing specification and illustration sections Communication with the bq2050 is always performed with the least significant bit being transmitted first Figure 3 shows an example of a communication sequence to read the bq2050 NAC register bq2050 Written by Host to bq2050 Received by Host to bq2050 l CMDR 03h NAC 65h LSB MSB LSB MSB Break 11000000 10100110 TD205002 eps Figure 3 Typical Communication With the bq2050 bq2050 Registers The bq2050 command and status registers are listed in Table 7 and described below Command Register CMDR The write only CMDR register is accessed when eight valid command bits have been received by the bq2050 The CMDR register contains two fields a WAR bit m Command address The WR bit of the command register is used to select whether the received command is for a read or a write function The W R values are CMDR Bits 4 3 7 WR 6 Where W R is 0 The bq2050 outputs the requested register con tents specified by the address portion of CMDR The following eight bits should be written to the register specified by the address por tion of CMDR The lower seven bit field of CMDR contains the address portion of the register to be accessed Attempts to write to invalid addresses are ignored CMDR Bits 7 6 5 4 3
9. sistor Vsr lt Vss indicates discharge and Vsr gt Vss indicates charge The effective voltage drop Vsro as seen by the bq2050 is Vsr Vos Display control input DISP high disables the LED display DISP tied to Vcc allows PROGx to connect directly to Vcc or Vss instead of through a pull up or pull down resistor DISP floating allows the LED display to be active during charge DISP low activates the display See Table 1 Secondary battery input This input monitors the battery cell voltage potential through a high impedance resis tive divider network for end of discharge voltage EDV thresholds and battery re moved Register backup input This pin is used to provide backup potential to the bq2050 registers during periods when Vcc lt 3V A storage capacitor or a battery can be connected to RBI Serial I O pin This is an open drain bidirectional pin Voltage reference output for regulator REF provides a voltage reference output for an optional micro regulator Supply voltage input Ground Functional Description General Operation The bq2050 determines battery capacity by monitor ing the amount of current input to or removed from a rechargeable battery The bq2050 measures dis charge and charge currents measures battery volt age estimates self discharge monitors the battery for low battery voltage thresholds and compensates for temperature and charge discharge rates The cur rent measurement is
10. 80 1 160 1 320 1 640 1 1280 1 2560 count H H 49152 614 307 154 76 8 38 4 19 2 mVh H Z 45056 563 282 141 70 4 35 2 17 6 mVh H L 40960 512 256 128 64 0 32 0 16 0 mVh Z H 36864 461 230 115 57 6 28 8 14 4 mVh Z Z 33792 422 211 106 53 0 26 4 13 2 mVh Z L 30720 384 192 96 0 48 0 24 0 12 0 mVh L H 27648 346 173 86 4 43 2 21 6 10 8 mVh L 25600 320 160 80 0 40 0 20 0 10 0 mVh L L 22528 282 141 70 4 35 2 17 6 8 8 mVh Ver cguyalneto 2 90 45 22 5 11 25 5 6 2 8 mV counts sec nom Select PFC 30720 counts or 48mVh PROG float PROG2 low PROGs high PROGa float PROGs float PROG float The initial full battery capacity is 48mVh 960mAh until the bq2050 learns a new capacity with a qualified discharge from full to EDV1 Nominal Available Capacity NAC NAC counts up during charge to a maximum value of LMD and down during discharge and self dis charge to 0 NAC is reset to 0 on initialization and on the first valid charge following discharge to EDV1 To prevent overstatement of charge during periods of overcharge NAC stops incrementing when NAC LMD Discharge Count Register DCR The DCR counts up during discharge independent of NAC and could continue increasing after NAC has decremented to 0 Prior to NAC 0 empty battery both discharge and self discharge increment the DCR After NAC 0 only discharge increments the DCR The DCR resets to 0 when NAC LMD The D
11. CR does not roll over but stops counting when it reaches FFFFh The DCR value becomes the new LMD value on the first charge after a valid discharge to Vepv1 if No valid charge initiations charges greater than 256 NAC counts where Vsro gt Vsrq occurred dur ing the period between NAC LMD and EDV1 de tected The self discharge count is not more than 4096 counts 8 to 18 of PFC specific percentage threshold determined by PFC The temperature is gt 0 C when the EDV1 level is reached during discharge The valid discharge flag VDQ indicates whether the present discharge is valid for LMD update Scaled Available Energy SAE SAE is useful in determining the available energy within the battery and may provide a more useful capacity reference in battery chemistries with sloped voltage profiles during discharge SAE may be converted to a mWh value using the following formula bq2050 E mWh SAEH 256 SAEL 2 4 SCALE Ry Ray Rs Rp where Rpi Rpg and Rs are resistor values in ohms SCALE is the selected scale from Table 2 SAEH and SAEL are digital values read via DQ 6 Compensated Available Capacity CAC CAC counts similar to NAC but contains the avail able capacity compensated for discharge rate and temperature Charge Counting Charge activity is detected based on a positive voltage on the Vsr input If charge activity is detected the bq2050 increments NAC at a rate proportion
12. O0 O0 BQ2050 0 O mae UNITRODE Features gt Conservative and repeatable measurement of available capac ity in Lithium Ion rechargeable batteries gt Designed for battery pack inte gration 120A typical operating current Small size enables imple mentations in as little as 1 square inch of PCB gt Integrate within a system or as a stand alone device Display capacity via single wire serial communication port or direct drive of LEDs gt Measurements compensated for current and temperature gt Self discharge compensation us ing internal temperature sensor gt 16 pin narrow SOIC bq2050 Lithium lon Power Gauge IC General Description The bq2050 Lithium Ion Power Gauge IC is intended for battery pack or in system installation to maintain an accurate record of available battery capacity The IC monitors a voltage drop across a sense resistor connected in series between the negative battery termi nal and ground to determine charge and discharge activity of the battery Compensations for bat tery temperature and rate of charge or discharge are applied to the charge discharge and self discharge calculations to provide available ca pacity information across a wide range of operating conditions Bat tery capacity is automatically recali brated or learned in the course of a discharge cycle from full to empty Nominal available capacity may be directly indicated u
13. P Temperature Bits 5 4 3 TMP2 TMP1 7 6 TMP3 2 TMP4 The bq2050 contains an internal temperature sensor The temperature is used to set charge and discharge ef ficiency factors as well as to adjust the self discharge co efficient The temperature register contents may be translated as shown in Table 7 The bq2050 calculates the gas gauge bits GG3 GG0 as a function of CACH and LMD The results of the calculation give available capacity in increments from 0 to 15 Table 7 Temperature Register bq2050 Last Measured Discharge Register LMD LMD is a read write register address 05h that the TMP3 TMP2 3 TOE MEO Temperature bq2050 uses as a measured full reference The bq2050 0 0 0 0 T lt 30 C adjusts LMD based on the measured discharge capacity 0 0 0 1 30 C lt T lt 20 C of the battery from full to empty In this way the bq2050 Fi F updates the capacity of the battery LMD is set to PFC 0 0 1 0 20 C lt T lt 10 C during a bq2050 reset 0 0 1 1 10 C lt T lt 0 C 0 1 0 0 oc lt T lt 10 C Secondary Status Flags Register FLGS2 0 1 0 1 10 C lt T lt 20 C The read only FLGS2 register address 06h contains 0 1 1 0 20 C lt T lt 30 C the secondary bq2050 flags 0 1 1 30 C lt T lt 40 C
14. PLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or services might be or are used Tl s publication of information regarding any third party s products or services does not constitute Tl s approval warranty or endorsement thereof Copyright 1999 Texas Instruments Incorporated
15. age Thresholds ta TOPR V 3 0 to 6 5V Symbol Parameter Minimum Typical Maximum Unit Notes VEDVF Final empty warning 1 44 1 47 1 50 V SB VEDV1 First empty warning 1 49 1 52 1 55 V SB Vsro SR sense range 300 2000 mV SR Vsr Vos VsRQ Valid charge 210 uV Vsr Vos see note VsRD Valid discharge 200 uV Vsr Vos see note Vucv Maximum single cell voltage 2 20 2 25 2 30 V SB Note Vos is affected by PC board layout Proper layout guidelines should be followed for optimal performance See Layout Considerations 16 DC Electrical Characteristics Ta Topr bq2050 Symbol Parameter Minimum Typical _ Maximum _ __Unit Notes Vcc Supply voltage 3 0 4 25 6 5 sg a vey beat aad Vos Offset referred to Vsr 50 150 uV DISP Vcc a Reference at 25 C 5 7 6 0 6 3 V IREF 5UA Reference at 40 C to 85 C 4 5 LO V IREF 5UA RREF Reference input impedance 2 0 5 0 MQ Vrer 3V 90 135 uA Vcc 3 0V DQ 0 Icc Normal operation 120 180 uA Voc 4 25V DQ 0 170 250 uA Vcc 6 5V DQ 0 Vsp Battery input 0 Vece V RSBmax SB input impedance 10 MQ 0 lt Vss lt Vcc Iprsp DISP input leakage 5 uA VpisP Vss ILCOM LCOM input leakage 0 2 0 2 uA DISP Vcc I RBI RBI data retention current 100 nA VRBI gt Vcc lt 3V
16. al to Vsr and if enabled activates an LED display Charge actions in crement the NAC after compensation for temperature The bq2050 determines charge activity sustained at a continuous rate equivalent to Vsro gt Vsra A valid charge equates to sustained charge activity greater than 256 NAC counts Once a valid charge is detected charge counting continues until Vsro Vsr Vos falls below Vsre Vsrq is 210uV and is described in the Digital Magnitude Filter section Discharge Counting Discharge activity is detected based on a negative voltage on the Vsr input All discharge counts where Vsro lt Vsrp cause the NAC register to decrement and the DCR to increment Vsrp is 200uV and is described in the Digital Magnitude Filter section Self Discharge Estimation The bq2050 continuously decrements NAC and increments DCR for self discharge based on time and temperature The self discharge count rate is programmed to be a nominal Xs NAC per day or disabled This is the rate for a bat tery whose temperature is between 20 30 C The NAC register cannot be decremented below 0 Count Compensations Discharge Compensation Corrections for the rate of discharge temperature and anode type are made by adjusting an internal compensation factor This factor is based on the measured rate of discharge of the battery Tables 3A and 3B outline the correction factor typi cally used for graphite anode Li Ion batteries and Tables 4A and 4B o
17. approximately 10 C See Table 5 below Table 5 Self Discharge Compensation Typical Rate Temperature Range PROGs ZorL lt 10 C NACho 4g 10 20 C NAC 94 20 30 C NAC 30 40 C NAZ e 40 50 C NAC 50 60 C NAC 60 70 C NAC gt 70 C NAC Self discharge may be disabled by connecting PROGs H Digital Magnitude Filter The bq2050 has a digital filter to eliminate charge and dis charge counting below a set threshold The bq2050 setting is 200 V for Vsrp and 210uV for Vsra bq2050 Table 6 bq2050 Current Sensing Errors Symbol Parameter Typical Maximum Units Notes INL Integrated non linearity 2 4 Add 0 1 per C above or below 25 C error z and 1 per volt above or below 4 25V INR Integrated non 1 2 Measurement repeatability given repeatability error 7 similar operating conditions Error Summary Capacity Inaccurate The LMD is susceptible to error on initialization or if no updates occur On initialization the LMD value in cludes the error between the programmed full capacity and the actual capacity This error is present until a valid discharge occurs and LMD is updated see the DCR description on page 7 The other cause of LMD er ror is battery wear out As the battery ages the meas ured capacity must be adjusted to account for changes in actual battery capacity A Capacity Inaccurate counter CPI is maintaine
18. d and incremented each time a valid charge occurs qualified by NAC see the CPI register description and is reset whenever LMD is updated from the DCR The counter does not wrap around but stops counting at 255 The ca pacity inaccurate flag CI is set if LMD has not been up dated following 64 valid charges Current Sensing Error Table 5 illustrates the current sensing error as a func tion of Vsro A digital filter eliminates charge and dis charge counts to the NAC register when Vsro is between Vsrq and Vsrp Communicating With the bq2050 The bq2050 includes a simple single pin DQ plus re turn serial data interface A host processor uses the in terface to access various bq2050 registers Battery char acteristics may be easily monitored by adding a single contact to the battery pack The open drain DQ pin on the bq2050 should be pulled up by the host system or may be left floating if the serial interface is not used The interface uses a command based protocol where the host processor sends a command byte to the bq2050 The command directs the bq2050 to either store the next eight bits of data received to a register specified by the command byte or output the eight bits of data specified by the command byte The communication protocol is asynchronous return to one Command and data bytes consist of a stream of eight bits that have a maximum transmission rate of 333 bits sec The least significant bit of a command or da
19. ed if the discharge rate is greater than 2C typical and resumes y second after the rate falls below 2C RBI Input The RBI input pin is intended to be used with a storage ca pacitor or external supply to provide backup potential to the internal bq2050 registers when Vcc drops below 3 0V Vcc is output on RBI when Vcc is above 3 0V A diode is re quired to isolate the external supply Reset The bq2050 can be reset either by removing Vcc and grounding the RBI pin for 15 seconds or by writing 0x80 to register 0x39 Temperature The bq2050 internally determines the temperature in 10 C steps centered from approximately 35 C to 85 C The temperature steps are used to adapt charge and dis charge rate compensations self discharge counting and available charge display translation The temperature range is available over the serial port in 10 C incre ments as shown in the following table TMP hex Temperature Range Ox lt 30 C 1x 30 C to 20 C 2x 20 C to 10 C 3x 10 C to 0 C 4x 0 C to 10 C 5x 10 C to 20 C 6x 20 C to 30 C 7x 30 C to 40 C 8x 40 C to 50 C 9x 50 C to 60 C Ax 60 C to 70 C Bx 70 C to 80 C Cx gt 80 C Layout Considerations The bq2050 measures the voltage differential between the SR and Vss pins Vos the offset voltage at the SR pin is greatly affected by PC board layout For optimal results the PC board layout should fo
20. gister 02h Read TMP3 TMP2 TMP1 TMPO GG3 GG2 GG1 GGO Nominal available ca NACH pacity high byte reg 03h R W NACH7 NACH6 NACH5 NACH4 NACH3 NACH2 NACH1 NACHO ister Nominal available NACL capacity low byte 17h Read NACL7 NACL6 NACL5 NACL4 NACL3 NACL2 NACL1 NACLO register Battery BATID jidentification 04h R W BATID7 BATID6 BATID5 BATID4 BATID3 BATID2 BATID1 BATIDO register LMp Last measured dis 95 RW LMD7 LMD6 LMD5 LMD4 LMD3 LMD2 LMD1 LMDO charge register FLGS2 P aaau status 06h Read nu DR2 DR1 DRO nu na nwa OVLD ags register ppp Program pin pull O7h Read n u n u PPD6 PPD5 PPD4 PPD3 PPD2 PPD1 down register PPU Ba ha pin pull up ogh Read n u n u PPU6 PPU5 PPU4 PPU3 PPU2 PPU1 Capacity CPI inaccurate count reg 09h Read CPI7 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 CPIO ister VSB ae voltage OBh Read VSB7 VSB6 VSB5 VSB4 VSB3 VSB2 VSB1 VSBO yrs _ End ofdischarge thresh OCh R W vrs7 vise vrss vrs4 VTS3 vrs2 VTS1 VTS0 old select register Compensated avail CACH lable capacity high byte ODh Read CACH7 CACH6 CACH5 CACH4 CACH3 CACH2 CACH1 CACHO register Compensated CACL available capacity low OEh Read CACL7 CACL6 CACL5 CACL4 CACL3 CACL2 CACL1 CACLO byte register Scaled available SAEH _ fenergy high byte reg
21. iew bq2050 2 Programmed Full Count PFC or initial bat Example Selecting a PFC Value tery capacity Gi iven The initial LMD and gas gauge rate values are pro grammed by using PROG1 PROG4 The bq2050 is a a configured for a given application by selecting a ahs or PT Li Ion batt k d PFC value from Table 2 The correct PFC may be apac ty An l on attery coke anode determined by multiplying the rated battery capac Current TANET 50m to 1 ity in mAh by the sense resistor value eee a mode i Battery capacity mAh sense resistor Q Self discharge NAc per day 25 C Voltage drop over sense resistor 2 5mV to 50mV PFC mVh Nominal discharge voltage 3 6V Selecting a PFC slightly less than the rated capac Therefore ity provides a conservative capacity reference until the bq2050 learns a new capacity reference 1000mAh 0 059 50mVh Table 1 bq2050 Programming Pin PROGs Compensation PROG DISP Connection Self Discharge NAC on Reset Display State H Table 4 Disabled PFC LEDs disabled Z Table 4 NA 0 LEDs on when charging L Table 3 NA 0 LEDs on for 4 sec Note PROGs and PROG states are independent Table 2 bq2050 Programmed Full Count mVh Selections Pro grammed PROG x Full PROG L PROG Z Count 1 2 PFC PROG3 H PROG3 Z PROG3 L PROG3 H PROG3 Z PROG3 L Units _ k SCALE SCALE SCALE SCALE SCALE SCALE mVh 1
22. itions of discharge bq2050 The battery s initial capacity is equal to the Pro grammed Full Count PFC shown in Table 2 Until LMD is updated NAC counts up to but not beyond this threshold during subsequent charges This approach al lows the gas gauge to be charger independent and com patible with any type of charge regime 1 Last Measured Discharge LMD or learned battery capacity LMD is the last measured discharge capacity of the battery On initialization application of Vcc or bat tery replacement LMD PFC During subsequent discharges the LMD is updated with the latest measured capacity in the Discharge Count Register DCR representing a discharge from full to below EDV1 A qualified discharge is necessary for a capac ity transfer from the DCR to the LMD register The LMD also serves as the 100 reference threshold used by the relative display mode Charge Inputs Current Rate and Temperature Compensation Discharge Current Self Discharge Timer Rate and Temperature Compensation Temperature Compensation Main Counters and Capacity Reference LMD Outputs Nominal Last Discharge Available lt Measured lt __ Count Charge Discharged Qualified Register NAC LMD Transfer DCR Temperature Step Other Data Temperature Translation v Compensated Serial Available Charge Port LED Display etc FG205002 eps Figure 2 Operational Overv
23. l responsibili ties and indemnifies Unitrode from all liability or damages Benchmarg is a registered trademark of Unitrode Corporation Printed in U S A 20 IMPORTANT NOTICE Texas Instruments and its subsidiaries Tl reserve the right to make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement including those pertaining to warranty patent infringement and limitation of liability Tl warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS INCLUSION OF TI PRODUCTS IN SUCH AP
24. ld bq2050 to host 500 us tDSU Data setup 750 us tDH Data hold 750 us tov Data valid 1 50 ms tssu Stop setup 2 25 ms tsH Stop hold 700 us tsv Stop valid 2 95 ms tB Break 3 ms tBR Break recovery 1 ms Notes The open drain DQ pin should be pulled to at least Vcc by the host system for proper DQ operation Serial Communication Timing DQ R W 1 DQ R W 0 DQ BREAK DQ may be left floating if the serial interface is not used tCYCH CYCB tB 18 TD201002 eps 16 Pin SOIC Narrow SN bq2050 EE 16 Pin SN 0 150 SOIC D to al Inches Millimeters e B q Dimension Min Max Min Max t 1 l mmn A 0 060 0 070 1 52 1 78 A1 0 004 0 010 0 10 0 25 E B 0 013 0 020 0 33 0 51 C 0 007 0 010 0 18 0 25 H D 0 385 0 400 9 78 10 16 E 0 150 0 160 3 81 4 06 A e 0 045 0 055 1 14 1 40 C AI H 0 225 0 245 5 72 6 22 i AA a 1 L 0 015 0 035 0 38 0 89 I l Le 004 L Data Sheet Revision History Change No Page NO CSCI rE OF Change e 1 4 Changed reset procedure Was Reset by issuing command over serial port Is Reset by removing Vcc and grounding RBI for 15 s 11 14 Deleted reset register 16 Changed values Vepvr Min was 1 45 Max
25. llow the strict rule of a single point ground return Sharing high current ground with small signal ground causes undesirable noise on the small signal nodes Additionally m The capacitors C1 and C2 should be placed as close as possible to the Vcc and SB pins respectively and their paths to Vss should be as short as possible A high quality ceramic capacitor of 0 luf is recommended for Vcc m The sense resistor capacitor should be placed as close as possible to the SR pin m The sense resistor Rg should be as close as possible to the bq2050 Gas Gauge Operation The operational overview diagram in Figure 2 illustrates the operation of the bq2050 The bq2050 accumulates a measure of charge and discharge currents as well as an estimation of self discharge Charge and discharge cur rents are temperature and rate compensated whereas self discharge is only temperature compensated The main counter Nominal Available Capacity NAC represents the available battery capacity at any given time Battery charging increments the NAC register while battery discharging and self discharge decrement the NAC register and increment the DCR Discharge Count Register The Discharge Count Register DCR is used to update the Last Measured Discharge LMD register only if a complete battery discharge from full to empty occurs without any partial battery charges Therefore the bq2050 adapts its capacity determination based on the actual cond
26. made by monitoring the voltage across a small value series sense resistor between the negative battery terminal and ground The estimate of scaled available energy is made using the remaining average battery voltage during the discharge cycle and the remaining nominal available charge The bq2050 scaled available energy measurement is corrected for the environmental and operating conditions Figure 1 shows a typical battery pack application of the bq2050 using the LED display capability as a charge state indicator The bq2050 is configured to display ca pacity in relative display mode The relative display mode uses the last measured discharge capacity of the battery as the battery full reference A push button display feature is available for momentarily enabling the LED display The bq2050 monitors the charge and discharge currents as a voltage across a sense resistor see Rs in Figure 1 A filter between the negative battery terminal and the SR pin may be required if the rate of change of the bat tery current is too great bq2050 Power Gauge IC REF LCOM Vcc Q1 RB vcc 1 SEG4 PROG4 SB SEGo PROG2 C2 RB2 SEG3 PROG3 SEG4 PROG4 SEG5 PROG5 PROG PSTAT Directly connect to Vcc across 1 cell VgaT gt 3V R C on SR may be required application specific in designs using 3 or more cells Otherwise R1 C1 and Q1 are
27. needed for regulation of gt 1 cell Charger e Load Programming resistors 6 max and ESD protection diodes are not shown A series Zener may be used to limit discharge current at low voltages FG205001 eps Figure 1 Battery Pack Application Diagram LED Display bq2050 Voltage Thresholds In conjunction with monitoring Vsr for charge discharge currents the bq2050 monitors the battery potential through the SB pin The voltage is determined through a resistor divider network per the following equation BBL Ni RB2 where N is the number of cells RB1 is connected to the positive battery terminal and RB2 is connected to the negative battery terminal The single cell battery volt age is monitored for the end of discharge voltage EDV EDV threshold levels are used to determine when the battery has reached an empty state Two EDV thresholds for the bq2050 are programmable with the default values fixed at EDV1 early warning 1 52V EDVF empty 1 47V If Vsp is below either of the two EDV thresholds the as sociated flag is latched and remains latched independ ent of Vsp until the next valid charge The Vsp value is also available over the serial port During discharge and charge the bq2050 monitors Vsr for various thresholds used to compensate the charge and discharge rates Refer to the count compensation section for details EDV monitoring is disabl
28. nt outputs are modulated as two banks with segments 1 3 and 5 alternating with segments 2 and 4 The segment outputs are modulated at approximately 100Hz with each segment bank active for 30 of the pe riod 15 bq2050 SEG blinks at a 4Hz rate whenever Vsp has been de tected to be below Vepvi EDV1 1 indicating a low battery condition Vsp below Vepvr EDVF 1 disables the display output Microregulator The bq2050 can operate directly from one cell A micro power source for the bq2050 can be inexpensively built using the FET and an external resistor to accommodate a greater number of cells see Figure 1 bq2050 Absolute Maximum Ratings Symbol Parameter Minimum Maximum Unit Notes Vece Relative to Vss 0 3 7 0 V All other pins Relative to Vss 0 3 7 0 V REF Relative to Vss 0 3 8 5 V Current limited by R1 see Figure 1 Minimum 100Q series resistor should be used to protect SR in case of a VsR Relative to Vss tke TO M shorted battery see the bq2050 appli cation note for details Torr Operating tempera 0 70 C Commercial hore 40 85 C Industrial Note Permanent device damage may occur if Absolute Maximum Ratings are exceeded Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet Exposure to con ditions beyond the operational limits for extended periods of time may affect device reliability DC Volt
29. quent valid charge ac tion detected or EDV1 is asserted with the temperature less than 0 C On first discharge after NAC LMD The first end of discharge warning flag EDV1 warns the user that the battery is almost empty The first segment pin SEG is modulated at a 4Hz rate if the display is enabled once EDV1 is asserted which should warn the user that loss of battery power is immi nent The EDV1 flag is latched until a valid charge has been detected The EDV1 threshold is externally con trolled via the VTS register see Voltage Threshold Reg ister on this page 1 12 The EDV1 values are FLGS1 Bits 7 6 5 4 3 2 1 0 EDV1 Where EDV1 is 0 Valid charge action detected Vsp gt Vrs 1 VssB lt Vrs providing that the discharge rate is lt 2C The final end of discharge warning flag EDVF flag is used to warn that battery power is at a failure condi tion All segment drivers are turned off The EDVF flag is latched until a valid charge has been detected The EDVF threshold is set 50mV below the EDV1 threshold The EDVF values are FLGS1 Bits 7 6 5 4 3 2 1 0 EDVF Where EDVF is 0 Valid charge action detected Vsp 2 Vrs 50mV 1 Vss lt Vrs 50mV providing the discharge rate is lt 2C Temperature Register TMP The read only TMP register address 02h contains the battery temperature TM
30. sing a five segment LED display These seg ments are used to graphically indi cate available capacity The bq2050 supports a simple single line bidi rectional serial link to an external processor common ground The bq2050 outputs battery information in response to external commands over the serial link The bq2050 may operate directly from one cell Vgar gt 3V With the REF output and an external transis tor a simple inexpensive regulator can be built for systems with more than one series cell Internal registers include available capacity temperature scaled avail able energy battery ID battery status and programming pin set tings To support subassembly test ing the outputs may also be con trolled The external processor may also overwrite some of the bq2050 power gauge data registers Pin Connections LCOM SEG PROG1 SEG2 PROG2 SEG3 PROG3 SEGa4 PROG4 SEGs PROG5 PROG6 Vss 16 Pin Narrow SOIC PN205001 eps 9 96 C Pin Names LCOM LED common output SEG PROG LED segment 1 program 1 input SEG2 PROG2 LED segment 2 program 2 input SEG3 PROG3 LED segment 3 program 3 input SEG4 PROG4 LED segment 4 program 4 input SEGs PROGs LED segment 5 program 5 input PROG6 Program 6 input REF Voltage reference output N C No connect DQ Serial communications input output RBI Register backup input SB Battery sense input DISP Display control input SR Sense resistor input
31. ta byte is transmitted first The protocol is simple enough that it can be implemented by most host proces sors using either polled or interrupt processing Data input from the bq2050 may be sampled using the pulse width capture timers available on some microcontrol lers If a communication error occurs e g tcycn gt 6ms the bq2050 should be sent a BREAK to reinitiate the serial interface A BREAK is detected when the DQ pin is driven to a logic low state for a time tg or greater The DQ pin should then be returned to its normal ready high logic state for a time tgr The bq2050 is now ready to receive a command from the host processor The return to one data bit frame consists of three dis tinct sections The first section is used to start the transmission by either the host or the bq2050 taking the DQ pin to a logic low state for a period tsTRH B The next section is the actual data transmission where the data should be valid by a period tpsu after the negative edge used to start communication The data should be held for a period tpv to allow the host or bq2050 to sample the data bit The final section is used to stop the transmission by re turning the DQ pin to a logic high state by at least a pe riod tssu after the negative edge used to start commu nication The final logic high state should be held until a period tsy to allow time to ensure that the bit trans mission was stopped properly The timings for data and
32. the operation of the bq2050 There is no de fault setting for this register 13 The overload flag OVLD is asserted when a discharge rate in excess of 2C is detected OVLD remains asserted as long as the condition persists and is cleared 0 5 sec onds after the rate drops below 2C The overload condi tion is used to stop sampling of the battery terminal char acteristics for end of discharge determination Program Pin Pull Down Register PPD The read only PPD register address 07h contains some of the programming pin information for the bq2050 The segment drivers SEG1 have a corresponding PPD regis ter location PPDi 6 A given location is set if a pull down resistor has been detected on its corresponding segment driver For example if SEG and SEG have pull down resistors the contents of PPD are xx001001 Program Pin Pull Up Register PPU The read only PPU register address 08h contains the rest of the programming pin information for the bq2050 The segment drivers SEGi 6 have a corresponding PPU regis ter location PPUj A given location is set if a pull up re sistor has been detected on its corresponding segment bq2050 driver For example if SEG3 and SEG have pull up resis tors the contents of PPU are xx100100 PPD PPU Bits 4 3 PPU PPU4 PPD PPD4 5 PPU6 PPD6 2 PPU3 PPD3 1 PPU2 PPD2 0 PPU PPD Capaci
33. ty Inaccurate Count Register CPI The read only CPI register address 09h is used to in dicate the number of times a battery has been charged without an LMD update Because the capacity of a re chargeable battery varies with age and operating condi tions the bq2050 adapts to the changing capacity over time A complete discharge from full NAC LMD to empty EDV1 1 is required to perform an LMD update assuming there have been no intervening valid charges the temperature is greater than or equal to 0 C and the self discharge counter is less than 4096 counts The CPI register is incremented every time a valid charge is detected When NAC gt 0 94 LMD however the CPI register increments on the first valid charge CPI does not increment again for a valid charge until NAC lt 0 94 LMC This prevents continuous trickle charging from incrementing CPI if self discharge decre ments NAC The CPI register increments to 255 with out rolling over When the contents of CPI are incre mented to 64 the capacity inaccurate flag CI is as serted in the FLGS1 register The CPI register is reset whenever an update of the LMD register is performed and the CI flag is also cleared Battery Voltage Register VSB The read only battery voltage register is used to read the single cell battery voltage on the SB pin The VSB regis ter address OBh is updated approximately once per sec ond with the present value of the battery voltage Vsp
34. utline the factors typically used for coke anode Li Ion batteries The compensation factor is applied to CAC and is based on discharge rate and temperature bq2050 Table 3A Graphite Anode Discharge Approximate Compensation Discharge Rate Factor Efficiency lt 0 5C 1 00 100 2 0 5C 1 05 95 Table 3B Graphite Anode Temperature Compensation Temperature Factor Efficiency 2 10 C 1 00 100 0 C to 10 C 1 10 90 10 C to 0 C 1 35 74 lt 10 C 2 50 40 Table 4A Coke Anode Discharge Approximate Compensation Discharge Rate Factor Efficiency lt 0 5C 1 00 100 2 0 5C 1 15 86 Table 4B Coke Anode Temperature Compensation Temperature Factor Efficiency gt 10 C 1 00 100 0 C to 10 C 1 25 80 10 C to 0 C 2 00 50 lt 10 C 8 00 12 Charge Compensation The bq2050 applies the following temperature compen sation to NAC during charge Temperature Compensation Temperature Factor Efficiency lt 10 C 0 95 95 2 10 C 1 00 100 This compensation applies to both types of Li Ion cells Self Discharge Compensation The self discharge compensation is programmed for a nominal rate of x NAC per day This is the rate for a battery within the 20 C 30 C temperature range This rate varies across 8 ranges from lt 10 C to gt 70 C chang ing with each higher temperature
35. was 1 49 Min now is 1 44 Max now is 1 50 Vepv1 Min was 1 50 Min now is 1 49 2 17 Changed values Voc Min was 2 5 Min now is 3 0 2 4 11 13 14 Reinserted reset register 2 9 Maximum offset Vos Max was 150 Max now is 180 Notes Change 1 June 1995 B changes from Dec 1994 19 Change 2 Sept 1996 C changes from June 1995 B bq2050 Ordering Information bq2050 Temperature Range blank Commercial 20 to 70 C N Industrial 40 to 85 C Package Option SN 16 pin narrow SOIC Device bq2040 Gas Gauge IC With SMB Interface Contact factory for availability UNITRODE 17919 Waterview Parkway Dallas Texas 75252 Fax 972 437 9198 Tel 972 437 9195 www benchmarq com or www unitrode com Copyright 1996 Unitrode Corporation All rights reserved No part of this data sheet may be reproduced in any form or means without express permission from Unitrode Unitrode reserves the right to make changes in its prod ucts without notice Unitrode assumes no responsibility for use of any products or circuitry described within No license for use of intel lectual property patents copyrights or other rights owned by Unitrode or other parties is granted or implied Unitrode does not authorize the use of its components in life support systems where failure or malfunction may cause injury to the user If Unitrode components are used in life support systems the user assumes al
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