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TEXAS INSTRUMENTS ADS1240 ADS1241 handbook

1. Load Cell MSP430x4xx ADS1240 or other uP EMI Filter NWN EMI Filter AA SA FIGURE 8 Schematic of a General Purpose Weigh Scale 2 7V 5 25V 2 7V 5 25V EMI Filter 7 IVY 4 VV EMI Filter IVY VV iE Load Cell DRDY SCLK ADS1240 Dout MSP430x4xx ADS1241 Diy or other uP cs EMI Filter Ke eg EMI Filter NV G 14 2 Rp Re FIGURE 9 Block Diagram for a High Precision Weigh Scale i ADS1240 1241 NO Texas SBAS173C www ti com 21 DEFINITION OF TERMS An attempt has been made to be consistent with the termi nology used in this data sheet In that regard the definition of each term is given as follows Analog Input Voltage the voltage at any one analog input relative to AGND Analog Input Differential Voltage given by the following equation IN IN Thus a positive digital output is produced whenever the analog input differential voltage is positive while a negative digital output is produced whenever the differential is negative For example when the converter is configured with a 2 5V reference and placed in a gain setting of 1 the positive full scale output is produced when the analog input differen tial is 2 5V The negative full scale output is produced when the differential is 2 5V In each case the actual input voltages must remain within the AGND to AVpp range
2. 7 5 ppm of FS Offset Drift 0 02 ppm of FS C Gain Error 0 005 Gain Error Drift 0 5 Common Mode Rejection at DC fom 60Hz fpara 15Hz 130 fom 50Hz fpara 15Hz 120 Normal Mode Rejection fgig 50HZ fpata 15Hz 100 Lan 60Hz fpara 15Hz 100 Output Noise Typical Characteristics Power Supply Rejection at DC dB 20 log AVoyt AVpp 95 VOLTAGE REFERENCE INPUT VREF Veer REF IN REF IN RANGE 0 Reference Input Range REF IN REF IN RANGE 1 Common Mode Rejection at DC Common Mode Rejection fvrercm 60Hz fpara 15Hz Bias Current Vper 2 5V POWER SUPPLY REQUIREMENTS Power Supply Voltage AVpp Analog Current PDWN 0 or SLEEP PGA 1 Buffer OFF PGA 128 Buffer OFF PGA 1 Buffer ON PGA 128 Buffer ON Digital Current Normal Mode DVpp 5V SLEEP Mode DVpp 5V Read Data Continuous Mode DVpp 5V PDWN Power Dissipation PGA 1 Buffer OFF DVpp 5V NOTES 1 Calibration can minimize these errors to the level of the noise 2 AVour is a change in digital result 3 12pF switched capacitor at fsamp clock frequency i ADS1240 1241 NO Texas SBAS173C www ti com ELECTRICAL CHARACTERISTICS AVpp 3V All specifications 40 C to 85 C AVpp 3V DVpp 2 7V to 5 25V fmon 19 2kHz PGA 1 Buffer ON fpata 15Hz and Vpep 1 25V unless otherwise specified PARAMETER ANALOG INPUT Aw Ajn7 Ancom Analog Input Range Full Scale Input Voltage Range
3. Conversion Cycle the term conversion cycle usually refers to a discrete A D conversion operation such as that per formed by a successive approximation converter As used here a conversion cycle refers to the tpara time period Data Rate The rate at which conversions are completed See definition for fraa fosc 128 QSPEED _ _ fosc mfactor fMop fsamp the frequency or switching speed of the input sam SAMPLING FREQUENCY 1 2 4 8 tape fosc mfactor fosc 2 f SAMP mfactor fosc 24 fosc 28 64 128 f OSC pling capacitor The value is given by one of the following equations fbara the frequency of the digital output data produced by the ADS1240 and ADS1241 fpara is also referred to as the Data Rate Full Scale Range FSR as with most A D converters the full scale range of the ADS1240 and ADS1241 is defined as the input that produces the positive full scale digital output minus the input that produces the negative full scale digital output For example when the converter is configured with a 2 5V t 8 fosc reference and is placed in a gain setting of 2 the full scale DATA 128 2SPEED 1280 2DR range is 1 25V positive full scale minus 1 25V negative full scale 2 5V SPEED 0 1 e ec DR 0 1 2 Least Significant Bit LSB Weight this is the theoretical fosc the frequency of the crystal oscillator or CMOS com patible input signal at the Xp input of the
4. Differential signals should be adjusted so that both signals are within the buffer s input range The buffer can be enabled using the BUFEN pin or the BUFEN bit in the ACR register The buffer is on when the BUFEN pin is high and the BUFEN bit is set to one If the BUFEN pin is low the buffer is disabled If the BUFEN bit is set to zero the buffer is also disabled ADS1240 1241 SBAS173C The buffer draws additional current when activated The current required by the buffer depends on the PGA setting When the PGA is set to 1 the buffer uses approximately 50uA when the PGA is set to 128 the buffer uses approxi mately 500A PGA The Programmable Gain Amplifier PGA can be set to gains of 1 2 4 8 16 32 64 or 128 Using the PGA can improve the effective resolution of the A D converter For instance with a PGA of 1 on a 5V full scale signal the A D converter can resolve down to 1uV With a PGA of 128 and a full scale signal of 39mV the A D converter can resolve down to 75nV AVpp current increases with PGA settings higher than 4 OFFSET DAC The input to the PGA can be shifted by half the full scale input range of the PGA using the Offset DAC ODAC register The ODAC register is an 8 bit value the MSB is the sign and the seven LSBs provide the magnitude of the offset Using the offset DAC does not reduce the performance of the A D converter For more details on the ODAC please refer to TI application report
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6. Input Impedance Differential Bandwidth foata 3 75Hz fpara 7 50Hz foata 15 00Hz Programmable Gain Amplifier Input Capacitance Input Leakage Current Burnout Current Sources CONDITIONS Buffer OFF Buffer ON In In See Block Diagram RANGE 0 RANGE 1 Buffer OFF Buffer ON 3dB 3dB 3dB User Selectable Gain Ranges Modulator OFF T 25 C ADS1240 ADS1241 AGND 0 1 AGND 0 05 TYP AVpp 0 1 AVpp 1 5 Vper PGA Veer 2 PGA OFFSET DAC Offset DAC Range Offset DAC Monotonicity Offset DAC Gain Error Offset DAC Gain Error Drift RANGE 0 RANGE 1 Vper 2 PGA Vper 4 PGA Bits ppm C SYSTEM PERFORMANCE Resolution Integral Nonlinearity Offset Error Offset Drift Gain Error Gain Error Drift Common Mode Rejection Normal Mode Rejection Output Noise Power Supply Rejection No Missing Codes End Point Fit at DC fom 60HZ fpara 15Hz fom 50Hz fpara 15Hz Lan 50HZ fpara 15Hz fse 60Hz fpara 15Hz at DC dB 20 log AVoyr AV pp 15 0 04 0 01 1 0 130 120 100 100 Typical Character 90 0 0015 stics Bits of FS ppm of FS ppm of FS C VOLTAGE REFERENCE INPUT VREF Reference Input Range Common Mode Rejection Common Mode Rejection Bias Current Vper REF IN REF IN RANGE 0 REF IN REF IN RANGE 1 at DC fvrercm 60Hz foara 15Hz Vper 1 25 POWER SUPPLY REQUIR
7. ADS1240 and ADS1241 fmon the frequency or speed at which the modulator of the ADS1240 and ADS1241 is running This depends on the SPEED bit as given by the following equation amount of voltage that the differential voltage at the analog input has to change in order to observe a change in the output data of one least significant bit It is computed as follows Full Scale Range LSB Weight j Se where N is the number of bits in the digital output tpata the inverse of fpara or the period between each data output 5V SUPPLY ANALOG INPUT GENERAL EQUATIONS DIFFERENTIAL PGA OFFSET FULL SCALE DIFFERENTIAL PGA SHIFT GAIN SETTING FULL SCALE RANGE INPUT VOLTAGES RANGE RANGE INPUT VOLTAGES RANGE 5V 1 2 5V 2 5V 1 25V 1 25V 0 625V PGA Zones 1 25V 0 625V 0 625V 312 5mV 312 5mV 156 25mV 156 25mV 78 125mV 78 125mV 39 0625mV 39 0625mV 19 531mV 312 5mV 156 25mV 78 125mV 39 0625mV 19 531mV 9 766mV RANGE 0 VREF 2e PGA RANGE 1 NOTES 1 With a 2 5V reference 2 Refer to electrical specification for analog input voltage range TABLE VI Full Scale Range versus PGA Setting da TEXAS 22 INSTRUMENTS www ti com ADS1240 1241 SBAS173C IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to di
8. Analog D A converter provides an offset cor rection with a range of 50 of the Full Scale Range FSR The Programmable Gain Amplifier PGA provides selectable gains of 1 to 128 with an effective resolution of 19 bits at a gain of 128 The A D conversion is accomplished with a 2nd order delta sigma modu lator and programmable Finite Impulse Response FIR filter that provides a simultaneous 50Hz and 60Hz notch The reference input is differential and can be used for ratiometric conversion The serial interface is SPI compatible Up to eight bits of data I O are also provided that can be used for input or output The ADS1240 and ADS1241 are designed for high resolution measure ment applications in smart transmitters industrial process control weigh scales chromatography and portable instrumentation AGND O Weer VREF 2nd Order Modulator Digital Filter O O O O DVpp DGND PDWN DSYNC RESET DRDY Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet PRODUCTION DATA information is current as of publication date S Products conform to specifications per the terms of Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters Copyright 2001 2003 Texas Instruments Incorporated T
9. DIR register then the corresponding DIO register bit value determines the state of the output pin O AGND 1 AVpp It is still possible to perform A D conversions on a pin configured as data I O This may be useful as a test mode where the data I O pin is driven and an A D conversion is done on the pin O WRITE AjyX DX HU To Analog Mux hhe DIO READ FIGURE 7 Analog Data Interface Pin SERIAL PERIPHERAL INTERFACE The Serial Peripheral Interface SPI allows a controller to communicate synchronously with the ADS1240 and ADS1241 The ADS1240 and ADS1241 operate in slave only mode The serial interface is a standard four wire SPI CS SCLK Diy and Dou interface that supports both serial clock polarities POL pin Chip Select CS The chip select CS input must be externally asserted before communicating with the ADS1240 or ADS1241 CS must stay LOW for the duration of the communication Whenever CS goes HIGH the serial interface is reset CS may be hard wired LOW Serial Clock SCLK The serial clock SCLK features a Schmitt triggered input and is used to clock Di and Dour data Make sure to have a clean SCLK to prevent accidental double shifting of the data If SCLK is not toggled within 3 DRDY pulses the serial interface resets on the next SCLK pulse and starts a new communication cycle A special pattern on SCLK resets the entire chip see the RESET section for additional
10. for an output data rate of 15Hz 7 5Hz or 3 75Hz Under these conditions the digital filter rejects both 50Hz and 60Hz interference Figure 6 shows the digital filter frequency response for data output rates of 15Hz 7 5Hz and 3 75Hz If a different data output rate is desired a different crystal frequency can be used However the rejection frequencies shift accordingly For example a 3 6864MHz master clock with the default register condition has 3 6864MHZz 2 4576MHZ2 15Hz 22 5Hz data output rate and the first and second notch is 1 5 e 50Hz and 60Hz 75Hz and 90Hz DATA I O INTERFACE The ADS1240 has four pins and the ADS1241 has eight pins that serve a dual purpose as both analog inputs and data I O These pins are powered from AVpp and are configured through the IOCON DIR and DIO registers These pins can be individually configured as either analog inputs or data I O See Figure 7 page 14 for the equivalent schematic of an Analog Data I O pin The IOCON register defines the pin as either an analog input or data I O The power up state is an analog input If the pin is configured as an analog input in the IOCON register the DIR and DIO registers have no effect on the state of the pin If the pin is configured as data I O in the IOCON register then DIR and DIO are used to control the state of the pin The DIR register controls the direction of the data pin either as an input or output If the pin is configured as a
11. 001 F1 1111 0010 F24 1111 0011 F3 1111 0100 F4 11111011 FB 1111 1100 FC 1111 1101 FDy 1111 1110 FE NOTE The received data format is always MSB First the data out format is set by the BIT ORDER bit in the ACR register TABLE IV Command Summary RDATA Read Data Description Read the most recent conversion result from the Data Output Register DOR This is a 24 bit value Operands None Bytes 1 Encoding 00000001 Data Transfer Sequence Dour MSB Mid Byte LSB NOTE 1 For wait time refer to timing specification An TEXAS 18 INSTRUMENTS www ti com RDATAC Read Data Continuous Description Read Data Continuous mode enables the con tinuous output of new data on each DRDY This command eliminates the need to send the Read Data Command on each DRDY This mode may be terminated by either the STOPC command or the RESET command Wait at least 10 fosc after DRDY falls before reading Operands None Bytes 1 Encoding 00000011 Data Transfer Sequence Command terminated when uuuu uuuu equals STOPC or RESET DRDY DRDY vee De MSB Mid Byte LSB NOTE 1 For wait time refer to timing specification ADS1240 1241 SBAS173C STOPC Stop Continuous Description Ends the continuous data output mode Issue after DRDY goes LOW Operands None Bytes 1 Encoding 0000 1111 Data Transfer Sequence DRDY 0000 1111 RREG Read from Registers Din XXX Desc
12. Burr Brown Products from Texas Instruments ISS ADS1240 ADS1241 SBAS173C JUNE 2001 REVISED NOVEMBER 2003 24 Bit ANALOG TO DIGITAL CONVERTER FEATURES e 24 BITS NO MISSING CODES SIMULTANEOUS 50Hz AND 60Hz REJECTION 90dB MINIMUM 0 0015 INL 21 BITS EFFECTIVE RESOLUTION PGA 1 19 BITS PGA 128 PGA GAINS FROM 1 TO 128 SINGLE CYCLE SETTLING PROGRAMMABLE DATA OUTPUT RATES EXTERNAL DIFFERENTIAL REFERENCE OF 0 1V TO 5V ON CHIP CALIBRATION SPI COMPATIBLE 2 7V TO 5 25V SUPPLY RANGE 600 W POWER CONSUMPTION UP TO EIGHT INPUT CHANNELS UP TO EIGHT DATA I O APPLICATIONS INDUSTRIAL PROCESS CONTROL WEIGH SCALES LIQUID GAS CHROMATOGRAPHY BLOOD ANALYSIS SMART TRANSMITTERS PORTABLE INSTRUMENTATION Only A All trademarks property of their respective owners O BUFEN DESCRIPTION The ADS1240 and ADS1241 are precision wide dynamic range delta sigma Analog to Digital A D converters with 24 bit resolution operating from 2 7V to 5 25V power supplies The delta sigma A D converter provides up to 24 bits of no missing code performance and effective resolution of 21 bits The input channels are multiplexed Internal buffering can be selected to provide very high input impedance for direct connection to transducers or low level voltage signals Burnout current sources are provided that allow for detection of an open or shorted sensor An 8 bit Digital to
13. Byte Read Only Reset Value 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DOR23 DOR22 DOR21 DOR20 DOR19 DOR18 DOR17 DOR16 DOR1 Address OE Data Output Register Middle Byte Read Only Reset Value 00 bit 7 bit 6 bit bit 4 bit 3 bit 2 bit 1 bit 0 DOR15 DOR14 DOR13 DOR12 DOR11 DOR10 DORO9 DOROS DORO Address OF Data Output Register Least Significant Byte Read Only Reset Value 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DORO7 DORO6 DOROS DORO4 DORO3 DORO2 DORO1 DOROO 17 SBAS173C www ti com ADS1240 AND ADS1241 CONTROL COMMAND DEFINITIONS The commands listed in Table IV control the operations of the ADS1240 and ADS1241 Some of the commands are stand alone commands e g RESET while others require additional bytes e g WREG requires the count and data bytes Operands n count 0 to 127 r register 0 to 15 x don t care RDATA Read Data RDATAC Read Data Continuously STOPG Stop Read Data Continuously RREG Read from REG mr WREG Write to REG mmm SELFCAL Offset and Gain Self Cal SELFOCAL Self Offset Cal SELFGCAL Self Gain Cal SYSOCAL Sys Offset Cal SYSGCAL Sys GainCal WAKEUP Wakup from SLEEP Mode DSYNC Sync DRDY SLEEP Put in SLEEP Mode RESET Reset to Power Up Values 0000 0001 01H 0000 0011 03 0000 1111 OF 0001 rrrr 1X4 xxxx_nnnn of regs 1 0101 rrrr 5xp xxxXX nnnn of regs 1 1111 0000 Fu 1111 0
14. E 1K Tape and Reel 1000 NOTE 1 For the most current specifications and package information refer to our web site at www ti com DIGITAL CHARACTERISTICS 40 C to 85 C DVpp 2 7V to 5 25V Digital Input Output Logic Family Logic Level Vu DVpp 0 2 e DVpp DGND 0 4 Input Leakage Ju 10 Ju Master Clock Rate fosc 5 Master Clock Period tosc i NO Teas ADS1240 1241 www ti com SBAS173C ELECTRICAL CHARACTERISTICS AVpp 5V All specifications Tun to Tmax AVpp 5V DVpp 2 7V to 5 25V fmon 19 2kHz PGA 1 Buffer ON fpata 15Hz and Vor 2 5V unless otherwise specified ADS1240 ADS1241 PARAMETER CONDITIONS TYP ANALOG INPUT A0 Ajy7 Ancom Analog Input Range Buffer OFF AGND 0 1 AVpp 0 1 Buffer ON AGND 0 05 AVpp 1 5 Full Scale Input Range In In See Block Diagram RANGE 0 Vpep PGA RANGE 1 Vper 2 PGA Differential Input Impedance Buffer OFF Buffer ON Bandwidth foata 3 75Hz 3dB foarta 7 50Hz 3dB foata 15 00Hz 3dB Programmable Gain Amplifier User Selectable Gain Ranges Input Capacitance Input Leakage Current Modulator OFF T 25 C Burnout Current Sources OFFSET DAC Offset DAC Range RANGE 0 Vper 2 PGA RANGE 1 Vper 4 PGA Offset Monotonicity Bits Offset DAC Gain Error 10 Offset DAC Gain Error Drift 1 ppm C SYSTEM PERFORMANCE Resolution No Missing Codes Bits Integral Nonlinearity End Point Fit 0 0015 of FS Offset Error
15. EMENTS Power Supply Voltage Analog Current Digital Current Power Dissipation AVpp PDWN 0 or SLEEP PGA 1 Buffer OFF PGA 128 Buffer OFF PGA 1 Buffer ON PGA 128 Buffer ON Normal Mode DVpp 3V SLEEP Mode DVpp 3V Read Data Continuous Mode DVpp 3V PDWN 0 PGA 1 Buffer OFF DVpp 3V NOTES 1 Calibration can minimize these errors to the level of the noise 2 AVour is a change in digital result 3 12pF switched capacitor at fgayp clock frequency NG TEXAS INSTRUMENTS www ti com ADS1240 1241 SBAS173C PIN CONFIGURATION ADS1240 PIN CONFIGURATION ADS1241 Top View Top View ADS1240 ADS1241 Aen AGND Ancom An3 D3 An2 D2 An7 D7 An6 D6 PIN DESCRIPTIONS ADS1240 PIN PIN NUMBER DESCRIPTION NUMBER DESCRIPTION DVpp Digital Power Supply Sr Ge GE roun DGND Digital Ground igital Grou Xin Clock Input Xin Clock Input Xour Clock Output used with external crystals Zou Clock Output used with external crystals RESET Active LOW resets the entire device RESET Active LOW resets the entire device DSYNC Active LOW Synchronization Control DSYNC Active LOW Synchronization Control PDWN Active LOW Power Down The power down func PDWN Active LOW Power Down The power down func tion shuts down the analog and digital circuits tion shuts down the analog and digital circuits DGND Digital Ground DGND Digital Ground VREFs Positive Differential R
16. EXAS INSTRUMENTS www ti com ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC Deg Ee iN DISCHARGE SENSITIVITY Input Current 100mA Momentary DGND to AGND 0 3V to 0 3V This integrated circuit can be damaged by ESD Texas Instru pa 10mA Continuous ments recommends that all integrated circuits be handled with AGND PA ha Ban appropriate precautions Failure to observe proper handling 0 3V to DVpp 0 P i Digital Output Voltage to DGND 0 3V to DVpp 0 3V and installation procedures can cause damage Seni EE ESD damage can range from subtle performance degradation Storage Temperature Range 60 C to 150 C to complete device failure Precision integrated circuits may be Lead Temperature soldering 10s more susceptible to damage because very small parametric NOTE 1 Stresses above these ratings may cause permanent damage changes could cause the device not to meet its published Exposure to absolute maximum conditions for extended periods may degrade specifications device reliability EVALUATION MODULE ORDERING INFORMATION PRODUCT DESCRIPTION ADS1241EVM ADS1240 and ADS1241 Evaluation Module PACKAGE ORDERING INFORMATION SPECIFIED PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA QUANTITY ADS1240 SSOP 24 40 C to 85 C ADS1240E ADS1240E Rails 60 j g ti ADS1240E 1K Tape and Reel 1000 ADS1241 SSOP 28 40 C to 85 C ADS1241E ADS1241E Rails 48 k R n i ADS1241
17. L1 PSELO Positive Channel Select 0000 Aw default 0001 An 0010 An2 0011 A3 0100 An4 0101 An5 0110 Auf 0111 An7 1xxx AINCOM except when xxx 111 1111 Reserved bit 3 0 NSEL3 NSEL2 NSEL1 NSELO Negative Channel Select 0000 Aw 0001 Aw default 0010 A2 0011 Ajy3 0100 Ad 0101 Ab 0110 A6 0111 A7 1xxx AINCOM except when xxx 111 1111 Reserved da TEXAS INSTRUMENTS 15 www ti com ACR Address 02 Analog Control Register Reset Value X0 bit 7 bit 6 bit 5 bit4 bit 3 bit2 bit 1 bit 0 DRDY SPEED BUFEN BIT ORDER RANGE ort oro bit 7 DRDY Data Ready Read Only This bit duplicates the state of the DRDY pin bit6 U B Data Format 0 Bipolar default 1 Unipolar DIGITAL OUTPUT Hex Ox7FFFFF 0x000000 0x800000 OxFFFFFF 0x000000 0x000000 bit 5 SPEED Modulator Clock Speed 0 fmon fosc 128 default 1 fmon fosc 256 bit 4 BUFEN Buffer Enable 0 Buffer Disabled default 1 Buffer Enabled bit 3 BIT ORDER Data Output Bit Order 0 Most Significant Bit Transmitted First default 1 Least Significant Bit Transmitted First This configuration bit controls only the bit order within the byte of data that is shifted out Data is always shifted out of the part most significant byte first Data is always shifted into the part most significant bit first bit 2 RANGE Range Select 0 Full Scale Input Range equal
18. ON Address 064 I O Configuration Register Reset Value 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fe Te e e e e e e bit 7 0 107 100 Data I O Configuration 0 Analog default 1 Data Configuring the pin as a data I O pin allows it to be controlled through the DIO and DIR registers Bit 4 to bit 7 is not used in ADS1240 OCRO Address 07 Offset Calibration Coefficient Least Significant Byte Reset Value 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ADS1240 1241 SBAS173C OCH Address 08 Offset Calibration Coefficient Middle Byte Reset Value 004 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 OCR2 Address 09 Offset Calibration Coefficient Most Significant Byte Reset Value 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 FSRO Address 0A Full Scale Register Least Significant Byte Reset Value 594 bit 7 bit 6 bit bit 4 bit 3 bit 2 bit 1 bit 0 FSRO7 FSR06 FSROS FSRO4 FSRO3 FSR02 FSR01 FSR00 FSR1 Address OD Full Scale Register Middle Byte Reset Value 55 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 FSR15 FSR14 FSR13 FSR12 FSR11 FSR10 FSR09 FSR08 A ADS1240 1241 NO Texas FSR2 Address OC Full Scale Register Most Significant Byte Reset Value 55 bit 7 bit 6 bit bit 4 bit 3 bit 2 bit 1 bit 0 FSR23 FSR22 FSR21 FSR20 FSR19 FSR18 FSR17 FSR16 DOR2 Address 0D Data Output Register Most Significant
19. SBAA077 MODULATOR The modulator is a single loop second order system The modulator runs at a clock speed fmop that is derived from the external clock fosc The frequency division is deter mined by the SPEED bit in the SETUP register as shown in Table l SPEED DR BITS 1st NOTCH fosc BIT 01 FREQ 2 4576MHz 50 60Hz 25 30Hz 100 120Hz 50 60Hz 3 75Hz 1 875Hz 4 9152MHz TABLE Output Configuration CALIBRATION The offset and gain errors can be minimized with calibration The ADS1240 and ADS1241 support both self and system calibration Self calibration of the ADS1240 and ADS1241 corrects inter nal offset and gain errors and is handled by three commands SELFCAL SELFGAL and SLEFOCAL The SELFCAL com mand performs both an offset and gain calibration SELFGCAL performs a gain calibration and SELFOCAL performs an offset calibration each of which takes two tpara periods to complete During self calibration the ADC inputs are discon nected internally from the input pins The PGA must be set to 1 prior to issuing a SELFCAL or SELFGCAL command Any PGA is allowed when issuing a SELFOCAL command For example if using PGA 64 first set PGA 1 and issue NG TEXAS INSTRUMENTS 11 www ti com SELFGCAL Afterwards set PGA 64 and issue SELFOCAL For operation with a reference voltage greater than AVpp 1 5 volts the buffer must also be turned off during gain self calibration to avoid exceeding the buffe
20. agram Note if both POL and SCLK pins are held high applying the SCLK Reset Waveform to the CS pin also resets the part ADS1240 1241 SBAS173C ADS1240 AND ADS1241 REGISTER The operation of the device is set up through individual registers Collectively the registers contain all the informa ADDRESS REGISTER BIT 7 BIT 6 ID tion needed to configure the part such as data format multiplexer settings calibration settings data rate etc The set of the 16 registers are shown in Table Ill BOCS PSEL3 NSEL3 DRDY BIT ORDER SIGN OSET3 DIO 7 DIO 3 DIR 7 DIR 3 107 103 OCR07 OCR15 OCR23 OCR03 OCR11 OCR19 FSR07 FSR15 FSR23 FSR03 FSR11 FSR19 DOR23 DOR15 DOR07 TABLE Ill Registers DETAILED REGISTER DEFINITIONS SETUP Address 00 Setup Register Reset Value iiii0000 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 palo Eso bit 7 4 Factory Programmed Bits bit 3 BOCS Burnout Current Source 0 Disabled default 1 Enabled PGA2 PGA1 PGAO Programmable Gain Amplifier Gain Selection 000 1 default bit 2 0 001 2 010 4 011 8 100 16 101 32 110 64 111 128 ADS1240 1241 SBAS173C DOR19 DOR11 DOR03 MUX Address 01 Multiplexer Control Register Reset Value 01 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PSEL3 PSEL2 PSEL1 PSELO NSEL3 NSEL2 NSEL1 NSELO bit 7 4 PSEL3 PSEL2 PSE
21. de Operands None Bytes 1 Encoding 1111 1011 Data Transfer Sequence Dy 1111 1011 An TEXAS 20 INSTRUMENTS www ti com DSYNC Sync DRDY Description Synchronizes the ADS1240 and ADS1241 to an external event Operands None Bytes 1 Encoding 11111100 Data Transfer Sequence Dy 11111100 SLEEP Sleep Mode Description Puts the ADS1240 and ADS1241 into a low power sleep mode To exit sleep mode issue the WAKEUP command Operands None Bytes 1 11111101 Data Transfer Sequence Dy 11111101 RESET Reset to Default Values Description Restore the registers to their power up values This command stops the Read Continuous mode Encoding Operands None Bytes 1 Encoding 11111110 Data Transfer Sequence Diy 1111 1110 ADS1240 1241 SBAS173C APPLICATION EXAMPLES EEN GENERAL PURPOSE WEIGH SCALE HIGH PRECISION WEIGH SCALE Figure 8 shows a typical schematic of a general purpose Figure 9 shows the typical schematic of a high precision weigh scale application using the ADS1240 In this example weigh scale application using the ADS1240 The front end the internal PGA is set to either 64 or 128 depending on the differential amplifier helps maximize the dynamic range maximum output voltage of the load cell so that the load cell output can be directly applied to the differential inputs of 2 7V 5 25V 2 7V 5 25V O O EMI Filter AA SA EMI Filter AG VW
22. e sented by the voltage difference between the pins Vpep and Meer The absolute voltage on either pin Vper or per Can range from AGND to AVpp However the follow ing limitations apply For AVpp 5 0V and RANGE 0 in the ACR the differential Vref must not exceed 2 5V For AVpp 5 0V and RANGE 1 in the ACR the differential Veer must not exceed 5V For AVpp 3 0V and RANGE 0 in the ACR the differential Voer must not exceed 1 25V For AVpp 3 0V and RANGE 1 in the ACR the differential Veer must not exceed 2 5V CLOCK GENERATOR The clock source for the ADS1240 and ADS1241 can be provided from a crystal oscillator or external clock When the clock source is a crystal external capacitors must be provided to ensure start up and stable clock frequency This is shown in both Figure 5 and Table Il Sum is only for use with external crystals and it should not be used as a clock driver for external circuitry An TEXAS 12 INSTRUMENTS www ti com Crystal FIGURE 5 Crystal Connection CLOCK PART SOURCE FREQUENCY C C NUMBER Crystal ECS ECSD 2 45 32 Crystal ECS ECSL 4 91 Crystal ECS ECSD 4 91 Crystal CTS MP 042 4M9182 TABLE Il Recommended Crystals DIGITAL FILTER The ADS1240 and ADS1241 have a 1279 tap linear phase Finite Impulse Response FIR digital filter that a user can configure for various output data rates When a 2 4576MHz crystal is used the device can be programmed
23. e a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Amplifiers amplifier ti com Audio www ti com audio Data Converters dataconverter ti com Automotive www ti com automotive DSP dsp ti com Broadband www ti com broadband Interface interface ti com Digital Control www ti com digitalcontrol Logic logic ti com Military www ti com military Power Mgmt power ti com Optical Networking www ti com opticalnetwork Microcontrollers microcontroller ti com Security www ti com security Telephony www ti com telephony Video amp
24. eference Input a VREF Negative Differential Reference Input VREF Positive Differential Reference Input An0 DO Analog Input 0 Data O 0 VREF Negative Differential Reference Input An D1 Analog Input 1 Data I O 1 Ajn0 DO Analog Input O Data I O 0 A n4 D4 Analog Input 4 Data I O 4 Ajy1 D1 Analog Input 1 Data I O 1 Ajy5 D5 Analog Input 5 Data I O 5 Aj2 D2 Analog Input 2 Data I O 2 Aiy6 D6 Analog Input 6 Data VO 6 Ajn7 D7 Analog Input 7 Data I O 7 A w2 D2 Analog Input 2 Data I O 2 Aj 3 D3 Analog Input 3 Data I O 3 AGND Analog Ground Ancom Analog Input Common connect to AGND if unused AV pp Analog Power Supply AGND Analog Ground POL Serial Clock Polarity AVpp Analog Power Supply CS Active LOW Chip Select POL Serial Clock Polarity Serial Data Input Schmitt Trigger Kag SC Ge SC Spean e erial Data Input Schmitt Trigger Serial Data Output IN l pu gg Dout Serial Data Output Serial Clock Schmitt Trigger SCLK Serial Clock Schmitt Trigger Active LOW Data Ready DRDY Active LOW Data Ready Buffer Enable BUFEN Buffer Enable Ajy3 D3 Analog Input 3 Data I O 3 Aincom Analog Input Common connect to AGND if unused i ADS1240 1241 MP Texas 5 SBAS173C www ti com DIAGRAM 1 DIAGRAM 2 TIMING DIAGRAMS Dour NOTE 1 Bit order 0 SCLK Reset Waveform ADS1240 or ADS1241 Resets On Falling Edge 300 tosc lt t12 lt 500 tosc tig gt 5 tosc 550
25. herwise specified OFFSET DAC OFFSET vs TEMPERATURE Cal at 25 C 10k Readings 209 Viy OV 170 om 140 S T 110 5 2 5 80 6 A 50 5 z 2 2 An E O 2 40 70 100 50 30 10 10 30 50 70 90 3 5 3 0 2 5 2 0 1 5 1 0 5 0 05 1 0 15 20 25 30 35 Temperature C ppm of FS OFFSET DAC GAIN vs TEMPERATURE OFFSET DAC Cal at 25 C NOISE vs SETTING 1 00020 0 8 1 00016 ag 1 00012 1 00008 2 0 6 N 1 00004 is 05 1 00000 S 3 0 99996 J us S 0 99992 P 0 3 0 99988 S o2 0 99984 f 0 99980 0 1 0 99976 0 50 30 6 10 10 30 90 128 96 64 32 0 32 64 96 128 Temperature C Offset DAC Setting i ADS1240 1241 X9 Texas INSTRUMENTS SBAS173C www ti com OVERVIEW INPUT MULTIPLEXER The input multiplexer provides for any combination of differ ential inputs to be selected on any of the input channels as shown in Figure 1 For example if A0 is selected as the positive differential input channel any other channel can be selected as the negative terminal for the differential input An0 DO A D1 Burnout Current Source An2 D2 An3 D3 And D4 Anb D5 An6 D6 AfD ADS1241 Ancom Only New Conversion Begins Complete Previous Conversion channel With this method it is possible to have up to eight single ended input channels or four independent differential in
26. ied EFFECTIVE NUMBER OF BITS vs PGA SETTING EFFECTIVE NUMBER OF BITS vs PGA SETTING 21 5 21 0 20 5 20 0 19 5 19 0 ENOB rms 18 5 18 0 Buffer OFF 17 5 17 0 1 2 4 8 16 32 64 128 1 2 4 8 16 32 64 128 PGA Setting PGA Setting EFFECTIVE NUMBER OF BITS vs PGA SETTING NOISE vs INPUT SIGNAL 20 5 20 0 19 5 19 0 18 5 18 0 ENOB rms 17 5 Noise rms ppm of FS 17 0 Buffer OF 16 5 16 0 1 2 4 8 16 32 64 128 PGA Setting COMMON MODE REJECTION RATIO POWER SUPPLY REJECTION RATIO vs FREQUENCY vs FREQUENCY 140 140 120 120 100 100 80 60 CMRR dB PSRR dB 40 40 20 20 Buffer ON Buffer ON 1 10 100 1k 10k 100k 1 10 100 1k 10k 100k Frequency of Power Supply Hz Frequency of Power Supply Hz i ADS1240 1241 NO Texas SBAS173C www ti com TYPICAL CHARACTERISTICS Cont All specifications AVpp 5V DVpp 5V fosc 2 4576MHz PGA 1 fpara 15Hz and Vper REF IN REF IN 2 5V unle
27. information Clock Polarity POL The clock polarity input POL controls the polarity of SCLK When POL is LOW data is clocked on the falling edge of SCLK and SCLK should be idled LOW Likewise when POL is HIGH the data is clocked on the rising edge of SCLK and SCLK should be idled HIGH Data Input Dn and Data Output Dou The data input Dj and data output Dour receive and send data from the ADS1240 and ADS1241 Dour is high imped ance when not in use to allow Di and Dour to be connected together and driven by a bidirectional bus Note the Read NG TEXAS 14 INSTRUMENTS www ti com Data Continuous Mode RDATAC command should not be issued when Di and Dour are connected While in RDATAC mode Din looks for the STOPC or RESET command If either of these 8 bit bytes appear on Dour which is con nected to Di the RDATAC mode ends DATA READY DRDY PIN The DRDY line is used as a status signal to indicate when data is ready to be read from the internal data register DRDY goes LOW when a new data word is available in the DOR register It is reset HIGH when a read operation from the data register is complete It also goes HIGH prior to the updating of the output register to indicate when not to read from the device to ensure that a data read is not attempted while the register is being updated The status of DRDY can also be obtained by interrogating bit 7 of the ACR register address 2 The serial interface can ope
28. n input in the DIR register then the corresponding DIO register bit reflects the state of the pin Make sure the pin is driven to a ADS1240 1241 SBAS173C ADS1240 AND ADS1241 FILTER RESPONSE WHEN fpara 15Hz 20 40 60 80 100 120 140 160 180 200 Frequency Hz ADS1240 AND ADS1241 FILTER RESPONSE WHEN Loan 7 5Hz 20 40 60 80 100 120 140 160 180 200 Frequency Hz ADS1240 AND ADS1241 FILTER RESPONSE WHEN fparp 3 75Hz 40 60 80 100 120 140 160 180 200 Frequency Hz Magnitude dB Magnitude dB Magnitude dB FREQUENCY RESPONSE FROM 45Hz to 65Hz WHEN fpara 15Hz 55 Frequency Hz FREQUENCY RESPONSE FROM 45Hz to 65Hz WHEN fpara 7 5Hz 55 Frequency Hz FREQUENCY RESPONSE FROM 45Hz to 65Hz WHEN fpata 3 75Hz Frequency Hz fosc 2 4576MHz SPEED 0 or fosc 4 9152MHz SPEED 1 DATA 3dB ATTENUATION OUTPUT RATE BANDWIDTH fin 50 0 3Hz fin 60 0 3Hz fin 50 1Hz fin 60 1Hz FIGURE 6 Filter Frequency Responses ADS1240 1241 SBAS173C da TEXAS INSTRUMENTS 13 www ti com logic one or zero when configured as an input to prevent excess current dissipation If the pin is configured as an output in the
29. n the negative input acts as a pull down causing the negative input to go to ground The ADS1240 41 therefore outputs full scale 7FFFFF Hex Previous Conversion Data New Conversion Complete SETTLING ERROR vs DELAY TIME 10 000000 1 000000 fox 2 4576MHZ 0 100000 0 010000 0 001000 Settling Error 0 000100 0 000010 0 000001 8 10 Delay Time t55 ay ms FIGURE 2 Input Multiplexer Configuration An TEXAS 10 INSTRUMENTS www ti com ADS1240 1241 SBAS173C CODE 0x7FFFFF FIGURE 3 Burnout detection while sensor is open circuited Figure 4 shows a short circuited sensor Since the inputs are shorted and at the same potential the ADS1240 41 signal outputs are approximately zero Note that the code for shorted inputs is not exactly zero due to internal series resistance low level noise and other error sources SHORT y CIRCUIT FIGURE 4 Burnout detection while sensor is short circuited INPUT BUFFER The input impedance of the ADS1240 41 without the buffer enabled is approximately 5MQ PGA For systems requiring very high input impedance the ADS1240 41 provides a chopper stabilized differential FET input voltage buffer When activated the buffer raises the ADS1240 41 input impedance to approximately 5GQ The buffer s input range is approximately 50mV to AVpp 1 5V The buffer s linearity will degrade beyond this range
30. put channels for the ADS1241 and four single ended input channels or two independent differential input channels for the ADS1240 Note that Ancom can be treated as an input channel The ADS1240 and ADS1241 feature a single cycle settling digital filter that provides valid data on the first conversion after a new channel selection In order to minimize the settling error synchronize MUX changes to the conversion beginning which is indicated by the falling edge of DRDY In other words issuing a MUX change through the WREG command immediately after DRDY goes LOW minimizes the settling error Increasing the time between the conversion beginning DRDY goes LOW and the MUX change com mand oc ay results in a settling error in the conversion data as shown in Figure 2 BURNOUT CURRENT SOURCES The Burnout Current Sources can be used to detect sensor short circuit or open circuit conditions Setting the Burnout Current Sources BOCS bit in the SETUP register activates two 2uA current sources called burnout current sources One of the current sources is connected to the converter s nega tive input and the other is connected to the converter s positive input Figure 3 shows the situation for an open circuit sensor This is a potential failure mode for many kinds of remotely con nected sensors The current source on the positive input acts as a pull up causing the positive input to go to the positive analog supply and the current source o
31. r input range System calibration corrects both internal and external offset and gain errors While performing system calibration the appropriate signal must be applied to the inputs The system offset calibration command SYSOCAL requires a zero input differential signal see Table IV page 18 It then computes the offset that nullifies the offset in the system The system gain calibration command SYSGCAL requires a positive full scale input signal It then computes a value to nullify the gain error in the system Each of these calibrations takes two tpata periods to complete System gain calibration is recom mended for the best gain calibration at higher PGAs Calibration should be performed after power on a change in temperature or a change of the PGA The RANGE bit ACR bit 2 must be zero during calibration Calibration removes the effects of the ODAC therefore dis able the ODAC during calibration and enable again after calibration is complete At the completion of calibration the DRDY signal goes low indicating the calibration is finished The first data after calibration should be discarded since it may be corrupt from calibration data remaining in the filter The second data is always valid EXTERNAL VOLTAGE REFERENCE The ADS1240 and ADS1241 require an external voltage reference The selection for the voltage reference value is made through the ACR register The external voltage reference is differential and is repr
32. rate in 3 wire mode by tying the CS input LOW In this case the SCLK Dy and Dour lines are used to communi cate with the ADS1240 and ADS1241 This scheme is suitable for interfacing to microcontrollers If CS is required as a decoding signal it can be generated from a port bit of the microcontroller DSYNC OPERATION Synchronization can be achieved either through the DSYNC pin or the DSYNC command When the DSYNC pin is used the digital circuitry is reset on the falling edge of DSYNC While DSYNC is LOW the serial interface is deactivated Reset is released when DSYNC is taken HIGH Synchroni zation occurs on the next rising edge of the system clock after DSYNC is taken HIGH When the DSYNC command is sent the digital filter is reset on the edge of the last SCLK of the DSYNC command The modulator is held in RESET until the next edge of SCLK is detected Synchronization occurs on the next rising edge of the system clock after the first SCLK following the DSYNC command POWER UP SUPPLY VOLTAGE RAMP RATE The power on reset circuitry was designed to accommodate digital supply ramp rates as slow as 1V 10ms To ensure proper operation the power supply should ramp monotoni cally RESET The user can reset the registers to their default values in three different ways by asserting the RESET pin by issuing the RESET command or by applying a special waveform on the SCLK the SCLK Reset Waveform as shown in the Timing Di
33. ription Output the data from up to 16 registers starting with the register address specified as part of the instruction The number of registers read will be one plus the second byte count If the count exceeds the remaining registers the ad dresses wrap back to the beginning Operands rn Bytes 2 Encoding 0001 rrrr xxxx nnnn Data Transfer Sequence Read Two Registers Starting from Register 01 MUX Dour MUX ACR NOTE 1 For wait time refer to timing specification WREG Write to Registers Description Write to the registers starting with the register address specified as part of the instruction The number of registers that will be written is one plus the value of the second byte Operands rn Bytes 2 Encoding 0101 rrrr xxxx nnnn Data Transfer Sequence Write Two Registers Starting from 04 DIO Din 0101 0100 X xxxx 0001 A Data for DIO A Data for DIR ADS1240 1241 SBAS173C SELFCAL Offset and Gain Self Calibration Description Starts the process of self calibration The Offset Calibration Register OCR and the Full Scale Register FSR are updated with new values after this operation Operands None Bytes 1 Encoding 11110000 Data Transfer Sequence Dy C 1111 0000 SELFOCAL Offset Self Calibration Description Starts the process of self calibration for offset The Offset Calibration Register OCR is updated after this operation Operands None Bytes 1 Encoding 11110001 Da
34. scontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using TI components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards Tl does not warrant or represent that any license either express or implied is granted under any Tl patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may requir
35. ss otherwise specified OFFSET vs TEMPERATURE GAIN vs TEMPERATURE Cal at 25 C Cal at 25 C 50 1 00010 0 1 00006 o 8 1 00002 50 T E 5 0 99998 PGA64 E 5 100 ZS 0 99994 9 PGA128 ote 0 99990 200 0 99986 50 30 10 10 30 50 70 90 50 30 10 10 30 50 70 90 Temperature C Temperature C INTEGRAL NONLINEARITY vs INPUT SIGNAL ANALOG CURRENT vs TEMPERATURE 10 150 8 140 40 C 6 SC 130 zx 4 ig 12 P 85 C 1 TITAN SE 5 2 Na a a 3 110 Pd 5 0 er 5 100 ca 2 3 Ge NA Z o SCH 4 i Tac 80 25 C 6 70 8 60 50 2 5 2 0 15 10 05 0 05 10 15 20 25 50 30 10 10 30 50 70 90 Vin V Temperature C ANALOG CURRENT vs PGA DIGITAL CURRENT vs SUPPLY AVpp 5V Buffer ON Buffer OFF Normal Normal 4 91MHz lied AV pp 3V Buffer ON Ianto HA Joers HA Buffer SLEEP 2 45MHz 1 2 4 8 16 32 64 128 PGA Setting An TEXAS 8 INSTRUMENTS ADS1 240 1 241 www ti com SBAS173C TYPICAL CHARACTERISTICS Cont All specifications AV pp 5V DVpp 5V fosc 2 4576MHz PGA 1 foara 15Hz NOISE HISTOGRAM and Vpez REF IN REF IN 2 5V unless ot
36. ta Transfer Sequence D n 1111 0001 SELFGCAL Gain Self Calibration Description Starts the process of self calibration for gain The Full Scale Register FSR is updated with new values after this operation Operands None Bytes 1 Encoding 11110010 Data Transfer Sequence Dw C 1111 0010 da TEXAS INSTRUMENTS 19 www ti com SYSOCAL System Offset Calibration Description Initiates a system offset calibration The input should be set to OV and the ADS1240 and ADS1241 compute the OCR value that compensates for offset errors The Offset Calibration Register OCR is updated after this operation The user must apply a zero input signal to the appropriate analog inputs The OCR register is automatically updated afterwards Operands None Bytes 1 Encoding 11110011 Data Transfer Sequence Di C 1111 0011 SYSGCAL System Gain Calibration Description Starts the system gain calibration process For a system gain calibration the input should be set to the reference voltage and the ADS1240 and ADS1241 compute the FSR value that will compensate for gain errors The FSR is updated after this operation To initiate a system gain calibration the user must apply a full scale input signal to the appropriate analog inputs FCR register is updated automati cally Operands None Bytes 1 Encoding 11110100 Data Transfer Sequence Diy C 11114 0100 WAKEUP Description Wakes the ADS1240 and ADS1241 from SLEEP mo
37. to Vpep default 1 Full Scale Input Range equal to 1 2 Voer NOTE This allows reference voltages as high as AVpp but even with a 5V reference voltage the calibration must be performed with this bit set to 0 bit 1 0 DR1 DRO Data Rate fosc 2 4576MHz SPEED 0 00 15Hz default 01 7 5Hz 10 3 75Hz 11 Reserved NG TEXAS 16 INSTRUMENTS www ti com ODAC Address 03 Offset DAC Reset Value 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 Sign 0 Positive 1 Negative Offset PE SEF 21 RANGE 0 2ePGA 127 Offset ER SEA RANGE 1 4ePGA 127 NOTE The offset DAC must be enabled after calibration or the calibration nullifies the effects DIO Address 04 Data UO Reset Value 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wor oon ven oor ors 07 oor Teer If the IOCON register is configured for data a value written to this register appears on the data UO pins if the pin is configured as an output in the DIR register Reading this register returns the value of the data I O pins Bit 4 to bit 7 is not used in ADS1240 DIR Address 05 Direction Control for Data I O Reset Value FF bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DIR7 ore DIR5 DIR4 DIR3 DIR2 DIR1 oro Each bit controls whether the corresponding data UO pin is an output 0 or input 1 The default power up state is as inputs Bit 4 to bit 7 is not used in ADS1240 IOC
38. tosc lt t44 lt 750 tosc 1050 tosc lt t s lt 1250 tosc RESET DSYNC PDWN L TIMING CHARACTERISTICS TABLES SCLK Period SCLK Pulse Width HIGH and LOW CS low to first SCLK Edge Setup Time Din Valid to SCLK Edge Setup Time Valid Diy to SCLK Edge Hold Time Delay between last SCLK edge for Di and first SCLK edge for Dour RDATA RDATAC RREG WREG SCLK Edge to Valid New Dour SCLK Edge to Dour Hold Time Last SCLK Edge to Dour Tri State NOTE Dour goes tri state immediately when CS goes HIGH CS LOW time after final SCLK edge Final SCLK edge of one command until first edge SCLK of next command RREG WREG DSYNC SLEEP RDATA RDATAC STOPC SELFGCAL SELFOCAL SYSOCAL SYSGCAL SELFCAL RESET also SCLK Reset or RESET Pin Pulse Width Allowed analog input change for next valid conversion DOR update DOR data not valid First SCLK after DRDY goes LOW RDATAC Mode Any other mode NOTES 1 Load 20pF 10kQ to DGND 2 CS may be tied LOW KG TEXAS INSTRUMENTS www ti com tosc Periods DRDY Periods ns ns ns ns tosc Periods ns ns tosc Periods ns tosc Periods DRDY Periods DRDY Periods tosc Periods tosc Periods tosc Periods tosc Periods tosc Periods tosc Periods ADS1240 1241 SBAS173C TYPICAL CHARACTERISTICS All specifications AVpp 5V DVpp 5V fosc 2 4576MHz PGA 1 fpara 15Hz and Vper REF IN REF IN 2 5V unless otherwise specif

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