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FAIRCHILD 74LCX11 Low Voltage Triple 3-Input AND Gate with 5V Tolerant Inputs datasheet

1. 2 00 amp BOTTOM R0 09 mi SEATING PLANE 0 09mln 14 Lead Thin Shrink Small Outline Package TSSOP JEDEC MO 153 4 4mm Wide Package Number MTC14 Fairchild does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and c whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be rea sonably expected to result in a significant injury to the user 11 2 A critical component in any component of a life support device or system whose failure to perform can be rea sonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness www fairchildsemi com www fairchildsemi com sinduj AG YUM d eDeyoA MOT
2. or LOW to HIGH Dynamic Switching Characteristics Symbol Parameter Quiet Output Dynamic Peak VoL Quiet Output Dynamic Peak VoL Capacitance V Ta 25 C Conditions idi Units V Typical 50 pF Vi 3 3V Vi OV 3 3 0 8 C 30 pF Vin 2 5V ViL 0V 2 5 0 6 C 50 Vin 3 3V Vit 0V 3 3 0 8 V 30 pF Vin 2 5V Vi 0V 2 5 0 6 Output Capacitance Voc 3 3V OV or Input Capacitance Voc Open V OV or Vec Power Dissipation Capacitance Voc 3 3V V OV or Voc f 10 MHz pF www fairchildsemi com pF pF Loading and Waveforms Generic for LCX Family puz 7 FIGURE 1 AC Test Circuit C includes probe and jig capacitance tpi z Voc x2at Voc 2 5 0 2V 6V at Voc 3 3 0 3V DATA IN GND F v OUT mo Waveform for Inverting and Non Inverting Functions I ty CONTROL IN CLOCK OUTPUT Propagation Delay Pulse Width and t ec Waveforms OUTPUT Vcc CONTROL mi aun euz v Y OUT mo 3 STATE Output High Enable and Disable Tlmes for Logic OUTPUT m Yee CONTROL mi tp DATA 3 STATE Output Low Enable and Disable Times for Logic 90 90 10 trise and lan FIGURE 2 Waveforms Input Pulse Characteristics f 1MHz t t 3ns CO NENNEN 3 3V 0 3V 1 5V VoL 0 3V V
3. MO 241 2 5 x 3 0mm 74LCX11MTC MTC14 14 Lead Thin Shrink Small Outline Package TSSOP JEDEC MO 153 4 4mm Wide 74LCX11MTCX_NL Pb Free 14 Lead Thin Shrink Small Outline Package TSSOP JEDEC MO 153 4 4mm Note 1 Wide Pb Free package per JEDEC J STD 020B Note 1 NL indicates Pb Free package per J STD 020B Device available in Tape and Reel only Note 2 DQFN package available in Tape and Reel only 2005 Fairchild Semiconductor Corporation DS012426 www fairchildsemi com 74LCX11 Connection Diagrams Logic Symbol Pin Assignments for SOIC SOP and TSSOP IEEE IEC 1 0 C 0 GND 0 C Top View Pad Assignments for DQFN 0 Co Logic Diagram B Y C Pin Descriptions Pin Names Description Top Through View Inputs Outputs www fairchildsemi com 2 Absolute Maximum 3 Symbs Unis Voo Supay CdS Vo DC Output Voltage 0 5 to Vcc 0 5 Output in HIGH or LOW State Note 4 V 50 lik DC Input Diode Current a 798 Vi lt GND mA lok DC Output Diode Current 50 Vo lt GND 50 Vo gt Voc E E Recommended Operating Conditions Note 5 Vcc Supply Voltage Operating V Data Retention Output Current Voc 3 0V 3 6V Voc 2 7V 3 0V mA Voc 2 3V 2 7V Free Air Operating Temperature C Note 3 The Absolute Maximum Ratings are those values beyond which the safety of the devi
4. Measured at Hub gt 4 DETAIL See detail AA Tape Size 9 E 0 059 0 512 0 795 2 165 0 488 330 0 1 50 13 00 20 20 55 00 12 4 7 www fairchildsemi com LEXO IvZ 74LCX11 Physical Dimensions inches millimeters unless otherwise noted 0 150 0 157 3 810 3 988 0 010 0 020 0 254 0 508 ALL LEADS 0 102 ALL LEAD TIPS 0 008 0 010 0 203 0 254 0 016 0 050 0 004 8 MAX TYP ALL LEADS 0 406 1 270 TYP ALL LEADS SEATING Y PLANE 1 0 335 0 344 8 509 8 738 0 228 0 244 5 791 6 198 LEAD NO 1 A IDENT 0 053 0 069 1 346 1 753 0 004 0 010 a ee ee ae AE ILE BEEN 0 014 0 020 TYP 1 270 0 356 0 508 TYP 0 008 i 0 203 0356 1 090 M14A REV Hi 14 Lead Small Outline Integrated Circuit SOIC JEDEC MS 012 0 150 Narrow www fairchildsemi com Package Number M14A Physical Dimensions inches millimeters unless otherwise noted Continued 10 2 0 1 1 1 a PIN 1 IDENT ALL LEAD TIPS 1 8 0 1 al 0 15 0 05 0 35 0 51 DIMENSIONS ARE IN MILLIMETERS NOTES A CONFORMS TO EIAJ EDR 7320 REGISTRATION ESTABLISHED IN DECEMBER 1998 B DIMENSIONS ARE IN MILLIMETERS DIMENSIONS ARE EXCLUSIVE OF BURRS MOLD FLASH AND TIE BAR EXTRUSIONS M14DRevB1
5. 0 60 0 15 10 00 14 13 9 8 5 01 TYP 9 27 TYP Ei xs SOO t LAND PATTERN RECOMMENDATION SEE DETAIL xem dct 4 N 0 8 TYP 0 25 SEATING PLANE 1 25 m DETAIL A 14 Lead Small Outline Package SOP EIAJ TYPE Il 5 3mm Wide Package Number M14D www fairchildsemi com LLXO 102 74LCX11 Physical Dimensions inches millimeters unless otherwise noted Continued 3 00 B 2 50 2X Cs 10 15 ELLA am L dE 0 18 0 30 0 100 CAB 200 BOTTOM VIEW NOTES A CONFORMS TO JEDEC REGISTRATION MO 241 VARIATION B DIMENSIONS ARE IN MILLIMETERS C DIMENSIONS AND TOLERANCES PER ASME Y14 5M 1994 MLPO14ArevA Pb Free 14 Terminal Depopulated Quad Very Thin Flat Pack No Leads DQFN JEDEC MO 241 2 5 x 3 0mm Package Number MLP014A www fairchildsemi com 10 Physical Dimensions inches millimeters unless otherwise noted Continued pas CEU 0 43 ALL LEAD TIPS PIN 1 IDENT udi yore 9818 sp i 0 10 0 05 0 65 019 0 30 4 0 1385 85 05 NOTES CONFORMS TO JEDEC REGISTRATION MO 153 VARIATION AE REF NOTE 6 DATED 7 93 B DIMENSIONS ARE IN MILLIMETERS C DIMENSIONS ARE EXCLUSIVE OF BURRS MOLD FLASH AND TIE BAR EXTRUSIONS D DIMENSIONING AND TOLERANCES PER ANSI 14 5 1982 MT C14revD 0 09 0 20
6. U D Acx April 1995 FAIRCHILD Revised July 2005 SEMICONDUCTOR 74LCX11 Low Voltage Triple 3 Input AND Gate with 5V Tolerant Inputs General Description Features The LCX11 is a triple 3 input AND gate with buffered out E 5V tolerant inputs and outputs puts LCX devices are designed for low voltage 2 5V or 2 3 3 6V Vcc specifications provided 3 3V operation with the added capability of interfacing to a 5V signal environment The 74LCX11 is fabricated with advanced CMOS technol Power down high impedance inputs and outputs ogy to achieve high speed operation while maintaining 24 mA output drive Vec 3 0V CMOS low power dissipation E implements patented noise EMI reduction circuitry E Latch up performance exceeds JEDEC 78 conditions ESD performance Human body model gt 2000V Machine model gt 200V eadless DQFN Package E 6 0ns tpp max Vec 3 3V 10 uA lcc max Ordering Code Package Order Number Package Description Number 74LCX11M M14A 14 Lead Small Outline Integrated Circuit SOIC JEDEC MS 012 0 150 Narrow 74LCX11MX_NL M14A Pb Free 14 Lead Small Outline Integrated Circuit SOIC JEDEC MS 012 0 150 Narrow Note 1 74LCX11SJ M14D 14 Lead Small Outline Package SOP EIAJ TYPE II 5 8mm Wide S ndu AG YUM INdu d eDeyoA MOT 74LCX11BQX MLPO014A Pb Free 14 Terminal Depopulated Quad Very Thin Flat Pack No Leads DQFN JEDEC Note 2
7. ce cannot be guaranteed The device should not be operated at these limits The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings The Recom mended Operating Conditions table will define the conditions for actual device operation Note 4 lj Absolute Maximum Rating must be observed Note 5 Unused inputs must be held HIGH or LOW They may not float DC Electrical Characteristics 40 C to 85 C Symbol Parameter Conditions Units m Vin HIGH Level Input Voltage 23 27 ViL LOW Level Input Voltage PEE Vou HIGH Level Output Voltage EM T p HEU ae posee VoL LOW Level Output Voltage lo 100 uA 99 3 em _ ae 35 87 i loc Quiescent Supply Current Vi Vec or GND 3 6V lt V lt 5 5V www fairchildsemi com LEXO IvZ 74LCX11 AC Electrical Characteristics lPLH losiH Ta 40 C to 85 C 500 Vec 3 3V 0 3V Vcc 2 7V 2 5V 0 2V Symbol Parameter 6 ce Units C 50 pF C 50 pF C 30pF Propagation Delay 1 5 6 0 1 5 7 0 1 5 7 2 ns tPHL 1 5 6 0 1 5 7 0 1 5 7 2 Output to Output Skew 1 0 ns tosHL Note 6 1 0 Note 6 Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device The specification applies to any outputs switching in the same direction either HIGH to LOW
8. x Vy VoL 0 3V VoL 0 15V 0 3V 0 3V 0 15V www fairchildsemi com LLXO 102 74LCX11 Schematic Diagram Generic for LCX Family input stage www fairchildsemi com Tape and Reel Specification Tape Format for DQFN Package Tape Number Cavity Cover Tape Designator Section Cavities Status Status Leader Start End 125 typ Empty Sealed Carrier 3000 Filled Sealed Trailer Hub End 75 typ Empty Sealed TAPE DIMENSIONS inches millimeters 2 00 0 05 1 55 0 05 2 N 7 4 1 55 0 05 0 30 0 05 SECTION B B Wa Sia s PKG SIZE DIM Bo SECTION 0 1 2530 28204 25X25 28 0 1 28201 092 0 1 DIMENSIONS ARE IN MILLIMETERS NOTES unless otherwise specified 1 Cummulative pitch for feeding holes and cavities chip pockets not to exceed 0 008 0 20 over 10 pitch span 2 Smallest allowable bending radius 3 Thru hole inside cavity is centered within cavity 4 Tolerance is 0 002 0 05 for these dimensions on all 12mm tapes 5 Ao and Bo measured on a plane 0 120 0 30 above the bottom of the pocket 6 Ko measured from a plane on the inside bottom of the pocket to the top surface of the carrier 7 Pocket position relative to sprocket hole measured as true position of pocket Not pocket hole 8 Controlling dimension is millimeter Diemension in inches rounded REEL DIMENSIONS inches millimeters W1 Measured at Hub W2 max

FAIRCHILD 74LCX11 Low Voltage Triple 3-Input AND Gate with 5V Tolerant Inputs datasheet

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