ST 74LCX07 LOW VOLTAGE CMOS HEX BUFFER (OPEN DRAIN) WITH 5V TOLERANT INPUTS handbook
Contents
1. Note Drawing not in scale 74LCX07 Tape amp Reel TSSOP14 MECHANICAL DATA inch DIM MIN TYP MAX A 12 992 C 0 504 0 519 D 0 795 N 2 362 T 0 882 Ao 0 264 0 272 Bo 0 209 0 217 Ko 0 063 0 071 Po 0 153 0 161 P 0 311 0 319 Y N Y A Note Drawing not in scale 74LCX07 Table 10 Revision History Date Revision Description of Changes 15 Sep 2004 4 Ordering Codes Revision pag 1 10 11 74LCX07 Information furnished is believed to be accurate and reliable However STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics The ST logo is a re2. or LOW to HIGH The remaining output is measured in the LOW state ky 3 11 74LCX07 Table 8 AC Electrical Characteristics Test Condition Value Symbol Parameter Vec CL Re t t 40 to 85 C 55 to 125 C Unit v PF 2 ns Min Max Min Max tpLz Propagation Delay 2 7 7 0 7 0 2 Time con dl ad a se 10 52 sig tpzL Propagation Delay 2 7 7 0 7 0 2 Time RT or se 10 52 tos n Output To Output 3 0 to 3 6 50 500 2 5 1 0 1 0 ns tosHL Time note1 1 Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch ing in the same direction either HIGH or LOW tosLH tPLHm 7 trLHnl tosHL tPHLm u trHLnl 2 Parameter guaranteed by design Table 9 Capacitive Characteristics Test Condition Value Symbol Parameter Vec Ta 25 C Unit V Min Typ Max Cin Input Capacitance 3 3 Vin 0 to Voc 6 pF Cour Output Capacitance 3 3 Vin 0 to Voc 14 pF Cpp Power Dissipation Capacitance 3 3 fin 10MHz 4 3 note 1 Vin 0 or Vec pl 1 Cpp is defined as the value of the IC s internal equivalent capacitance which is calculated from the operating current consumption without load Refer to Test Circuit Average operating current can be obtained by the following equation lcc opr Cpp X Vc X fin
3. 11 74LCX07 Figure 2 Input And Output Equivalent Circuit Table 2 Pin Description SC14780 Table 3 Truth Table Table 4 Absolute Maximum Ratings PIN N SYMBOL NAME AND FUNCTION A Y 1 3 5 9 11 1Ato6A Data Inputs k 13 H Z 2 4 i 19 1Yto6Y Data Outputs Z High Impedance 7 GND Ground 0V 14 Voc Positive Supply Voltage Symbol Parameter Value Unit Voc Supply Voltage 0 5 to 7 0 V VI DC Input Voltage 0 5 to 7 0 V Vo DC Output Voltage Vcc OV 0 5 to 7 0 V Vo DC Output Voltage High or Low State note 1 0 5 to Vcc 0 5 Vv lik DC Input Diode Current 50 mA lox DC Output Diode Current note 2 50 mA lo DC Output Current 50 mA loc DC Supply Current per Supply Pin 100 mA IGND DC Ground Current per Supply Pin 100 mA Tstg Storage Temperature 65 to 150 C TL Lead Temperature 10 sec 300 C Absolute Maximum Ratings are those values beyond which damage to the device may occur Functional operation under these conditions is not implied 1 2 Vo lt GND 2 11 absolute maximum rating must be observed 4 Table 5 Recommended Operating Conditions 74LCX07 Symbol Parameter Value Unit Voc Supply Voltage note 1 2 0 to
4. 3 6 V VI Input Voltage 0 to 5 5 V Vo Output Voltage Vcc OV 0 to 5 5 V Vo Output Voltage High or Low State 0 to Vec V lo lo High or Low Level Output Current Vcc 3 0 to 3 6V 24 mA lon lo High or Low Level Output Current Vcc 2 7V 12 mA Top Operating Temperature 55 to 125 C dt dv Input Rise and Fall Time note 2 0 to 10 ns V 1 Truth Table guaranteed 1 5V to 3 6V 2 Vin from 0 8V to 2V at Voc 3 0V Table 6 DC Specifications Test Condition Value Symbol Parameter Vec 40 t0 85 C 55 to 125 C Unit v Min Max Min Max Vin High Level Input 20 20 yv Vol f 5 E em 2 7 to 3 6 IL ed 0 8 0 8 V Voltage VoL Low Level Output 2 7 to 3 6 lo 100 uA 0 2 0 2 Voltage 2 7 lo 12 mA 0 4 0 4 e l9 16 mA 0 4 0 4 3 0 lo 24 mA 0 55 0 55 O ei 2 7t03 6 V 0to5 5V 5 5 pA urrent loff Power Off Leakage Es Current 0 Vior Vo 5 5V 10 10 HA loz High Impedance Vis Vig or Vic Output Leakage 2 7 to 3 6 Va 0toV 5 5 HA Current o cc loc Quiescent Supply Vi Vcc or GND 10 10 2 7 to 3 6 A Current 2 V or Vo 3 6 to 5 5V 10 io Alec Icc incr per Input 2 7t03 6 Vin Vcc 0 6V 500 500 uA Table 7 Dynamic Switching Characteristics Test Condition Value T 25 C i Symbol Parameter Vec A Unit v Min Typ Max Voip Dynamic Low Level Quiet 33 Vi OV 0 8 y Voiv Output note 1 i Vin 3 3V 0 8 1 Number of outputs defined as n Measured with n 1 outputs switching from HIGH to LOW
5. Icc 6 per gate Figure 3 Test Circuit SC08900 TEST SWITCH PLH PHL Open tpzL tPLz 6V tez tPHZz GND C 50 pF or equivalent includes jig and probe capacitance Ri R1 5002 or equivalent Rt Zour of pulse generator typically 50Q 4 4 11 74LCX07 Figure 4 Waveform Propagation Delay f 1MHz 50 duty cycle 5C 14670 SZA 5 11 74LCX07 SO 14 MECHANICAL DATA 0 25 mm GAGE PLANE L 0016019D lt 6 11 74LCX07 TSSOP14 MECHANICAL DATA mm inch DIM MIN TYP MAX TYP MAX A 1 2 0 047 Al 0 05 0 15 0 006 A2 0 8 1 1 05 0 041 b 0 19 0 30 0 012 c 0 09 0 20 0 0089 D 4 9 5 5 1 0 201 E 6 2 6 4 6 6 0 260 E1 4 3 4 4 4 48 0 176 e 0 65 BSC 0 0256 BSC K 0 8 8 L 0 45 0 60 0 75 0 030 E1 PIN 1 IDENTIFICATION 0080337D 7 11 74LCX07 Tape amp Reel SO 14 MECHANICAL DATA 8 11 inch DIM MIN TYP MAX A 12 992 C 0 504 0 519 D 0 795 N 2 362 T 0 882 Ao 0 252 0 260 Bo 0 354 0 362 Ko 0 082 0 090 Po 0 153 0 161 P 0 311 0 319 Y N Y A
6. O O 74LCX07MTRI O O SZA 74LCX07 LOW VOLTAGE CMOS HEX BUFFER OPEN DRAIN WITH 5V TOLERANT INPUTS 5V TOLERANT INPUTS HIGH SPEED tpp 5 2ns MAX at Voc 3V POWER DOWN PROTECTION ON INPUTS AND OUTPUTS m SYMMETRICAL OUTPUT IMPEDANCE lloul lot 24mA MIN at Voc 3V m PCI BUS LEVELS GUARANTEED AT 24 mA OPERATING VOLTAGE RANGE Vcc OPR 2 0V to 3 6V 1 5V Data Retention m PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 07 m LATCH UP PERFORMANCE EXCEEDS 500mA JESD 17 m ESD PERFORMANCE HBM gt 2000V MIL STD 883 method 3015 MM gt 200V DESCRIPTION The 74LCX07 is a low voltage CMOS OPEN DRAIN HEX BUFFER fabricated with sub micron silicon gate and double layer metal wiring C MOS technology It is ideal for low power and high speed 3 3V applications lt can be interfaced to 5V signal environment for inputs Figure 1 Pin Connection And IEC Logic Symbols PC10970 September 2004 Table 1 Order Codes PACKAGE T amp R 7ALCKOTMITR TSSOP 74LCX07TTR The internal circuit is composed of 2 stages including buffer output which provides high noise immunity and stable output It has same speed performance at 3 3V than 5V AC ACT family combined with a lower power consumption All inputs and outputs are equipped with protection circuits against static discharge giving them 2KV ESD immunity and transient excess voltage CS04190 Rev 4 1
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