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FAIRCHILD 74LCX00 Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs handbook

1. lou 8 mA 2 3 18 lon 12 mA 27 2 2 V lou 18 mA 3 0 24 lou 24 mA 3 0 2 2 VoL LOW Level Output Voltage lo 100 uA 2 3 3 6 0 2 lol 8mA 23 0 6 lg 12 mA 27 0 4 V lg 16 mA 3 0 0 4 lo 24 mA 3 0 0 55 li Input Leakage Current 0 lt lt 5 5 2 3 3 6 15 0 uA lorr Power Off Leakage Current Vi or Vo 5 5V 0 10 uA loc Quiescent Supply Current Vi Vcc or GND 2 3 3 6 10 uA 3 6V lt lt 5 5V 2 3 3 6 10 Increase per Input Vin Voc 0 6V 2 3 3 6 500 uA www fairchildsemi com 74LCX00 AC Electrical Characteristics TA 40 C to 85 CF R 5000 Voc 3 3V 0 3V Voc 2 7V Voc 2 5V 0 2V Symbol Parameter Units C 50pF C 50pF C 30pF Min Max Min Max Min Max tPHL Propagation Delay 1 5 5 2 1 5 6 0 1 5 6 2 ns tpLH 15 5 2 15 6 0 15 6 2 tosuL Output to Output Skew Note 6 1 0 ns losiH 1 0 Note 6 Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device The specification applies to any outputs switching in the same direction either HIGH to LOW tos or LOW to HIGH tos u Dynamic Switching Characteristics Vec Ta 25 C Symbol Parameter Conditions Unit V Typical Voip Quiet Output Dynamic Peak VoL C 50 pF 3 3V Vi OV 3 3 0 8 C 30 pF Vj 2 5V Vi 0V 25
2. 0 6 Voiv Quiet Output Dynamic Valley Vo C 50 pF 3 3V OV 3 3 0 8 V C 30 pF 2 5V Vi 0V 25 0 6 Capacitance Symbol Parameter Conditions Typical Units Cin Input Capacitance Voc Open V OV or Vec 7 pF Output Capacitance Voc 3 3V V OV or Voc 8 pF Cpp Power Dissipation Capacitance Voc 3 3V OV or Voc f 10 MHz 25 pF www fairchildsemi com AC LOADING and WAVEFORMS 1 1 Family FIGURE 1 AC Test Circuit C includes probe and jig capacitance Test Switch ipi pe PHL Open testers 6V at Voc 3 3 0 3V Voc x2at Voc 2 5 0 2V tpzutpyz GND DATA Waveform for Inverting and Non Inverting Functions CONTROL Yoo IN GND tree CLOCK Veni leur OUTPUT Propagation Delay Pulse Width and tec Waveforms OUTPUT Y CONTROL mi 2 X VoL 3 STATE Output Low Enable and Disable Times for Logic OUTPUT CONTROL mi ND teuz V DATA V wh OUT mo Y 3 STATE Output High Enable and Disable Times for Logic DATA IN i CONTROL INPUT t MR rec OR Vmi CLEAR Setup Time Hold Time and Recovery Time for Logic Vou 90 90 10 10 VoL trise and tray FIGURE 2 Waveforms Input Characteristics f 1MHZz t t 3ns Symbol 3 3V 0 3V
3. 2 7V 2 5V 0 2V Vii 1 5V 1 5V Vino 1 5V 1 5V Veg2 Vy Vo 0 3V VoL 0 3V VoL 0 15V Vy Von 0 3V Von 0 3V Von 0 15V www fairchildsemi com 00XO TPZ 74LCX00 Schematic Diagram Generic for LCX Family input stage www fairchildsemi com Tape and Reel Specification Tape Format for DQFN 00XO TPZ Package Tape Number Cavity Cover Tape Designator Section Cavities Status Status Leader Start End 125 typ Empty Sealed BQX Carrier 3000 Filled Sealed Trailer Hub End 75 typ Empty Sealed TAPE DIMENSIONS inches millimeters 40 041 B 2002005 i 91 55 0 05 1 75 0 01 A A ao at t WD ES ON i 2 5 50 0 10 Q 2 1200 030 i5 1 __ Ab 8 4 75 010 yey sl 155 0 05 0 30 0 05 SECTION B B zi i S PKG SIZE DIM Ao DIM Bo DIM Ko SECTION NOTES unless otherwise specified 1 Cummulative pitch for feeding holes and cavities chip pockets not to exceed 0 008 0 20 over 10 pitch span 2 Smallest allowable bending radius 3 Thru hole inside cavity is centered within cavity 4 Tolerance is 0 002 0 05 for these dimensions on all 12mm tapes 5 Ao and Bo measured on a plane 0 120 0 30 above the bottom of the pocket 6 Ko measured from a plane on the
4. inside bottom of the pocket to the top surface of the carrier 7 Pocket position relative to sprocket hole measured as true position of pocket Not pocket hole 8 Controlling dimension is millimeter Diemension in inches rounded REEL DIMENSIONS inches millimeters W1 Measured at Hub W2 max Measured atHub gt A B Min 4 1 T m Dia C sre de Dia A Dia D n i Dia N min i Fi l max K A v Y _ See detail AA DETAEAR Y Tape Size A B C D N w1 w2 Tam 13 0 0 059 0 512 0 795 2 165 0 488 0 724 330 0 1 50 13 00 20 20 55 00 12 4 18 4 7 www fairchildsemi com 74LCX00 ALL LEAD TIPS Package Number M14A 0 228 0 244 5 791 6 198 LEAD NO 1 A IDENT 9 150 0 157 3 610 3 988 lt 0 010 0 020 0 053 0 069 0 254 0 508 9 1 346 1 753j 8 MAX TYP ALL LEADS M M AR ig at i PLANE 5 0 008 0 010 004 0 203 0 254 0 016 0 050 0 356 1 270 TYP ALL LEADS 0 0 406 1 270 TYP 0 102 TYP ALL LEADS Physical Dimensions inches millimeters unless otherwise noted 0 335 0 344 8 509 8 738 0 010 max 0 254 0 004 0 010 0 102 0 254 0 014 0 020 0 356 0 508 0 008 la 0203 7 M14 REV hi 14 Lead Small Outline Integrated Circuit SOIC JEDEC MS 012 0 150 Narrow www fairchilds
5. N MO 241 VARIATION AA B DIMENSIONS ARE IN MILLIMETERS C DIMENSIONS AND TOLERANCES PER ASME Y14 5M 1994 MLPO14ArevA Pb Free 14 Terminal Depopulated Quad Very Thin Flat Pack No Leads DQFN JEDEC MO 241 2 5 x 3 0mm Package Number MLP014A www fairchildsemi com 10 Physical Dimensions inches millimeters unless otherwise noted Continued E B ALL LEAD TIPS PIN 1 te Max posteis en i 1 L 0 10 0 05 0 65 019 0 30 130 85 05 NOTES A CONFORMS TO JEDEC REGISTRATION MO 153 VARIATION AB REF NOTE 6 DATED 7 93 DIMENSIONS ARE IN MILLIMETERS DIMENSIONS ARE EXCLUSIVE OF BURRS MOLD FLASH AND TIE BAR EXTRUSIONS D DIMENSIONING AND TOLERANCES PER ANSI 14 5 1982 MTC14rcevD 7728 omn 4 16 i 0 42 65 4 j LAND PATTERN RECOMMENDATION DETAIL A gp n puse 2 00 TOP amp BOTTOM LANE 14 Lead Thin Shrink Small Outline Package TSSOP JEDEC MO 153 4 4mm Wide Package Number MTC14 Fairchild does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and Fairchild r
6. O 153 4 4mm Wide 74LCXOOMTCX_NL MTC14 14 Lead Thin Shrink Small Outline Package TSSOP JEDEC MO 153 4 4mm Note 2 Wide Devices also available in Tape and Reel Specify by appending the suffix letter X to the ordering code Pb Free package per JEDEC J STD 020B Note 1 DQFN package available in Tape and Reel only Note 2 _NL package available in Tape and Reel only sindu 1ue49J0 AG 9185 GNVWN 1nduj z 00XO Tt 2005 Fairchild Semiconductor Corporation DS012408 www fairchildsemi com 74LCX00 Logic Symbol Connection Diagrams IEEE IEC Pin Assignments for SOIC SOP and TSSOP Ao a o 85 A 5 5 Bi Ao 8 By 92 o GND E Pad Assignments for DQFN Pin Descriptions 19 19 m 2 i3 A2 Pin Names Description Sols Gale An Bn Inputs 1 1152 On Outputs 1 5 510 GBs 7 s Top View www fairchildsemi com 2 Absolute Maximum 3 Symbol Parameter Value Conditions Units Voc Supply Voltage 0 5 to 7 0 V Vi DC Input Voltage 0 5 to 47 0 V Vo DC Output Voltage 0 5to Vcc 0 5 Output in HIGH or LOW State Note 4 V lik DC Input Diode Current 50 Vi GND mA lox DC Output Diode Current 50 Vo lt GND A 50 Vo lo DC Output S
7. O O 74LCX0OMX NLO March 1995 ur st FAIRCHILD Revised January 2005 ae SEMICONDUCTOR 1M 74LCX00 Low Voltage Quad 2 Input NAND Gate with 5V Tolerant Inputs General Description Features The LCX00 contains four 2 input NAND gates The inputs E 5V tolerant inputs tolerate voltages up to 7V allowing the interface of 5V sys 2 3V 3 6V Voc specifications provided tems to 3V systems The 74LCX00 is fabricated with advanced CMOS technol ogy to achieve high speed operation while maintaining Power down high impedance inputs and outputs CMOS low power dissipation E 24 mA output drive Voc 3 0V W implements patented noise EMI reduction circuitry W Latch up performance exceeds JEDEC 78 conditions W ESD performance Human body model 2000V Machine model 200V E Leadless Pb Free DQFN package E 5 2 ns tpp max Vec 3 3V 10 uA loc max Ordering Code Package ee Order Number Package Description Number 74LCX00M M14A 14 Lead Small Outline Integrated Circuit SOIC JEDEC MS 012 0 150 Narrow 74LCX00MX NL M14A Pb Free 14 Lead Small Outline Integrated Circuit SOIC JEDEC MS 012 0 150 Narrow Note 2 74LCX00SJ M14D Pb Free 14 Lead Small Outline Package SOP EIAJ TYPE Il 5 3mm Wide 74LCX00BQX MLP014A Pb Free 14 Terminal Depopulated Quad Very Thin Flat Pack No Leads DQFN JEDEC Note 1 MO 241 2 5 x 3 0mm 74LCXOOMTC MTC14 14 Lead Thin Shrink Small Outline Package TSSOP JEDEC M
8. emi com 8 Physical Dimensions inches millimeters unless otherwise noted Continued 10 2 0 1 1 1 A mm 14 13 9 8 1 5 01 TYP 5 30 1 9 27 TYP l pee A 2 1 7 ALL LEAD TIPS PIN 1 IDENT 127 TYP 0 6 TYP LAND PATTERN RECOMMENDATION ALL LEAD TIPS D SEE DETAIL A 8 0 ze E E 4 0 15 0 25 DIMENSIONS ARE IN MILLIMETERS GAGE PLANE NOTES 0 8 0 25 A CONFORMS EIAJ EDR 7320 REGISTRATION ESTABLISHED IN DECEMBER 1998 uz B DIMENSIONS ARE IN MILLIMETERS i C DIMENSIONS ARE EXCLUSIVE OF BURRS MOLD FLASH AND TIE BAR EXTRUSIONS 0 60 0 15 SEATING PLANE M14DRevB1 DETAIL Pb Free 14 Lead Small Outline Package SOP EIAJ TYPE Il 5 3mm Wide Package Number M14D 9 www fairchildsemi com 00XO TPZ 74LCX00 Physical Dimensions inches millimeters unless otherwise noted Continued 4 00 MAX 2 20 MAX 1 40 MAX 4 _ 2 50 2x 0 15 S 2x os e TOP VIEW 0 80 MAX o to c 1 LLooOooa ust aloe po i 0 00 SEATING SIDE VIEW PLANE BOTTOM VIEW NOTES A CONFORMS TO JEDEC REGISTRATIO
9. eserves the right at any time without notice to change said circuitry and specifications LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and c whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be rea sonably expected to result in a significant injury to the user 2 A critical component in any component of a life support device or system whose failure to perform can be rea sonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness www fairchildsemi com www fairchildsemi com sindu 1ue49J0 AG GNVWN 1nduj z 00XO Tt
10. ource Sink Current 50 loc DC Supply Current per Supply Pin 100 mA laND DC Ground Current per Ground Pin 100 mA TsrG Storage Temperature 65 to 150 C Recommended Operating Conditions note 5 Symbol Parameter Min Max Units Voc Supply Voltage Operating 2 0 3 6 Data Retention 1 5 3 6 Vi Input Voltage 0 5 5 V Vo Output Voltage HIGH or LOW State 0 Voc V lolo Output Current 3 0V 3 6V 24 Vec 2 7V 3 0V 12 mA Voc 2 3V 2 7V 8 Free Air Operating Temperature 40 85 AVAV Input Edge Rate Viy 0 8V 2 0V Vcc 3 0V 0 10 ns V Note 3 The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings The Recom mended Operating Conditions table will define the conditions for actual device operation Note 4 lo Absolute Maximum Rating must be observed Note 5 Unused inputs must be held HIGH or LOW They may not float DC Electrical Characteristics 00XO TPZ Vcc 40 C to 85 C Symbol Parameter Conditions Units V Min Max Vin HIGH Level Input Voltage 23 27 14 v 27 36 2 0 Vit LOW Level Input Voltage 2 3 2 7 0 7 2 7 3 6 0 8 Vou HIGH Level Output Voltage 7100 pA 2 3 3 6 Voc 0 2

FAIRCHILD 74LCX00 Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs handbook

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