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PHILIPS 74HC/HCT107 Dual JK flip-flop with reset; negative-edge trigger handbook

1. SYMBOL PARAMETER TYPICAL CONDITIONS propagation delay nCP to nQ nCP to nQ teut teLy nR to nQ nQ maximum clock frequency C 15 pF Vec 5V input capacitance power dissipation notes 1 capacitance per flip flop and 2 Notes 1 Cpp is used to determine the dynamic power dissipation Pp in uW Pp Cpp x Vec x fi CL x Voc x fo where fi input frequency in MHz fo output frequency in MHz CL x Vec x fo sum of outputs C output load capacitance in pF Voc supply voltage in V For HC the condition is V GND to Vec For HCT the condition is Vi GND to Vcc 1 5 V ORDERING INFORMATION See 74HC HCT HCU HCMOS Logic Package Information December 1990 Philips Semiconductors Product specification Dual JK flip flop with reset negative edge trigger 74HC HCT 107 PIN DESCRIPTION PIN NO SYMBOL NAME AND FUNCTION 1 8 4 11 1J 2J 1K 2K synchronous inputs flip flops 1 and 2 1Q 2Q complement flip flop outputs 1Q 2Q true flip flop outputs GND ground 0 V 1CP 2CP clock input HIGH to LOW edge triggered 1R 2R asynchronous reset inputs active LOW Voc positive supply voltage a 7293220 3 7293193 Fig 1 Pin configuration Fig 2 Logic symbol Fig 3 IEC logic symbol December 1990 3 Philips Semiconductors Product specification Dual JK flip flop with reset negative edge trigger 74HC HCT 107 7Z93190
2. 1 7293195 Fig 4 Functional diagram Fig 5 Logic diagram one flip flop FUNCTION TABLE INPUTS OUTPUTS OPERATING MODE asynchronous reset L X X X L H toggle H l h h q q load 0 reset H L h L H load 1 set H L h H L hold no change H l l q q Note 1 H HIGH voltage level h HIGH voltage level one set up time prior to the HIGH to LOW CP transition L LOW voltage level LOW voltage level one set up time prior to the HIGH to LOW CP transition q lower case letters indicate the state of the referenced output one set up time prior to the HIGH to LOW CP transition X don t care J HIGH to LOW CP transition December 1990 4 Philips Semiconductors Product specification Dual JK flip flop with reset negative edge trigger 74HC HCT107 DC CHARACTERISTICS FOR 74HC For the DC characteristics see 74HC HCT HCU HCMOS Logic Family Specifications Output capability standard Icc category flip flops AC CHARACTERISTICS FOR 74HC GND 0 V tr tp 6 ns CL 50 pF Tamb C TEST CONDITIONS 74HC PARAMETER WAVEFORMS 40 to 85 40 to 125 propagation delay tpHL teLH nCP to nQ ropagation dela propagation delay PHL teH AR to nQ nQ tru_ trL output transition time clock pulse width HIGH or LOW reset pulse width LOW removal time nR to nCP set up time __ nJ nK to nCP hold time nJ nK to nCP maximum c
3. FORMS nJ nK INPUT aE INPUT nQ OUTPUT The shaded areas indicate when the input is permitted to change for predictable output performance 1 HC Vp 50 V GND to Vcc HCT Vy 1 3 V V GND to 3 V n OUTPUT 7293191 Fig 6 Waveforms showing the clock nCP to output nQ nQ propagation delays the clock pulse width the J and K to nCP set up and hold times the output transition times and the maximum clock pulse frequency nGP INPUT Vy nR INPUT nQ OUTPUT n OUTPUT 1 HC Vp 50 Vi GND to Vec 7222175 HCT Vy 1 3 V Vi GND to 3 V Fig 7 Waveforms showing the reset nR input to output nQ nQ propagation delays the reset pulse width and the nR to nCP removal time PACKAGE OUTLINES See 74HC HCT HCU HCMOS Logic Package Outlines December 1990 7
4. O Q 744C107 0 INTEGRATED CIRCUITS DATA SHEET For a complete data sheet please also download e The IC06 74HC HCT HCU HCMOS Logic Family Specifications e The IC06 74HC HCT HCU HCMOS Logic Package Information e The IC06 74HC HCT HCU HCMOS Logic Package Outlines 74HC HCT107 Dual JK flip flop with reset negative edge trigger Product specification December 1990 File under Integrated Circuits IC06 Philips PHILIP S Semiconductors DpH l LI Philips Semiconductors Product specification Dual JK flip flop with reset negative edge trigger 74HC HCT107 FEATURES e Output capability standard e Icc category flip flops GENERAL DESCRIPTION The 74HC HCT107 are high speed Si gate CMOS devices and are pin compatible with low power Schottky TTL LSTTL They are specified in compliance with JEDEC standard no 7A QUICK REFERENCE DATA GND 0 V Tamb 25 C t t 6 ns The 74HC HCT107 are dual negative edge triggered JK type flip flops featuring individual J K clock nCP and reset nR inputs also complementary Q and Q outputs The J and K inputs must be stable one set up time prior to the HIGH to LOW clock transition for predictable operation The reset nR is an asynchronous active LOW input When LOW it overrides the clock and data inputs forcing the Q output LOW and the Q output HIGH Schmitt trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times
5. lock pulse frequency December 1990 5 Philips Semiconductors Product specification Dual JK flip flop with reset negative edge trigger 74HC HCT107 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see 74HC HCT HCU HCMOS Logic Family Specifications Output capability standard Icc category flip flops Note to HCT types The value of additional quiescent supply current Alcc for a unit load of 1 is given in the family specifications To determine Alcc per input multiply this value by the unit load coefficient shown in the table below INPUT UNIT LOAD COEFFICIENT nk 0 60 nR 0 65 nCP nJ 1 00 AC CHARACTERISTICS FOR 74HCT GND 0 V tt tf 6 ns C 50 pF Tamb C TEST CONDITIONS 74HCT SYMBOL PARAMETER UNIT voc 25 40 to 85 40 to 125 V WAVEFORMS min typ max min max min max propagation delay tpHL PLH nCP to nQ propagation delay nCP to nQ a a propagation delay tehL tPLH AR to nQ nG tTHL trL output transition time 19 36 45 54 ns 4 5 Fig 6 tpHL tPLH clock pulse width HIGH or LOW reset pulse width LOW removal time nR to nCP set up time _ nJ nK to nCP hold time nJ nK to nCP maximum clock pulse frequency December 1990 6 Philips Semiconductors Product specification Dual JK flip flop with reset negative edge trigger 74HC HCT107 AC WAVE

PHILIPS 74HC/HCT107 Dual JK flip-flop with reset; negative-edge trigger handbook

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