74HC/HCT32 SSI handbook
Contents
1. nB INPUT nY OUTPUT 7290991 Fig 7 Waveforms showing the input nA nB to output nY propagation delays and the output Note to AC waveforms transition times 1 HC Vp 50 Vi GND to Vee HCT VM 1 3 V V GNDto3V 172 January 1986 is Material Copyrighted By Philips Semiconductors RE Printed F KAD li WWW dZSC2. AD JA WWW dZSC e6 74HC HCT32 SSI FUNCTION TABLE INPUTS OUTPUT m e w HIGH voltage level LOW voltage level 7Z87420 1 Fig 4 Functional diagram 7z90990 7Z93123 Fig 5 Logic diagram 74HC Fig 6 Logic diagram 74HCT one gate one gate DC CHARACTERISTICS FOR 74HC For the DC characteristics see chapter HCMOS family characteristics section Family specificati Output capability standard icc category SSI AC CHARACTERISTICS FOR 74HC GND 0 V tr tf 6 ns CL 50 pF output transition time Propagation delay nA nB tony 170 March 1988 is Material Copyrighted By Philips Semiconductors Printed F DBA 1g i tE E D WWW dZSC 6c Quad 2 input OR gate 74HC HCT32 SSI DC CHARACTERISTICS FOR 74HCT For the DC characteristics see chapter HCMOS family characteristics section Family specifications Output capability standard icc category 55 Note to HCT types The value of additional quiescent supply current Alce for a unit load of 1 is given in the family specifications To determine Alcc per input multiply this value by the unit load coefficient shown in the table below UNIT LOAD COEFFICIENT AC CHARACTERISTICS FOR 74HCT TEST CONDITIONS WAVEFORMS January 1986 171 is Material Copyrighted By Philips Semiconductors Printed F KAD li WWW dZSC 74HC HCT32 SSi AC WAVEFORMS nA
3. OO 4AHCIPNG OO 74HC HCT32 SSI QUAD 2 INPUT OR GATE FEATURES Output capability standard Icc category SSI SYMBOL PARAMETER CONDITIONS he tpHL propagation delay C 15 pF tPLH nA nB to nY Vec 5V Cs ee compliance with JEDEC standard no 7A or power dissipation notes 1 and 2 capacitance per gate The 74HC HCT32 provide the Notes 2 input OR function GND 0 V Tamb 25 C tr tf 6 ns 1 Cpp is used to determine the dynamic power dissipation Pp in uW Pp Cpp x Vcc x fi CL x Vcc x fo where fi input frequency in MHz CL output load capacitance in pF fo output frequency in MHz Vcc supply voltage in V E Cy x Vec x fy sum of outputs 2 ForHC the condition is Vj GND to Vcc For HCT the condition is Vj GND to Vcc 1 5 V GENERAL DESCRIPTION The 74HC HCT32 are high speed Si gate CMOS devices and are pin compatible with low power Schottky TTL LSTTL They are specified in PACKAGE OUTLINES 14 lead DIL plastic SOT27 14 jead mini pack plastic S014 SOT108A PIN DESCRIPTION SYMBOL NAME AND FUNCTION 1 4 9 12 1A to 4A data inputs 2 5 10 13 1B to 4B data inputs 3 6 8 11 1Y to 4Y data outputs 7 GND ground 0 V 14 Vec positive supply voltage 7Z37419 1 7Z287420 1 7236989 1 Fig 1 Pin configuration Fig 2 Logic symbol Fig 3 IEC logic symbol December 1990 169 is Material Copyrighted By Philips Semiconductors Printed F K
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74HC/HCT32 SSI handbook