TEXAS INSTRUMENTS D74AC245 CD74ACT245 Octal-Bus Transceiver Three-State Non-Inverting handbook
Contents
1. 50 Note 6 7 Low Level Output Voltage Vin or a ea eee 6 7 Ree 6 7 i Input Leakage Current Vcc or GND Three State or Leakage Vin Or VIL Current Vo Vcc or GND Quiescent Supply Current Icc Vcc or MSI GND Additional Supply Current per Alce Voc 4 5 to Input Pin TTL Inputs High 2 1 5 5 1 Unit Load NOTES 6 Test one output at a time for a 1 second maximum duration Measurement is made by forcing current and measuring voltage to minimize power dissipation oO Ba gt A P w to K EN colo T gt t oO ale are ol gt I oO c gt gt N P N 0 4 7 Test verifies a minimum 50Q transmission line drive capability at 85 C 75Q at 125 C CD74AC245 CD74ACT245 ACT Input Load Table 4s ae as ef NOTE Unit load is Alcg limit specified in DC Electrical Specifications Table e g 2 4mA max at 25 C Switching Specifications Input ty t 3ns CL 50pF Worst AC TYPES Data to Output 3 3 3 2 10 8 3 11 9 ns Note 9 5 2 2 7 7 2 1 8 5 ns Note 10 Output Disable to Output fo ele ee a ee ae Output Enable to Output Minimum Valley Voy During 4 at 4 at Switching of Other Outputs See Figure 1 25 C 25 C Output Under Test Not Switching Maximum Peak Vo During 1 at 1 at Switching of Other Outputs See Figure 1 25 C 25 C Output Under Test Not Switching He en ee ee eee eas input Capacitance e a ea ee eee ae Power Dissipation Capaci2. 0 CD74AC245 0 0 a TEXAS INSTRUMENTS Data sheet acquired from Harris Semiconductor SCHS245 CD 74AC245 CD 4ACT245 Octal Bus Transceiver September 1998 Three State Non Inverting Features Buffered Inputs Typical Propagation Delay 4ns at Voc 5V Ta 25 C C 50pF Exceeds 2kV ESD Protection MIL STD 883 Method 3015 SCR Latchup Resistant CMOS Process and Circuit Design Speed of Bipolar FAST AS S with Significantly Reduced Power Consumption Balanced Propagation Delays AC Types Feature 1 5V to 5 5V Operation and Balanced Noise Immunity at 30 of the Supply 24mA Output Drive Current Fanout to 15 FAST ICs Drives 50Q Transmission Lines Description The CD74AC245 and CD74ACT245 are octal bus transceiv ers that utilize the Harris Advanced CMOS Logic technology They are non inverting three state bidirectional transceiver buffers intended for two way transmission from A bus to B bus or B bus to A The logic level present on the direction input DIR determines the data direction When the output enable input OE is HIGH the outputs are in the high impedance state Ordering Information NUMBER RANGE C PACKAGE NOTES 1 When ordering use the entire part number Add the suffix 96 to obtain the variant in the tape and reel 2 Wafer and die for this part number is available which meets all elec trical specifications Please contact your local sales office or Harris c
3. LED OUTPUT LOW TO OFF TO LOW tr 3ns INPUT LEVEL Vs OUTPUT HIGH TO OFF TO HIGH OUTPUTS ENABLED OTHER INPUTS DUT WITH TIED HIGH THREE OR LOW STATE TPUT OUTPUT OUTPU DISABLE NOTE 14 For AC Series only When Vcc 1 5V RL 1kQ _0 2V EC VoL 4 Vee 8 Voc Vg OUTPUTS lq OUTPUTS DISABLED ENABLED o GND tpyz tpzH o OPEN tpu tPLH RLO 2 Vcc tpLz tpzL 5009 OPEN DRAIN FIGURE 2 THREE STATE PROPAGATION DELAY TIMES AND TEST CIRCUIT FIGURE 3 PROPAGATION DELAY TIMES OUTPUT YR NOTE OUTPUT LOAD NOTE For AC Series Only When Vcc 1 5V Ry 1kQ od FIGURE 4 PROPAGATION DELAY TIMES IMPORTANT NOTICE Texas Instruments and its subsidiaries Tl reserve the right to make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement including those pertaining to warranty patent infringement and limitation of liability Tl warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent TI deems necessary to support t
4. es 4 5V to 5 5V DC Input or Output Voltage Vi Vo Input Rise and Fall Slew Rate dt dv AC Types 1 5V to 3V 50ns Max AC Types 3 6V to 5 5V 20ns Max ACT Types 4 5V to 5 5V 10ns Max CAUTION Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied NOTES 3 For up to 4 outputs per device add 25mA for each additional output 4 Unless otherwise specified all voltages are referenced to ground 5 8a is measured with the component mounted on an evaluation PC board in free air DC Electrical Specifications TEST 40 C TO 55 C TO CONDITIONS 125 C PARAMETER SYMBOL AC TYPES High Level Input Voltage Low Level Input Voltage lt os o fe e e wfe ja e e o e j ee e Ce feja ej e 75 5 5 3 85 Note 6 7 50 3 85 Note 6 7 lt lt lt lt lt CD74AC245 CD74ACT245 DC Electrical Specifications Continued TEST CONDITIONS Veo PARAMETER SYMBOL Low Level Output Voltage VoL a D a R T gt Input Leakage Current Voc or GND Three State Leakage Viy or Vib Current Vo Vcc or GND Quiescent Supply Current loc Vec or MSI GND ACT TYPES High Level Input Voltage 4 5 to 5 5 5 5 High Level Output Voltage Viy or Vi 005 005 05 75 Note 6 7
5. his warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or services might be or are used Tl s publication of information regarding any third party s products or services does not constitute Tl s approval warranty or endorsement thereof Copyright 1999 Texas Instruments Incorporated
6. tance Cpp 57 57 pF Note 11 ACT TYPES Propagation Delay tpLH tPHL Data to Output uae 10 Propagation Delay tpLz tpHz Output Disable to Output Propagation Delay PZL tpzH Output Enable to Output Minimum Valley Voy During VOHV at Switching of Other Outputs See Figure 1 25 C Output Under Test Not Switching Maximum Peak Vog During VoLP 1 at Switching of Other Outputs See Figure 1 25 C Output Under Test Not Switching CD74AC245 CD74ACT245 Switching Specifications Input t t 3ns C 50pF Worst a Continued Input Input Capacitance Power Dissipation ae Note 11 NOTES Limits tested 100 3 3V Min is at 3 6V Max is at 3V 5V Min is at 5 5V Max is at 4 5V Cpp is used to determine the dynamic power consumption per channel AC Pp Vcc fi Cpp CL ACT Pp Vec fi Cpp CL Vcc Alec where fi input frequency C output load capacitance Vcc supply voltage ots VoH 4 OTHER y OUTPUTS A a a 4 Noe ees VoL _f VoH OUTPUT Vov UNDER TEST eee eee ee VoL NOTES 12 Input pulses have the following characteristics PRR lt 1MHz tr 3ns SKEW ins 13 R F fixture with 700MHz design rules required IC should be soldered into test board and bypassed with 0 1uF capacitor Scope and probes require 7OOMHz bandwidth FIGURE 1 SIMULTANEOUS SWITCHING TRANSIENT WAVEFORMS CD74AC245 CD74ACT245 tp 3ns OUTPUTS DISAB
7. ustomer service for ordering information CD74AC245 CD74ACT245 PDIP SSOP SOIC CAUTION These devices are sensitive to electrostatic discharge Users should follow proper IC Handling Procedures FAST is a Trademark of Fairchild Semiconductor Copyright Harris Corporation 1998 TOP VIEW File Number 1907 1 CD74AC245 CD74ACT245 Functional Diagram TRUTH TABLE CONTROL INPUTS H High Level L Low Level X Irrelevant To prevent excess currents in the High Z isolation modes all I O terminals should be terminated with 10kQ to 1MQ resistors CD74AC245 CD74ACT245 Absolute Maximum Ratings Thermal Information DC Supply Voltage Vcc 0 5V to 6V Thermal Resistance Typical Note 5 DC Input Diode Current lik PDIP Package For Vj lt 0 5V or V gt Veg 0 5V 2 cece ec ec ee eee 20MA SOIC Package DC Output Diode Current lox SSOP Package For Vo lt 0 5V or Vo gt Voc 0 5V n eee eee eee 50mMA Maximum Junction Temperature Plastic Package DC Output Source or Sink Current per Output Pin lo Maximum Storage Temperature Range 65 C to 150 C For Vo gt 0 5V or Vo lt Voc 0 5V eee eee 50mA Maximum Lead Temperature Soldering 10s DC Vcc or Ground Current Icc or lanp Note 3 100mA Operating Conditions Temperature Range Ta 55 C to 125 C Supply Voltage Range Vcc Note 4 AG Pesada iire eana A Ra heck SI ee Oh 1 5V to 5 5V AGT TYPES cfoece oe E ate beet heen ion emanat
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TEXAS INSTRUMENTS D74AC245 CD74ACT245 Octal Bus Transceiver Three State Non Inverting handbook