TEXAS INSTRUMENTS CD74AC175 CD74ACT175 Quad D Flip-Flop with Reset handbook
Contents
1. e a Oo oO j SITSlololo RI RPS ops D oa im 6 7 ee 6 7 Input Leakage Current Voc or GND Quiescent Supply Current loc Vec or MSI GND ACT TYPES High Level Input Voltage al Low Level Input Voltage pate High Level Output Voltage Viy or Vib 0 05 z da 1 Aa a ay gt A oa a oa ala oa oa oa 3 85 75 Note 6 7 oa eae Ee a Ea Oo ary Low Level Output Voltage Vin or Vit 0 36 1 65 D Input Leakage Current Vcc or GND Quiescent Supply Current loc Vec or MSI GND Additional Supply Current per Alce Voc 4 5 to 2 4 3 Input Pin TTL Inputs High 2 1 1 Unit Load NOTES 18 Test one output at a time for a 1 second maximum duration Measurement is made by forcing current and measuring voltage to minimize power dissipation 4 e2 Oo esi JES DE 3 94 AEM FF 19 Test verifies a minimum 50 transmission line drive capability at 85 C 75Q at 125 C ACT Input Load Table NOTE Unit load is Alcc limit specified in DC Electrical Specifications Table e g 2 4mA max at 25 C CD74AC175 CD74ACT175 Prerequisite For Switching Function 40 C TO 85 C 55 C TO 125 C AC TYPES Hold Time Removal Time MR to CP MR Pulse Width CP Pulse Width CP Frequency ACT TYPES Data to CP Set Up Time Cn T a EA o a a e e E fs eT a a E C 2 E E A C T Pe ee NOTES 20 3 3V Min is at 3V 21 5V Min is at 4 5V Switching2. Specifications Input t tt 3ns CL 50pF Worst Case 40 C TO 85 C 55 C TO 125 C AC TYPES _ 3 15 5 1 Note 11 CD74AC175 CD74ACT175 Switching Specifications Input t t 3ns C 50pF Worst Case Continued 40 C TO 85 C 55 C TO 125 C PARAMETER SYMBOL Vcc V TYP MAX TYP MAX UNITS cc Propagation Delay MRtoQ Q tpiy tpHL os 82 8 CL E L E A E E E E F ae ee Ce e e ee ee a a OO S N A Note 13 A a o l o a l l ACT TYPES Propagation Delay CP to Qn PLH PHL 5 3 10 5 2 9 11 5 ns Note 12 Poran oon mon nea 5 93 e ao e Input Capacitance CET enee Note 13 Limits tested 100 3 3V Min is at 3 6V Max is at 3V 5V Min is at 5 5V Max is at 4 5V Cpp is used to determine the dynamic power consumption per flip flop Pp Cpp Vec fi CL Vec2 fo Vcc Alcc where fi input frequency f output frequency C output load capacitance Vcc supply voltage INPUT LEVEL GND INPUT LEVEL INPUT Vs GND xe tw FIGURE 5 PROPAGATION DELAYS FIGURE 6 RESET OR SET PREREQUISITE AND PROPAGATION DELAYS OUTPUT RL NOTE OUTPUT INPUT LEVEL LOAD GND tH H NOTE For AC Series Only When Vcc 1 5V RL 1kQ INPUT LEVEL cd FIGURE 7 FIGURE 8 PROPAGATION DELAY TIMES IMPORTANT NOTICE Texas Instruments and its subsidiaries Tl reserve the right to make changes to their products or to discontinue any product or service
3. AS i8 CD74AC 175 AV FS te TEXAS INSTRUMENTS Data sheet acquired from Harris Semiconductor SCHS242 September 1998 Features Buffered Inputs Typical Propagation Delay 6 4ns at Voc 5V Ta 25 C C 50pF Exceeds 2kV ESD Protection MIL STD 883 Method 3015 SCR Latchup Resistant CMOS Process and Circuit Design Speed of Bipolar FAST AS S with Significantly Reduced Power Consumption Balanced Propagation Delays AC Types Feature 1 5V to 5 5V Operation and Balanced Noise Immunity at 30 of the Supply 24mA Output Drive Current Fanout to 15 FAST ICs Drives 50Q Transmission Lines Pinout CD74AC175 CD 4ACT175 Quad D Flip Flop with Reset Description The CD74AC175 and CD74ACT175 are quad D flip flops with reset that utilize the Harris Advanced CMOS Logic tech nology Information at the D input is transferred to the Q and Q outputs on the positive going edge of the clock pulse All four flip flops are controlled by a common clock CP and a common reset MR Resetting is accomplished by a LOW logic level independent of the clock Ordering Information maen _rance ecy eackace no NUMBER RANGE C PACKAGE NOTES 13 When ordering use the entire part number Add the suffix 96 to obtain the variant in the tape and reel 14 Wafer and die for this part number is available which meets all elec trical specifications Please contact your local sales office or Harris customer service for orderin
4. e Maximum Storage Temperature Range Maximum Lead Temperature Soldering 10s SOIC Lead Tips Only 65 C to 150 C AC Types 1 5V to 3V AC Types 3 6V to 5 5V ACT Types 4 5V to 5 5V 50ns Max 20ns Max 10ns Max CAUTION Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied NOTES 15 For up to 4 outputs per device add 25mA for each additional output 16 Unless otherwise specified all voltages are referenced to ground 17 Oja is measured with the component mounted on an evaluation PC board in free air DC Electrical Specifications TEST CONDITIONS PARAMETER SYMBOL AC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage VoH 5 5 Note 6 7 50 Note 6 7 40 C TO 550 C TO y 25 C 85 C 125 C cc V UNITS poy ip 3 o D to oo oe oa o oe oa PPPs Alo A M A foo wj feo LSIN A N gt i NPA AP oO A Ned 0 a gt o oa wo w o fo oi CD74AC175 CD74ACT175 DC Electrical Specifications Continued TEST 40 C TO 55 C TO e PARAMETER SYMBOL V L a EE UNITS Low Level Output Voltage Vin or VIL a Eee Ea ee Ca E ai a i ak a oO ua wj A oj
5. g information CD74AC175 CD74ACT175 PDIP SOIC CAUTION These devices are sensitive to electrostatic discharge Users should follow proper IC Handling Procedures FAST is a Trademark of Fairchild Semiconductor Copyright Harris Corporation 1998 TOP VIEW File Number 1964 1 CD74AC175 CD74ACT175 Functional Diagram TRUTH TABLE EACH FLIP FLOP INPUTS OUTPUTS High Level Steady State Low Level Steady State Irrelevant Transition from Low to High level QO Q0 Level before the Indicated Steady State Input conditions were established CD74AC175 CD74ACT175 Absolute Maximum Ratings DC Supply Voltage Vcc DC Input Diode Current lik For Vi lt 0 5V or Vj gt Vec t 0 5V 6 eee eee 20mA DC Output Diode Current lox For Vo lt 0 5V or Vo gt Veg 0 5V cece reece eee 50mA DC Output Source or Sink Current per Output Pin Io For Vo gt 0 5V or Vo lt Vee 0 5V 0 eee eee eee 50mA DC Vcc or Ground Current Icc or lanp Note 3 100mA 0 5V to 6V Operating Conditions Temperature Range TA Supply Voltage Range Vcc Note 4 AG Pesada iire eana A Ra heck SI ee Oh 1 5V to 5 5V AGT TYPES cfoece oe E ate beet heen ion emanates 4 5V to 5 5V DC Input or Output Voltage Vi Vo Input Rise and Fall Slew Rate dt dv 55 C to 125 C Thermal Information Thermal Resistance Typical Note 5 PDIP Package SOIC Package Maximum Junction Temperature Plastic Packag
6. oduct design TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or services might be or are used Tl s publication of information regarding any third party s products or services does not constitute Tl s approval warranty or endorsement thereof Copyright 1999 Texas Instruments Incorporated
7. without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement including those pertaining to warranty patent infringement and limitation of liability Tl warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer pr
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TEXAS INSTRUMENTS CD74AC175 CD74ACT175 Quad D Flip Flop with Reset handbook