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PHILIPS 74HC/HCT4020 14-stage binary ripple counter handbook

1. BEi 74H C HCT 4020 AF nM INTEGRATEDCIRCUTS GRATED CIRCUITS DATA SHEET For a complete data sheet please also download e The ICO6 74HC HCT HCU HCMOS Logic Family Specifications e The IC06 74HC HCT HCU HCMOS Logic Package Information e The IC06 74HC HCT HCU HCMOS Logic Package Outlines 74HC HCT4020 14 stage binary ripple counter Product specification September 1993 File under Integrated Circuits ICO6 Philips Semiconductors PHILIPS Philips Semiconductors Product specification 14 stage ple counter 74HC HCT4020 FEATURES Output capability standard Icc category MSI GENERAL DESCRIPTION The 74HC HCT4020 are high speed Si gate CMOS devices and are pin compatible with the 4020 of the 40008 series They are specified in compliance with JEDEC standard no 7A QUICK REFERENCE DATA GND 0 V Tamb 25 C tr t 6 ns The 74HC HCT4020 are 14 stage binary ripple counters with a clock input CP an overriding asynchronous master reset input MR and twelve fully buffered parallel outputs Qo Q3 to Q13 The counter is advanced on the HIGH to LOW transition of TP A HIGH on MR clears all counter stages and forces all outputs LOW independent of the state of CP Each counter stage is a static toggle flip flop TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC HeT trute propagation delay G 15 pF
2. Te propagation delay 55 170 215 225 ns 20 Fig8 MR to Qn 20 34 43 51 45 16 29 37 43 60 tral tro output transition time 19 75 a35 no ns 20 Fo7 7 i5 19 22 45 e 13 16 19 60 w lock pulse width 8 fi 100 120 ns 20 Fig7 HIGH or LOW 16 ja 20 24 45 14 3 7 20 60 w master reset pulse width 80 17 100 120 ns 20 Figs HIGH 16 6 20 24 45 14 5 17 20 60 tem removal time 50 fe 65 75 ns 20 Figs MR to CP 10 2 13 15 45 9 2 1 13 60 te maximum clock pulse 6 0 30 48 40 Maz 20 Fig 7 frequency 30 92 24 20 45 35 109 28 24 60 September 1993 5 Philips Semiconductors Product specification 14 stage binary ripple counter 74HC HCT4020 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see 74HC HCT HCU HCMOS Logic Family Specifications Output capability standard Ice category MSI Note to HCT types The value of additional quiescent supply current Acc for a unit load of 1 is given in the family specifications To determine Aloc per input multiply this value by the unit load coefficient shown in the table below INPUT UNIT LOAD COEFFICIENT OF 0 85 MR 1 10 AC CHARACTERISTICS FOR 74HCT GND 0 V ty t 6 ns C 50 pF TEST CONDITIONS SYMBOL PARAMETER UNIT y WAVEFORMS 25 40 to 85 40 to 125 Ww min typ max min max min max Tera thin propagation delay 18 36 45 s4 ns 45 Fi
3. Voo 5V TP to n 15 ns Q 10 Qnar 6 6 ns MR to On 17 19 ns pm maximum clock frequency w01 52 MHZ Ci input capacitance as Jas PF Cro power dissipation capacitance per package notes 1 and 2 19 20 pF Notes 1 Cep is used to determine the dynamic power dissipation Po in W Po Cpo x Voc x fi E C x Voc x fo where fi input frequency in MHz fo output frequency in MHz E C x Voc x fo sum of outputs Ca output load capacitance in pF Voc supply voltage in V 2 For HC the condition is Vi For HOT the condition is Vj ND to Voc IND to Vec 1 5 V ORDERING INFORMATION See 74HC HCT HCU HCMOS Logic Package Information September 1993 Philips Semiconductors Product specification 14 stage binary ripple counter 74HC HCT4020 PIN DESCRIPTION PIN NO SYMBOL NAME AND FUNCTION 9 7 5 4 6 13 12 14 15 1 2 3 8 10 16 Qo Qsto Qia GND TP MR Voc parallel outputs ground 0 V clock input HIGH to LOW edge triggered master reset input active HIGH positive supply voltage Fig Pin configuration FOTATA o cT 3 Fig 2 Logic symbol Fig 3 IEC logic symbol September 1993 Philips Semiconductors Product specification 14 stage binary ripple counter 74HC HCT4020 FUNCTION TABLE X
4. don t care transition transition o nmm on Fig 5 Logic diagram INPUTS OUTPUTS RAR se sace counten GF MR G Qstodis ag T T no change Po os fou os Joe o gt Joe Pe Pron foralors L L count amn P e be fa fe he g x H L Notes Fig 4 Functional diagram 1 H HIGH voltage level L LOW voltage level 7 LOW to HIGH clock 4 HIGH to LOW clock ser Tr i r U o U i mor 1 e aE n yy ly ey Pe Eg ay a Da Ta a aE O AD EOSEEESENS sag By G y DE y Ey E a E n 24 out ag ely Ry i ey ea Cy Ky Ey i CE E S ag our py TE el yl E ae Ty Fi Ty Te eg ve aa a ee re aS ee 8 urna EEL eyovmer a G G aoum FGE org oumur Pa Fig 6 Timing diagram September 1993 4 Philips Semiconductors Product specification 14 stage binary ripple counter 74HC HCT4020 DC CHARACTERISTICS FOR 74HC For the DC characteristics see 74HC HCT HCU HCMOS Logic Family Specifications Output capability standard Ice category MSI AC CHARACTERISTICS FOR 74HC GND O V t ty 6 ns C 50 pF Tame C TEST CONDITIONS 74HC SYMBOL PARAMETER UNIT Vog WAVEFORMS 25 40 to 85 40 to 125 v min typ max min max min max Tend thin propagation delay a9 J140 175 210 ns 20 Fig7 TP to Qo 14 28 35 42 45 n ae 30 36 60 tenu tein propagation delay 22 75 35 no ns 20 Fo7 Qn t0 Qn a jis 19 22 45 e 13 16 19 60
5. g7 CP to Qo Tera thin propagation delay a fis 19 22 ns 45 Fig7 Qn t0 Onis Tea propagation delay 22 45 56 e8 ns 45 Figs MR to Qn Tra trun output transition time 7 f5 19 22 ns 45 Fig7 tw Glock pulse width 2 7 25 30 ns 45 Fig7 HIGH or LOW tw master reset pulse width 20 8 25 30 ns 45 Fig8 HIGH Ten removal time 1w 2 13 15 ns 45 Fig8 MR to CP p maximum clock pulse 25 47 20 17 Maz 45 Fig7 frequency September 1993 6 Philips Semiconductors Product specification 14 stage binary ripple counter 74HC HCT4020 AC WAVEFORMS G weur 0 outeu 1 HO Vu 50t Vi GND to Vec HOT V4 1 3 V Vi GND to SV Fig 7 Waveforms showing the clock GP to output Qa propagation delays the clock pulse width the output transition times and the maximum clock frequency ma iNpur E meur ap oureut 1 HO Vu 500 Vi GND to Vec HOT Vu 1 3 V Vi GND t0 3 V Fig 8 Waveforms showing the master reset MR pulse width the master reset to output Qn propagation delays and the master reset to clock GP removal time PACKAGE OUTLINES See 74HC HCT HCU HCMOS Logic Package Outlines September 1993 7

PHILIPS 74HC/HCT4020 14-stage binary ripple counter handbook

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