POWER-ONE ZY7120 20A DC-DC Intelligent POL handbook
Contents
1. ZY 720HG Q1 TET U POWEr ONne ZY7120 20A DC DC Intelligent POL Data Sheet 3V to 13 2V Input 0 5V to 5 5V Output hanging the Shape of Power wet pomm A Compliant Applications Low voltage high density systems with Intermediate Bus Architectures IBA Point of load regulators for high performance DSP FPGA ASIC and microprocessor applications Desktops servers and portable computing Broadband networking optical and communications systems Active memory bus terminators Benefits Integrates digital power conversion with intelligent power management Eliminates the need for external power management components Completely programmable via industry standard communication bus One part that covers all applications Reduces board space system cost and complexity and time to market Description Member of the MaX YZ Family Features RoHS lead free and lead solder exempt products are available Wide input voltage range 3V 13 2V High continuous output current 20A Wide programmable output voltage range 0 5V 5 5V Active digital current share Single wire serial communication bus for frequency synchronization programming and monitoring Optimal voltage positioning with programmable slope of the VI line Overcurrent overvoltage undervoltage and overtemperature protections with programmable thresholds and types Programmable fixed2. hanging the Shape of Power 6 Typical Application Intermediate Voltage Bus SD C exe OK B SOKA d ZY7120 ZY7120 ZY7120 ZY7120 ADDRE ADDR ADDRE ADDR V1 V2 V3 Figure 25 Block Diagram of Typical Multiple Output Application with Digital Power Manager and Interface The block diagram of a typical application of ZY7120 point of load converters POL is shown in Figure 25 The system includes multiple POLs and a ZM7000 series Digital Power Manager DPM All POLs are connected to the DPM and to each other via a single wire SD sync data line The line provides synchronization of all POLs to the master clock generated by the DPM and simultaneously performs bidirectional data transfer between POLs and the DPM Each POL has a unique 5 bit address programmed by grounding respective address pins To enable the current share CS pins of POLs connected in parallel are linked together There are three groups of POLs in the application groups A B and group C A group is defined as a number of POLs interconnected via OK pins Grouping of POLs enables users to program control and monitor multiple POLs simultaneously and execute advanced fault management schemes The complete schematic of the application is shown in Figure 26 REV 2 1 MAR 14 2007 WWW power one com Page 14 of 34 x Pli ZY7120 20A DC DC Intelligent POL Data Sheet SN 3V to 13 2V Input 0 5V to 5 5V Output POWES ONC
3. iE 500 4 058 20 Figure 14 Turn On with Sequencing and Tracking Rising Slew Rate Programmed at 0 2V ms V1 and V3 delays are programmed at 20ms Vinz12V Ch1 V1 Ch2 V2 Ch3 V3 Tek Run 197 000 4 5 Chl High MS M UTE DRE aad 2020V Ch2 High 1 850 V Ch3 High 1 510 V SAC WRT USC UNT UNN ET YOR ON SN PS SOT Yr NS TER ES DNE ET VERY TPT YORE NS RTS ERE ES NS HS VU JR PO DIR INE ENG EN E Chi 500mV LY 300mV hard 00ms rn chi f 190mv ik 500mV fy 58 20 Figure 15 Turn On into Prebiased Load V3 is Prebiased by V2 via a Diode Vin 12V Ch1 V1 Ch2 V2 Ch3 V3 REV 2 1 MAR 14 2007 WWW power one com 3V to 13 2V Input 0 5V to 5 5V Output 5 3 Turn Off Characteristics Tek Prevu J Ch1 High 2 022V ken beoe TERE eee ch2 High i J 1 835 V Ch3 High ee ae ek es Tat Sea uel MEC AE ane Sage Tt eee Wn SC E T E 1 j 307 V SUM LUE 500 cune S00mV rim 0015 X uix UV 808 500mV 23 00 Figure 16 Tracking Turn Off Falling Slew Rate is Programmed at 0 5V ms Vin 12V Ch1 V1 Ch2 V2 Ch3 V3 Tek Run Ch1 High 2 040 V Ch2 High 1 845 V Ch3 High 1 510 V chi soomv ELEF 20017 Ooms A Chi X 134v IE 500mV 62 80 Figure 17 Turn Off with Tracking and Sequencing
4. 83 82 81 80 79 Fsw 500kHz Fsw 750kHzZ Fsw 1 000kHz 78 0 2 4 6 8 10 12 14 16 18 20 Output Current A Figure 8 Efficiency vs Load Vin 5V Vout 1 2V 94 93 92 91 90 89 88 87 86 85 84 83 Fsw 500kHZ Fsw 750kHz Fsw 1 OOOKHz 82 Output Current A Figure 9 Efficiency vs Load Vin 12V Vout 5V Page 9 of 34 ZY7120 20A DC DC Intelligent POL Data Sheet to 13 2V Input 0 5V to 5 5V Output la PowWEer one hanging the Shape of Power 94 93 M E 91 90 89 Vin 3 3V Vout 2 5V 88 Vin 5V Vout 1 2V Efficiency 96 87 1 Vin 12V Vout 5V 86 85 84 83 82 500 750 1000 Switching Frequency kHz Figure 10 Efficiency vs Switching Frequency lout 20A 5 2 Turn On Characteristics Tek Prevu jj ____ ______ Trig Ch1 High 2 035 V Ch2 High 1 850 V Ch3 High 1 510 V ESE RET er elt or er Lee TEE Ye Tot TEE TERI AS VN EAN YOR SOTTO t INE ERE TSE Ma INC IBI NLIS UMS DESTIN E A RT a hannah chi s00mv LY 300mV Wr 00ms A chi f 220mV SIE 500mV 5 9 24 60 Figure 11 Tracking Turn On Rising Sl
5. S Changing the Shape of Power Ce e 9 TEN 8 ut I i n 2 1 36 P T o 8 1 NH g d g Bou i v i E i gt m 8 s z b EXEEE E 88 99999 99999 FF z s s AEN M 4 oR gt gt en t n o 9 A A h a h M 5 qE JR A s x a NH z d m m gt sje c oct mr 5 2 u Freee 299gg E E g x 99999 eoooo m P JS EEE e D 10 10 10 VOD VOD VOD YOD YOC 1Dk 40k Tion 2 Figure 26 Complete Schematic of the Application Shown in Figure 25 Intermediate Bus Voltage is from 4 75V to 13 2V REV 2 1 MAR 14 2007 WWW power one com Page 15 of 34 ZY7120 20A DC DC Intelligent POL Data Sheet 3V to 13 2V Input 0 5V to 5 5V Output POWEr ONne hanging the Shape of Power T Pin Assignments and Description a eee oT enm Mame Type Type IBV lt 4 T5V Connect to Vi 75 ee w 3 ws team i wem _ w s ws tee ans w s wed boton 7 wem _ w s SSCs ave toting EN 10 Connect to PGND Connect to PGND 41 IO PU Condition Connect to OK pin of other Z POL and or DPM Leave floating i
6. Falling Slew Rate is Programmed at 0 5V ms Vinz12V Ch1 V1 Ch2 V2 Ch3 V3 Page 11 of 34 ZY7120 20A DC DC Intelligent POL Data Sheet 3V to 13 2V Input 0 5V to 5 5V Output PN PowWEer one hanging the Shape of Power 5 4 Transient Response The pictures below show the deviation of the output voltage in response to the 50 100 50 step load at 1A us In all tests the ZY7120 converters were switching at 1MHz and had 5x22uF and 5x47yF ceramic capacitors connected across the output pins Bandwidth of the feedback loop was programmed for faster transient response Tek al Ch3 Max 64 92mV Ch3 Min 1 76 80mvV SEE ET D SEXE TRE EPIIT SIBI ST ST ee UMS SD TBE SORT ME RR ET EI TORT PS TET Seer EP OT SE RT TOYO LC POE Y DT ENS PET MET NL M 1000 A Ch3 J 46 0mV 14Jan 2005 31 00 12 48 22 iE 50 0 Figure 18 Vin 12V Vout 5V BW 40kHz Tek EE Ch3 Max Se xc RE cc 67 20 Ch3 Min 1 82 47mV HS EES er p BOL DEN PO E PEN SO PR AR PEE TE AA A Tr Pmt LOT TEE EE pl M NS Rent aT ES 1 M 100 45 rn Ch3 7 46 OMV 14Jan 2005 831 00 17 16 01 iE 50 0MV A5 Figure 19 Vin 12V Vout 1V BW 35kHz REV 2 1 MAR 14 2007 www power one com Tek Ch3 Max 77 40mV 1 cCh3 Min 91 08mV aL 7 859 0mv 13 Jan 2005 30 40 18 26 53 Figure 20
7. Overtemperature Protection Default Non Latching 130ms period Programmable Latching Non Latching Turn Off Threshold Temperature is increasing 1 30 C Temperature is decreasing after the module was Dela From instant when threshold is exceeded until y the turn off command is generated H Tracking Protection when Enabled Default Disabled Programmable Latching Non Latching 130ms period Enabled during output voltage ramping up From instant when threshold is exceeded until the turn off command is generated Overtemperature Warning Programmapen S steps 9 o o ey IeoPesgehaxes __ 9 status of PG signal changes l Minimum OVP threshold is 1 0V REV 2 1 MAR 14 2007 www power one com Page 5 of 34 ZY7120 20A DC DC Intelligent POL Data Sheet 3V to 13 2V Input 0 5V to 5 5V Output POWET ONE hanging the Shape of Power 4 4 Feature Specifications Current Share Maximum Number of Modules m Maximum Number of Modules 2 Connected Parallel OUT MIN Interleave Default Degree Programmable in 11 25 steps 348 75 degree Sequencing Turn ON Delay Default Programmable in 1ms steps Turn OFF Delay Tracking Turn ON Slew Rate Default Turn OFF Slew Rate Programmable in 7 steps Optimal Voltage Positioning Feedback Loop Compensation Zero1 Effects phase lead and aree Programmable increases gain in mid b
8. The group includes overvoltage protection and the phase voltage error The phase voltage error is not available in ZY 7120 8 3 3 1 Overvoltage Protection The overvoltage protection is active whenever the output voltage of the POL exceeds the pre bias voltage if any If the output voltage exceeds the overvoltage protection threshold the overvoltage error signal is generated the POL turns off and the OV bit in the register ST is changed to 0 The high side switch is turned off instantly and simultaneously the low side switch is turned on to ensure reliable protection of sensitive loads The low side switch provides low impedance path to quickly dissipate REV 2 1 MAR 14 2007 WWW power one com energy stored in the output filter and achieve effective voltage limitation The OV threshold can be programmed from 110 to 130 of the output voltage setpoint but not lower than 1 0V 8 3 4 Faults and Errors Propagation The feature adds flexibility to the fault management scheme by giving users control over propagation of fault signals within and outside of the system The propagation means that a fault in one POL can be programmed to turn off other POLs and devices in the system even if they are not directly affected by the fault Page 23 of 34 ZY7120 20A DC DC Intelligent POL Data Sheet to 13 2V Input 0 5V to 5 5V Output POWEr ONne hanging the Shape of Power 8 3 4 1 Grouping of POLs
9. Vin 5V Vout 2 5V BW 45kHz iE 50 0 Ch3 Max 72 04mV i Ch3 Min j 78 53mV 7M i00ps rn Ch3 E 46 IE 50 0 14 2005 0 31 00 16 31 58 Figure 21 Vinz5V Vout 1V BW 40kHz Tek EDS Ch3 Max 77 47mV i Ch3 Min 1 92 60mv PRES i UU WS RF TEC IIS SUUS RP MO Te GL TUE DUCI RET INR SYRIEN PET E E EE TEE TEA FOOT YON BD 1 M 1000 r J 76 OMV 14Jan 2005 i 31 00 15 59 04 Figure 22 Vinz3 3V Vout 1V BW 40kHz iE 50 0mV v5 Page 12 of 34 ZY7120 20A DC DC Intelligent POL Data Sheet SN 3V to 13 2V Input 0 5V to 5 5V Output POWETS ONE hanging the Shape of Power 5 5 Thermal Derating Curves 20 18 O Output Current A gt 12 10 0 LFM 100 LFM 200 LFM 400 LFM 600 LFM 8 35 45 95 65 19 85 Temperature Figure 23 Thermal Derating Curves Vin 13 2V Vout 5 0V Fsw 500kHz 20 lt 19 9 18 5 O amp 17 5 O 16 0 LFM 100 LFM 200 LFM 400 LFM 600 LFM 15 65 70 15 80 85 Temperature Figure 24 Thermal Derating Curves Vin 5 0V Vout 2 5V Fsw 500kHz REV 2 1 MAR 14 2007 WWW power one com Page 13 of 34 49 IB Put ZY7120 20A DC DC Intelligent POL Data Sheet to 13 2V Input 0 5V to 5 5V Output la PoWEr one
10. 1 MAR 14 2007 WWW power one com Page 34 of 34
11. R w o FRQ2 FRQ1 FRQO INT4 INT3 INT2 INT 1 INTO Bit 7 Bit 0 Bit 7 5 FRQ 2 0 PWM Frequency Selection R Readable bit 000 500 2 W Writable bit 001 750kHz U Unimplemented bit 010 1000IHz read as 0 011 1250kHz 100 1250kHz 101 1500kHz 110 1750kHz 111 2000kHz Bit 4 0 INT 4 0 Interleave position 00h Ton starts with 0 0 Phase lag to SD Line 01h Ton starts wi th 11 25 Phase lag to SD Line 02h Ton starts with 22 50 Phase lag to SD Line n Value at POR reset 1Fh Ton starts with 348 75 Phase lag to SD Line Initial value depends on the state of the Interleave Mode Input IM Open At POR reset the 5 corresponding ADDRESS bits are loaded IM Low At POR reset a 0 is loaded Figure 48 Interleave Configuration Register INT 8 4 2 Interleave Interleave is defined as a phase delay between the synchronizing slope of the master clock on the SD pin and PWM signal of a POL The interleave can be programmed in the GUI PWM Controller window or directly via the lC bus by writing into the INT register Every POL generates switching noise If no interleave is programmed all POLs in the system switch simultaneously and noise reflected to the input source from all POLs is added together as shown in Figure 49 Tek Stop a a NUES NOTES OP P ME ORE By RE je 296ns 2
12. Z Series POLs can be arranged in several groups to simplify fault management A group of POLs is defined as a number of POLs with interconnected OK pins A group can include from 1 to 32 POLs If fault propagation within a group is desired the propagation bit needs to be checked in the GUI Fault Management Window The parameters can also be programmed directly via the IC bus by writing into the PC3 register shown in Figure 43 When propagation is enabled the faulty POL pulls its OK pin low A low OK line initiates turn off of other POLs in the group RW 0 RMW 0 R AW 1 R W 1 R IW 1 R W 1 R W 1 R W 1 PTM PGM TRP OTP OCP UVP OVP PVP Bit 7 Bit 0 Bit 7 PTM Temperature warning Message Readable bit R 1 enabled W Writable bit 0 disabled U Unimplemented bit Bit6 Power good message read as 0 1 enabled Value at POR reset 0 disabled Bit5 TRP Tracking fault propagation 1 enabled 0 disabled Bit4 Overtemperature fault propagation 1 enabled 0 disabled Bit 3 OCP Overcurrent fault propagation 1 enabled 0 disabled Bit2 UVP Undervoltage fault propagation 1 enabled 0 disabled Bit 1 OVP Overvoltage error propagation 1 enabled 0 disabled BitO PVP Phase voltage error propagation 1 enabled 0 disabled Figure 43 Protection Configuration Register PC3 In addition the OK lines can be connected to the DP
13. between different voltage rails which frequently recommended by ASIC manufacturers When the tracking protection is enabled the POL continuously compares actual value of the output voltage to its programmed value as defined by the output voltage and its rising slew rate If absolute Vo Enable command 0 OTP continuously enabled OCP enabled L Power Good Signal 0 OVP Threshold PG High 110 Vour SS Output Voltage PG Low Threshold p E MUERE 1 0V UVP Threshold _ prebiased output eo Tracking Thresholds OVP Threshold High 110 Vour Output Voltage PG Low Threshold UVP Threshold value of the difference exceeds 250mV the tracking fault signal is generated the POL turns off and the TR bit in the register ST is changed to 0 Both high side and low side switches of the POL are turned off instantly fast turn off The tracking protection can be disabled if it contradicts requirements of a particular system for example turning into high capacitive load where rising slew rate is not important It can be disabled in the GUI Fault Management window or directly via the I C bus by writing into the PC1 register OVP Threshold PG High 110 Vour Output Voltage PG Low Threshold i UVP Threshold Time Figure 42 Protections Enable Conditions 8 3 3 Errors
14. of the calculated value It is not recommended to use ADC saturation for output voltages higher than 2 0V The ADC saturation feedforward be programmed in the GUI PWM Controller window or directly via the IC bus by writing into the DCL register 8 4 5 Feedback Loop Compensation Feedback loop compensation can be programmed in the GUI PWM Controller window by setting frequency of poles and zeros of the transfer function REV 2 1 MAR 14 2007 www power one com The transfer function of the POL converter is shown in Figure 54 It is a third order function with two zeros and three poles Pole 1 is the integrator pole Pole 2 is used in conjunction with Zero 1 and Zero 2 to adjust the phase lead and limit the gain increase in mid band Pole 3 is used as a high frequency low pass filter to limit PWM noise Magnitude dB 50 Z1 P122 P2 P3 EM DIM P1 Pole 1 P2 Pole 3 P3 Pole 3 Z1 Zero 1 Z2 Zero 2 40 Figure 54 Transfer Function of PWM Positions of poles and zeroes are determined by coefficients of the digital filter The filter is characterized by four numerator coefficients Co Cy C2 and three denominator coefficients B4 The coefficients are automatically calculated when desired frequency of poles and zeros is entered in the GUI PWM Controller window The coefficients are stored in the COH COL C1H C1L C2H C2L C3H C3L B1 B2 and B3 registers Note The GUI automatica
15. other It is permissible to mix POLs operating at different frequencies in one system It allows optimizing efficiency and transient response of each POL in the system individually PWM Controller Address 02 Transfer Function Step Response Performance Apply To POL wmm oop Gain Powertrain wee Controller BW 39554 Hz a ill Peak 2 01 1 79 V Dig Filter Coefficients Numerator Magnitude Denominator Bl 2 B2 5 B3 1 Switching Frequency 1 100 1k 10k 100k 1000k ADC Saturation Feedforward Frequency Hz Sets Duty Cycle to Limit Auto Compensation Manual Compensation L Low Sets Duty Cycle to 0 Note The Compensate Button will execute a design procedure to PWM Phase amp Limit automatically compensate the voltage feedback loop The automatic design procedure optimizes the step response and the phase margin of the feedback loop Whenever a parameter affecting the controller open loop gain is changed then the auto compensate function should again be invoked In some cases manual post optimization of pole zero Phase lag 0 Restore Defaults placements might be required v Note 4 The Transfer Function of the power train is calculated based on the X settings done in the Transient Analysis set up Window Duty Cyde Limit Figure 47 PWM Controller Window REV 2 1 MAR 14 2007 www power one com R W 0 R W 0 R w 0 RW 0 R w 0 R w o R w 0
16. 0 Figure 37 Protection Status Register ST Thresholds of overcurrent over and undervoltage protections and Power Good limits can be programmed the GU Output Configuration window or directly via the C bus by writing into the CLS and PC2 registers shown in Figure 38 and Figure 39 Page 20 of 34 ZY7120 20A DC DC Intelligent POL Data Sheet 3V to 13 2V Input 0 5V to 5 5V Output POWEr ONne hanging the Shape of Power R W 0 R W 0 R W 0 R W 1 R W 1 R W 0 R W 1 R W 1 Bit 7 Bit 0 Bit 7 5 LR 2 0 Load regulation configuration 000 0 V A Ohm W Writable bit 001 0 39 V A Ohm U Unimplemented bit 010 0 78 V A Ohm read as 0 011 1 18 V A Ohm n Value at POR reset 100 1 57 V A Ohm 101 1 96 V A Ohm 110 2 35 V A Ohm 111 2 75 V A Ohm Bit4 Temperature compensation enable 0 disabled 1 enabled Bit 3 0 CLS 3 0 Current limit setting Oh corresponds to 37 1h corresponds to 47 R Readable bit Bh corresponds to 140 Values higher than Bh are translated to Bh 140 Figure 38 Current Limit Setpoint Register CLS R W 0 R W 1 R W 0 R W 0 RW 0 J reu over ois weis overo Bit 0 U U aes Bit 7 Bit 7 5 Unimplemented read as 0 R Readable bit Bit4 Set Power Good Low Level W Writable bit 1 95 of Vo U Unimplemented bit 0 90 of Vo Default read as 0 Bit 3 2 OVPL 1 0 Set Over Volta
17. 0 R W 0 R W 0 R W 0 R W 0 RIW O Bit 7 Bit 7 0 VOS 7 0 Output voltage setting 00h corresponds to 0 5000V R Readable bit 01h corresponds to 0 5125V W Writable bit u U Unimplemented bit 77h corresponds to 1 9875V read as 0 78h corresponds to 2 0000V n Value at POR reset 79h corresponds to 2 025V F9h corresponds to 5 225V FAh corresponds to 5 250V FBh corresponds to 5 300V FFh corresponds to 5 500V Figure 28 Output Voltage Setpoint Register VOS Page 17 of 34 ZY7120 20A DC DC Intelligent POL Data Sheet to 13 2V Input 0 5V to 5 5V Output POWEr ONne hanging the Shape of Power 8 1 1 Output Voltage Setpoint The output voltage programming range is from 0 5V to 5 5V Within this range there are 256 predefined ERE voltage setpoints To improve resolution of the Limit output voltage settings the voltage range is divided into three sub ranges as shown in Table 2 Vout Operating Curve Without Point Load Regulation VI Curve With Load Regulation Headroom without Load Regulation Headrbom with Load Regulation Light lout Heavy Load Load Lower Regulation Table 2 Output Voltage Adjustment Resolution Limit Resolution 0 500 5 55 9 Figure 29 Concept of Optimal Voltage Positioning 8 1 2 Output Voltage Margining If the output voltage needs to be varied by a certain percentage the margining function can be utilized T
18. 2 1 Ch4 Pk Pk NEM 1 df NEM ood 52 4mV UH 11 3mV nenslaensdasendenenlenensensslennaleenalesnalenenienen denen lenen lens lennailenaleensinsen denen denen sensn lene lesnaleena neas denen lanea lesendonsnfense lese lesnc lanea lane iansn ene lanea dnena nean inean denen denen enen enne denen M400ns A Ch4 16 8mV 7 10 0mV v ii 37 80 Figure 49 Input Voltage Noise No Interleave Page 26 of 34 ZY7120 20A DC DC Intelligent POL Data Sheet POWEr ONne to 13 2V Input 0 5V to 5 5V Output hanging the Shape of Power Figure 50 shows the input voltage noise of the three output system with programmed interleave Instead of all three POLs switching at the same time as in the previous example the POLs V1 V2 and V3 switch at 0 123 75 and 247 5 respectively Noise is spread evenly across the switching cycle resulting in more than 1 5 times reduction To achieve similar noise reduction without the interleave will require the addition of an external LC filter Besor En gt uv 1 Ch4 Pk Pk 33 4mV Ch4 RMS 6 89mV UTE ea CE CEEE ea COT S tl Se NUT GEN IUS URS BONUS UE COE INE PR GO DUNS hannah EA Cha 16 8mV 10 0mV 8j i3 27 00 Figure 50 Input Voltage Noise with Interleave Similar noise reduction can be achieved on the output o
19. 33 of 34 ZY7120 20A DC DC Intelligent POL Data Sheet 3V to 13 2V Input 0 5V to 5 5V Output POWEr oNne hanging the Shape of Power 8 6 32 Unexposed thermal copper area associated with each pad 6 9 must be free from other traces 1 8 x 22 Pin 1 2 c c 1 27 2 54 1 27 2 03 10 10 0 8 Figure 60 Recommended Pad Sizes 8 6 8 6 8 6 4 OOOOOOOO 6 4 4 0 y OVJ IXOCOGDOC CO 0 45mm Thermal Via x 16 0 45mm Thermal Via x 16 0 45mm Thermal Via x 16 Recommended via diameter is 0 45mm Barrel wall plating of gt 25bum Pitch lt 1 00mm Figure 61 Recommended PCB Layout for Multilayer PCBs Notes 1 NUCLEAR AND MEDICAL APPLICATIONS Power One products are not designed intended for use in or authorized for use as critical components in life support systems equipment used in hazardous environments or nuclear control systems without the express written consent of the respective divisional president of Power One Inc 2 TECHNICAL REVISIONS The appearance of products including safety agency certifications pictured on labels may change depending on the date manufactured Specifications are subject to change without notice lC is a trademark of Philips Corporation REV 2
20. 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 SAO A Figure 4 Efficiency vs Load Vinz12V Fsw 500kHz Figure 2 Efficiency vs Load Vin 3 3V Fsw 500kHz 95 96 90 92 85 90 D 88 80 e se 86 5 E 75 gt 84 i 5 o 82 g 70 80 78 65 76 Vin 3 3V Vin 5 0V Vin 12V 74 60 7 ce vais oM 0 5 1 5 2 5 3 5 4 5 5 5 70 x Output Voltage V REV 2 1 MAR 14 2007 0 2 4 6 8 10 12 14 16 18 20 Output Current A Figure 3 Efficiency vs Load Vin 5V Fsw 500kHz WWW power one com Figure 5 Efficiency vs Output Voltage lout 20A Fsw 500kHz Page 8 of 34 la PoWEr one ZY7120 20A DC DC Intelligent POL Data Sheet to 13 2V Input 0 5V to 5 5V Output hanging the Shape of Power Efficiency 95 90 85 80 75 70 65 Vout 0 5V Vout 2 5V Vout 1 2V 60 Input Voltage V Figure 6 Efficiency vs Input Voltage lout 20A Fsw 500kHz Efficiency NO REV 2 1 MAR 14 2007 96 95 Fsw 500kHz Fsw 750kHz Fsw 1 000kHz co C2 co co e 0 2 4 6 8 10 12 14 16 18 20 Output Current A Figure 7 Efficiency vs Load Vin 3 3V Vout 2 5V Efficiency 96 Efficiency 96 WWW power one com 90 89 88 87 86 85 84
21. C connected to vee Ramping Down 2 5 VDC External Low Voltage Supply Connect to VLDO pin when Vin lt 4 75V VLDO Input Current Current drawn from the external low mADC voltage supply at Vi po 5V 4 2 Output Specifications Programmable EM Default no programming 0 5 Vin 12V lout 0 5 lout Fsw 500kHz room temperature eee orden E E AME EE Load Regulation 0 to lout max Dynamic Regulation Slew rate 1A us 50 100 load step Peak Deviation Cout 330uF Fsw 1MHz Settling Time to 10 of peak deviation Vin 5 0V Vout 0 5V Vin 5 0V Vout 2 5V Vin 13 2V Vout 0 5V Vin 13 2V Vout 2 5V Vin 13 2V Vout 5 OV 50 Temperature Coefficient Temperature Coefficient Vin 12V lout 0 5 lout max 6 ppm C Switching Frequency E Programmable 250kHz steps 1 000 kHz Default UD ye EE Programmable 1 56 steps To 1 ZY7120i is a step down converter thus the output voltage is always lower than the input voltage as show in Figure 1 At the negative output current bus terminator mode efficiency of the ZY7120 degrades resulting in increased internal power dissipation Therefore maximum allowable negative current under specific conditions is 20 lower than the current determined from the derating curves shown in paragraph 5 5 Output Voltage Peak to Peak Ripple and Noise BW 20MHz Full Load REV 2 1 MAR 14 2007 WWW power one com Page 3 of 34 ZY7120 20A DC DC Intelligent POL Da
22. M to facilitate propagation of faults and errors between groups One DPM can control up to 4 independent groups To enable fault propagation between groups the respective bit needs to be checked in the GUI Fault and Error Propagation window shown in Figure 44 REV 2 1 MAR 14 2007 www power one com Fault and Error Propagation Fault amp Error Propagation and if Error turns off triggers Front End Crow Bar d d 4a d Figure 44 Fault and Error Propagation Window In this case low OK line will signal DPM to pull other OK lines low to initiate shutdown of other POLs as programmed in the GUI Fault and Error Propagation window If an error is propagated the DPM can also generate commands to turn off a front end a DC DC converter generating the intermediate bus voltage and trigger an optional crowbar protection to accelerate removal of the IBV voltage 8 3 4 2 Propagation Process Propagation of a fault OCP UVP OTP and TRP initiates regular turn off of other POLs The faulty POL in this case performs either the regular or the fast turn off depending on specific fault as described in section 8 3 2 Propagation of an error initiates fast turn off of other POLs The faulty POL performs the fast turn off and turns on its low side switch Example of the fault propagation is shown in Figure 45 Figure 46 In this three output system refer to the block diagram in Figure 25 the POL powering the ou
23. PM Programming Manual Page 29 of 34 Ag D IB Put ZY7120 20A DC DC Intelligent POL Data Sheet AN to 13 2V Input 0 5V to 5 5V Output PUMEI DIIE S Changing the Shape of Power System Configuration ZM 300Demo p1c File Load Config Program Config Read Contig Gen Spec sheet generate Interrupts Fault Propagation Intermediate Bus Parallel Bus 1 Parallel Bus 2 Parallel Bus 3 Parallel Bus 4 Parallel Bus 5 Parallel Bus 6 Parallel Bus 7 Peale Bus ILL IL Figure 55 GUI System Configuration Window REV 2 1 MAR 14 2007 WWW power one com Page 30 of 34 iO B Pd ZY7120 20A DC DC Intelligent POL Data Sheet to 13 2V Input 0 5V to 5 5V Output AN PoWEr one hanging the Shape of Power POL Configuration Address 6 Device Type Fault Management Tracking Fault Temperature Fault Over Current Fault Under Voltage Error Over Voltage Fault Phase Voltage Error Output Configuration Output Voltage Load Regulation Current Limitation Over Voltage Threshold Power Good Low Threshold Under Voltage Threshold Sequencing Turn On Delay Turn On Slew Rate Turn Off Delay Turn Off Slew Rate PWM Controller Switching Frequency Zero 1 fero 2 Pole 1 Pole 2 Pole 3 PWM Phase Lag PWM Duty Limit Transient Simulation Set Up Window BEH ZY 7120 Disabled Auto Restart Propagate Auto Restar
24. able bit Bit 7 2 DCL 5 0 Duty Cycle Limitation Oh 0 W Writable bit 01h 1 64 U Unimplemented bit E read as 0 3Fh 63 64 n Value at POR reset Bit 1 ADC high saturation feed forward 0 disabled 1 enabled Bit 0 LO ADC low saturation feed forward 0 disabled 1 enabled Figure 53 Duty Cycle Limit Register 8 4 4 ADC Saturation Feedforward To speed up the PWM response in case of heavy dynamic loads the duty cycle can be forced either to 0 or the duty cycle limit depending on the polarity of the transient This function is equivalent to having two comparators defining a window around the output voltage setpoint When an error signal is inside the window it will produce gradual duty cycle change proportional to the error signal If the error signal goes outside the window usually due to large output current steps the duty cycle will change to its limit in one switching cycle In most cases this will significantly improve transient response of the controller reducing amount of required external capacitance Under certain circumstances usually when the maximum duty cycle limit significantly exceeds its nominal value the ADC saturation can lead to the overcompensation of the output error The phenomenon manifests itself as low frequency oscillations on the output of the POL It can usually be reduced or eliminated by disabling the ADC saturation or limiting the maximum duty cycle to 120 140
25. adversely affect long term reliability and cause permanent damage to the converter Parameter Conditions Description Operating Temperature Controller case temperature Input Voltage 250ms Transient o J 5 Output Current See Output Current Derating Curves 20 3 Environmental and Mechanical Specifications Parameter Conditons Descripton wm E E BE ts Calculated Per Telcordia Technologies SR 332 Peak Refow Tempore _ Peak RetowTenpertwe Moisture Sensitivity Level JEDEC J STD 020C 3 Nom NEN NEM NEN E REV 2 1 MAR 14 2007 WWW power one com Page 2 of 34 ZY7120 20A DC DC Intelligent POL Data Sheet 3V to 13 2V Input 0 5V to 5 5V Output POWEr oNne hanging the Shape of Power 4 Electrical Specifications Specifications apply at the input voltage from 3V to 13 2V output load from 0 to 20A ambient temperature from 40 to 85 C 100uF output capacitance and default performance parameters settings unless otherwise noted 4 1 Input Specifications Parameter Condi ionsDescripiion Min Nom Max Units At Vin lt 4 75V VLDO pin needs to be Input voltage Vin connected to an external voltage source higher than 4 75V Input Current at no load Vinz4 75V VLDO pin connected to VIN Undervoltage Lockout VLDO Ramping Up 4 2 VDC connected to an Ramping Down 3 75 VDC Undervoltage Lockout VLDO Ramping Up 3 0 VD
26. and Zero 2 Effects phase lead and i eee ne Programmable increases gain in mid band Pole 1 Integrator Pole effects loop gain POIG 2 Effects prase ag ana Programmable 1 1000 kHz limits gain in mid band Pole 3 High frequency low pass filter to limit PWM noise Peg mime di uis Voltage Monitoring Accuracy 1 LSB 22mV Current Monitoring Accuracy 20 lout lt lout lt lout Nom 20 Temperature Monitoring Accuracy Junction temperature of POL controller 54 Remote Voltage Sense VS and VS pins Voltage Drop Compensation Between VS and VOUT 30 Voltage Drop Compensation Between VS and PGND 100 mV Achieving fast slew rates under specific line and load conditions may require feedback loop adjustment REV 2 1 MAR 14 2007 WWW power one com Page 6 of 34 ZY7120 20A DC DC Intelligent POL Data Sheet 3V to 13 2V Input 0 5V to 5 5V Output POWET ONE hanging the Shape of Power 4 5 Signal Specifications Parameter Conditions Description Min DD Internal supply voltage 9 9 SYNC DATA Line SD pin ViL sd LOW level input voltage 0 5 0 3 x VDD ViH sd HIGH level input voltage UE VDD 0 5 n 0 25 x 0 45 x Vhyst sd Hysteresis of input Schmitt trigger Ty ou m lt O LOW level sink current 0 5V Tr_sd Maximum allowed rise time 10 90 VDD 300 ns asi Clock frequency of extemal 50 45 5 amp 5 wz i ae pm ge Inp
27. bit is cleared and the Power Good Warning is removed The Power Good pin can also be pulled low by an external circuit to initiate the Power Good Warning Note To retrieve status information Status Monitoring in the GUI POL Group Configuration Window should be enabled refer to Digital Power Manager Data Sheet The DPM will retrieve the status information from each POL on a continuous basis REV 2 1 MAR 14 2007 WWW power one com 8 3 2 Faults This group includes overcurrent overtemperature undervoltage and tracking protections Triggering any protection in this group will turn off the POL 8 3 2 1 Overcurrent Protection Overcurrent protection is active whenever the output voltage of the POL exceeds the prebias voltage if any When the output current reaches the OC threshold the output voltage will start decreasing As soon as the output voltage decreases below the undervoltage protection threshold the fault signal is generated the POL turns off and the OC bit in the register ST is changed to 0 Both high side and low side switches of the POL are turned off instantly fast turn off The temperature compensation is added to keep the threshold approximately constant at temperatures above room temperature Note that the temperature compensation can be disabled in the GUI Output Configuration window or directly via the lC by writing into the CLS register However it is recommended to keep the temperatur
28. ble 1 ZY7120 Memory Registers Frequency Selection RUN Register B1 Dig Controller Denominator z Coefficient Coefficient Coefficient Coefficient Low Byte Coefficient High Byte Coefficient Low Byte Coefficient High Byte Coefficient Low Byte Coefficient High Byte Coefficient High Byte Coefficient Low Byte Output Current Monitoring Temperature Monitoring REV 2 1 MAR 14 2007 www power one com ZY 120 converters can be programmed using the Graphical User Interface or directly via the I C bus by using high and low level commands as described in the DPM Programming Manual ZY 120 parameters can be reprogrammed at any time during the system operation and service except for the digital filter coefficients the switching frequency and the duty cycle limit that can only be changed when the POL is turned off 8 1 Output Voltage The output voltage can be programmed in the GUI Output Configuration window shown in the Figure 27 or directly via the lC bus by writing into the VOS register shown in Figure 28 Output Configuration Address 02 Output Settings Margining Voltage 7 High 2 10 V 45 095 Y x 1 90 V 4 Low 5 0 Load Regulation Load Regulation 0 00mv A Monitoring Thresholds Over Voltage 130 w 2 60V 15 20 Power Good High 110 2 20V Current Power Good Low 90 1 80 V Under Voltage 75 1 50V Figure 27 Output Configuration Window R W 0O R W 0 R W
29. e compensation enabled 8 3 2 2 Undervoltage Protection The undervoltage protection is only active during steady state operation of the POL to prevent nuisance tripping If the output voltage decreases below the UV threshold and there is no OC fault the UV fault signal is generated the POL turns off and the UV bit in the register ST is changed to 0 The output voltage is ramped down according to sequencing and tracking settings regular turn off 8 3 2 3 Overtemperature Protection Overtemperature protection is active whenever the POL is powered up If temperature of the controller exceeds 130 C the OT fault is generated POL turns off and the OT bit in the register ST is changed to The output voltage is ramped down according to sequencing and tracking settings regular turn off If non latching OTP is programmed the POL will restart as soon as the temperature of the controller decreases below the Overtemperature Warning threshold of 120 C Page 22 of 34 iO IB Put ZY7120 20A DC DC Intelligent POL Data Sheet 3V to 13 2V Input 0 5V to 5 5V Output POWEr ONne hanging the Shape of Power 8 3 2 4 Tracking Protection Tracking protection is active only when the output voltage is ramping up The purpose of the protection is to ensure that the voltage differential between multiple rails being tracked does not exceed 250mV This protection eliminates the need for external clamping diodes
30. e ZM7XXX Digital Power Manager Programming Manual e Z One Graphical User Interface e ZMO00056 KIT USB to I C Adapter Kit User Manual 1 Ordering Information _ x AJ y Jg Output voltage setpoint RoHS compliance Packaging Option Product Series Output accuracy No suffix ROHS T1 500pcs T amp R family Intelligent L 1 0 or 20mV compliant with Pb T2 100pcs T amp R Z One POL 20A whichever is greater solder exemption T3 50pcs T amp R 1 0 or 10mV G RoHS compliant Q1 1pc sample for whichever is greater for all six substances evaluation only Module Converter Contact factory for availability The solder exemption refers to all the restricted materials except lead in solder These materials are Cadmium Cd Hexavalent chromium Cr6 Mercury Hg Polybrominated biphenyls PBB Polybrominated diphenylethers PBDE and Lead Pb used anywhere except in solder Packaging option is used only for ordering and not included in the part number printed on the POL converter label The evaluation board is available in only one configuration ZM7300 KIT HKS Example ZY7120HG T2 A 100 piece reel of RoHS compliant POL converters with the output voltage setpoint of 1 0 or 10mV whichever is greater Each POL converter is labeled ZY7120HG 2 Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings may cause performance degradation
31. es Overtemperature Warning and Power Good Signal The warnings do not turn off POLs but rather generate signals that can be transmitted to a host controller via the I C bus 8 3 1 1 Overtemperature Warning The Overtemperature Warning is generated when temperature of the controller exceeds 120 C The Overtemperature Warning changes the PT bit of the status register ST to 0 and sends the signal to the DPM Reporting is enabled in the GUI Fault Management window or directly via the I C by writing into the PC3 register shown in Figure 43 When the temperature falls below 117 C the PT bit is cleared and the Overtemperature Warning is removed 8 3 1 2 Power Good Power Good is an open collector output that is pulled low if the output voltage is outside of the Power Good window The window is formed by the Power Good High threshold that is equal to 110 of the output voltage and the Power Good Low threshold that can be programmed at 90 or 95 of the output voltage The Power Good protection is only enabled after the output voltage reaches its steady state level The PGOOD pin is pulled low during transitions of the output voltage from one level to other as shown in Figure 42 The Power Good Warning pulls the Power Good pin low and changes the PG bit of the status register ST to O It sends the signal to the DPM if the reporting is enabled When the output voltage returns within the Power Good window the PG pin is pulled high the PG
32. ew Rate is Programmed at 0 5V ms Vinz12V Ch1 V1 Ch2 V2 Ch3 V3 REV 2 1 MAR 14 2007 WWW power one com Tek e 4 Trig i Chl High ere cd tsm team rient i rte de 2 050 V L i i i 1 860 V Ch3 High 1 520 V LEN TEES TER TL NRT HEM ICI SITIS NIST BT YO er UN TIE MT 1 chi 500 4 500mV 00ms rn chi f 220mV ie 500mV 812 00 Figure 12 Turn On with Different Rising Slew Rates Rising Slew Rates are Programmed as follows V1 1V ms V2 0 5V ms V3 0 2V ms Vin 12V Ch1 V1 Ch2 V2 Ch3 V3 Tek Run T Chl High LotR EEE Mtn teret 2 050 V oes EE IT m ied id i i Ch2 High i i i T i 1 850 V Ch3 High 1 520 V PEST AST PE TAAT EEE NEET BES re INL PEN PER E NY SA ECT TIET BIET BE TEEL HE PAA DAET PE DI AEN DEET TEA TAT BS TEE SCIRE MITT C a el TAE RE RT chi s00mv oy 500 00ms r chi f 220mv IE 500 12 00 Figure 13 Sequenced Turn On Rising Slew Rate is Programmed at 1V ms V2 Delay is 2ms V3 delay is 4ms Vinz12V Ch1 V1 Ch2 V2 Ch3 V3 Page 10 of 34 ZY7120 20A DC DC Intelligent POL Data Sheet PAN PUWEI fJe hanging the Shape of Power Tek Run i Chi High AEN SEE eee i IE 2 030V Ch2 High 1 850 V Ch3 High 1 520 V chi soomv HL Y So0mV eines Ooms chi ft 190mV
33. f POLs connected in parallel Figure 51 and Figure 52 show the output noise of two ZY7120s connected parallel without and with 180 interleave respectively Resulting noise reduction is more than 2 times and is equivalent to doubling switching frequency or adding extra capacitance on the output of the POLs Tek SP __jj ____________ Ch3 Pk Pk IUE NC chc o B TERES Gee i E 5 977mvV 4 n 4 4 b mi i uis X D a tnn WIE T MNT E 5 00mV 5 29 Sep 2004 12 119 40 12 47 22 Figure 51 Output Voltage Noise Full Load No Interleave REV 2 1 MAR 14 2007 www power one com Tek SP p i 1 Pk Pk MT UM E m Im aa ERR E 29 pores dn s dene ro J 9 684mV E i 3 f ps X Imi bt j iali P ill s M Ch3 RMS i E l 4 1 410mV SAT TEOT UST SAT OBI RT DENT TOSS PORT SAN Oe ENT TEN DN MT Ig SHIRE SERT NES Se PENE EE SE SEF TEET BOE PAEL Ye Sed NM EE E PONT EE Od LO TSO TEE M 400ns A Ch3 7 3 00mV ie 5 00 mV 5j 29 Sep 2004 9 19 40 12 46 13 Figure 52 Output Voltage Noise Full Load 180 I
34. f not used _ wo Pu SmeDsatne ComedtSDpnofDPM Not Used Leave floating 3e Tielo PGND tar o or leave noaio or Pu Tieto POND for 0 or leave foaina ort 1 Pu OLAMesbi2 Tieto PGND tor 0 or leave foaina tori 1 eu otAessski Tete PGND or 0 or leave foaina fort __ Pu Tie to POND Tor 0 or leave toatrg tori _ f st volage sense comet ea pom ose me Positive Voltage Sense Connect to the positive point close to the load omae fe wwo SOS o meme Legend l input O output l O2input output P power A analog PU internal pull up REV 2 1 MAR 14 2007 WWW power one com Page 16 of 34 ZY7120 20A DC DC Intelligent POL Data Sheet to 13 2V Input 0 5V to 5 5V Output POWET ONE hanging the Shape of Power 8 Programmable Features Performance parameters of ZY7120 POL converters can be programmed via the industry standard C communication bus without replacing components or rewiring PCB traces Each parameter has a default value stored in the volatile memory registers detailed in Table 1 The setup registers OOh through 14h are programmed at the system power up When the user programs new performance parameters the values in the registers are overwritten Upon removal of the input voltage the default values are restored Ta
35. f small signal oscillations It is recommended to always add a small amount of load regulation to one of the converters connected in parallel to reduce loop gain and therefore improve stability 8 6 Performance Parameters Monitoring The POL converters can monitor their own performance parameters such as output voltage output current and temperature REV 2 1 MAR 14 2007 www power one com The output voltage is measured at the output sense pins output current is measured using the ESR of the output inductor and temperature is measured by the thermal sensor built into the controller IC Output current readings are adjusted based on temperature readings to compensate for the change of ESR of the inductor with temperature An 8 Bit Analog to Digital Converter ADC converts the output voltage output current and temperature into a digital signal to be transmitted via the serial interface The ADC allows a minimum sampling frequency of 1 kHz for all three values Monitored parameters are stored in registers VOM IOM and TMON that are continuously updated If the Retrieve Monitoring bits in the GUI Group Configuration window shown in Figure 56 are checked those registers are being copied into the ring buffer located in the DPM Contents of the ring buffer can be displayed in the GUI IBS Monitoring Window shown in Figure 57 or it can be read directly via the I C bus using high and low level commands as described in the D
36. ge Protection n Value at POR reset Level 00 110 of Vo 01 120 of Vo 10 130 of Vo Default 11 130 of Vo Bit 1 0 UVPL 1 0 Set Under Voltage Protection Level 00 75 of Vo Default 01 80 of Vo 10 85 of Vo Figure 39 Protection Configuration Register PC2 Note that the overvoltage and undervoltage protection thresholds and Power Good limits are defined as percentages of the output voltage Therefore the absolute levels of the thresholds change when the output voltage setpoint is changed either by output voltage adjustment or by margining In addition a user can change type of protections latching non latching or disable certain protections These settings are programmed in the GUI Fault Management window shown in Figure 40 or directly via the ge by writing into the PC1 register shown in Figure 41 REV 2 1 MAR 14 2007 WWW power one com POL Fault Management Address 07 IE Propagate Apply To POL Latching Enable Apply To Group Trigger Severity Tracking Differential Fault Apply To Board Over Temperature Fault Over Current Fault Under Voltage Fault Over Voltage Error Phase Error Figure 40 Fault Management Window R W 0 R W 1 R W 0 R W 0 R W 0 R W 0 R W 1 R W 1 TRE PVE TRP OTP OCP UVP OVP PVP Bit 7 Bit 0 Bit 7 TRE Tracking fault enable R Readable bit enabled W Writable bit 0 disabled U Unimplemented bit Bit6 PVE Pha
37. he margining can be programmed in the GU Output Configuration window or directly via the IC bus using high level commands as described in the DPM Programming Manual In order to properly margin POLs that are connected in parallel the POLs must be members of one of the Parallel Buses Refer to the GUI System Configuration Window shown in Figure 55 8 1 3 Optimal Voltage Positioning Optimal voltage positioning increases the voltage regulation window by properly positioning the output voltage setpoint Positioning is determined by the load regulation that can be programmed in the GUI Output Configuration window shown in Figure 27 or directly via the C bus by writing into the CLS register shown in Figure 38 Figure 29 illustrates optimal voltage positioning concept If no load regulation is programmed the headroom voltage differential between the output voltage setpoint and regulation limit is approximately half of the voltage regulation window When load regulation is programmed the output voltage will decrease as the output current increases so the VI characteristic will have a negative slope Therefore by properly selecting the operating point it is possible to increase the headroom as shown in the picture REV 2 1 MAR 14 2007 www power one com Increased headroom allows tolerating larger voltage deviations For example the step load change from light to heavy load will cause the output voltage to drop If
38. imes the value of the fuse without opening The fuse must not be placed in the grounded input line Abnormal and component failure tests were conducted with the POL input protected by a fast acting 65 V 15 A fuse If a fuse rated greater than 05 Monitoring Programming Status 15 A is used additional testing may be required In order for the output of the ZY7120 POL converter to be considered as SELV Safety Extra Low Voltage according to all lIEC60950 based standards the input to the POL needs to be supplied by an isolated secondary source providing a SELV also SEL 00 01 02 05 04 05 06 07 0S 09 10 11 12 13 14 15 16 17 19 19 20 2122 23 24 25 26 27 28 29 30 31 CRC Status Information Group Pre warning Temp Power Good Tracking Over Temperature Over Current Under Voltage Over voltage Phase voltage IBY Low Aux Devices M jp oo oo Yoltage V Current A Temp C Device All Signals amp Events FE Enable Crow Bar IBY High RES Min Monitoring FAIL in Status Data INO input Parametric Data IM1 input Interfaces INe input sp H c IMS input IBY Voltage IBV 12 24 V Run Time Counter 0 3h Commands Pending Front End Group B Group C Group D Figure 57 IBS Monitoring Window REV 2 1 MAR 14 2007 WWW power one com Page 32 of 34 ZY7120 20A DC DC Intelligent POL Data Sheet SN 3V to 13 2V Input 0 5V t
39. lly transforms zero pole frequencies into the digital filter coefficients It is strongly recommended to use the GUI to determine the filter coefficients Programming feedback loop compensation allows optimizing POL performance for various application conditions For example increase in bandwidth can significantly improve dynamic response 8 5 Current Share The POL converters are equipped with the digital current share function To activate the current share interconnect the CS pins of the POLs connected in parallel The digital signal transmitted over the CS Page 28 of 34 ZY7120 20A DC DC Intelligent POL Data Sheet 3V to 13 2V Input 0 5V to 5 5V Output POWEr oNne hanging the Shape of Power line sets output currents of all POLs to the same level When POLs are connected in parallel they must be included in the same parallel bus in the GUI System Configuration window shown in Figure 55 In this case the GUI automatically copies parameters of one POL onto all POLs connected to the parallel bus It makes it impossible to configure different performance parameters for POLs connected in parallel except for interleave and load regulation settings that are independent The interleave allows to reduce and move the output noise of the converters connected parallel to higher frequencies as shown in Figure 51 and Figure 52 The load regulation allows controlling the current share loop gain in case o
40. mp down time is included in the turn off delay as shown in Figure 35 User programmed turn off delay Top Turn Off Command Calculated Internal delay Tp Ramp down time ramp down command Vour Falling slew ratedV dT Time Figure 35 Relationship between Turn Off Delay and Falling Slew Rate As it can be seen from the figure the internally calculated delay Tp is determined by the equation below _ Ig Tor d V uL For proper operation Tp shall be greater than zero The appropriate value of the turn off delay needs to be programmed to satisfy the condition Page 19 of 34 ZY7120 20A DC DC Intelligent POL Data Sheet 3V to 13 2V Input 0 5V to 5 5V Output POWEr ONne hanging the Shape of Power If the falling slew rate control is not utilized the turn off delay only determines an interval from the application of the Turn Off command until both high side and low side switches are turned off In this case the output voltage ramp down process is determined by load parameters 8 2 3 Rising and Falling Slew Rates The output voltage tracking is accomplished by programming the rising and falling slew rates of the output voltage To achieve programmed slew rates the output voltage is being changed in 12 5mV steps where duration of each step determines the slew rate For example ramping up a 1 0V
41. nterleave The ZY7120 interleave feature is similar to that of multiphase converters however unlike in the case of multiphase converters interleave does not have to be equal to 360 N where N is the number of POLs in a system ZY7120 interleave is independent of the number of POLs in a system and is fully programmable in 11 25 steps It allows maximum output noise reduction by intelligently spreading switching energy 8 4 3 Duty Cycle Limit The ZY7120 is a step down converter therefore Vou is always less than Vw The relationship between the two parameters is characterized by the duty cycle and can be estimated from the following equation Your Vin MIN Where DC is the duty cycle Vout is the required maximum output voltage including margining S the minimum input voltage It is good practice to limit the maximum duty cycle of the PWM controller to a somewhat higher value compared to the steady state duty cycle as expressed by the above equation This will further protect the output from excessive voltages The duty cycle limit can be programmed in the GU PWM Controller window or directly via the C bus by writing into the DCL register shown in Figure 53 Page 27 of 34 ZY7120 20A DC DC Intelligent POL Data Sheet 3V to 13 2V Input 0 5V to 5 5V Output POWEr ONne hanging the Shape of Power R W 1 R W 1 R W 1 R W 0 R W 1 R W 0 R W 0 R W 0 Bit 7 Bit 0 R Read
42. o 5 5V Output POWES OM hanging the Shape of Power 10 Mechanical Drawings All Dimensions are in mm Tolerances 0 5 10 0 1 10 100 0 2 Pin Coplanarity 0 1 max 10 SMT Pickup Tab O la anl 0 0 H ojo foo E B a _ _ din E L 4440 3 13 4 300 a 0 000 gj Lr LH L In C 0 6 1 27 0 4 1 27 x10 x20 d x10 DS 27 94 32 0 3 Tilt Specification lt 5 from vertical 9 75 12 10 25 after assembly 12 9 1 3 5 3 25 Pin 1 15 75 SMT Pickup Center Point Figure 58 Mechanical Drawing LA E 25 24 2 EM __ J s Figure 59 Pinout Diagram Bottom View REV 2 1 MAR 14 2007 WWW power one com Page
43. output with a slew rate of 0 5V ms will require 80 steps duration of 25yus each Duration of each voltage step is calculated by dividing the master clock frequency generated by the DPM Since all POLs in the system are synchronized to the master clock the matching of voltage slew rates of different outputs is very accurate as it can be seen in Figure 11 and Figure 16 During the turn on process a POL not only delivers current required by the load 1 but also charges the load capacitance The charging current can be determined from the equation below av Croan X Where Cioap is load capacitance dVyg dt is rising voltage slew rate and is charging current When selecting the rising slew rate a user needs to ensure that long loce Where locp is the overcurrent protection threshold of the ZY7120 f the condition is not met then the overcurrent protection will be triggered during the turn on process To avoid this dVg dt and the overcurrent protection threshold should be programmed to meet the condition above REV 2 1 MAR 14 2007 www power one com R W 0 RA 0 R W 0 R W 1 R W 0 0 R W 0 Bit 7 Bit O Bit7 Unimplemented read as 0 Bit 6 4 R 2 0 Value of Vo rising slope corresponds to 0 1V ms default corresponds to 0 2V ms corresponds to 0 5V ms corresponds to 1 0V ms corresponds to 2 0V ms corresponds to 5 0V ms corre
44. p Next On Off Turn on off delay Slew Rates Turn Off gt 0 ms Rising 0 5 V ms O without slew rate control la gt 10 ms Falling 0 5 V ms 9 active discharge slew rate controlled Figure 32 Sequencing Tracking Window 8 2 1 Turn On Delay Turn on delay is defined as an interval from the application of the Turn On command until the output voltage starts ramping up REV 2 1 MAR 14 2007 www power one com R W 0 R W 0 R WwW 0 R W 0 R W 0O R W 0 R W 0 R W 0 Bit 7 Bit 0 Bit 7 0 DON 7 0 Turn on delay time 00h corresponds to Oms delay after turn on command has occurred FFh corresponds to 255ms delay after turn on command has occurred Figure 33 Turn On Delay Register DON 8 2 2 Turn Off Delay R W 0 R W 0 RAW 0 R W 0 R W 0 R W 0 sors bors sors Bit 7 Bit O Bit 7 6 Unimplemented read as 0 Bit 5 0 DOF 5 0 Turn off delay time 00h corresponds to Oms delay after turn off command has occurred 3Fh corresponds to 63ms delay after turn off command has occurred Figure 34 Turn Off Delay Register DOF Turn off delay is defined as an interval from the application of the Turn Off command until the output voltage reaches zero if the falling slew rate is programmed or until both high side and low side switches are turned off if the slew rate is not programmed Therefore for the slew rate controlled turn off the ra
45. reaches its steady state level VN Nb 4 a y 130ms is the interval from the instant of time when aliae maps down D ntl ine url ak ae ee output voltage starts to ramp up again Therefore Bound C 5 Ade d 4 the 130ms hiccup interval is guaranteed regardless EQ MEE NE E of the turn off delay S etting SRL S ie STE TA s ES i 500mV 29 Sep 2004 Tek stop i 2 110 40 12 28 58 anaes E Dm TAS DU Figure 46 Turn On into UVP on V3 The UV Fault Is panes Programmed To Be Non Latching and Propagate da m From Group C to Group A Ch1 V3 Group C Ch2 V2 Ch3 V1 Group Max CEES M bane mani 1 2 120V Summary of protections their parameters and 13 i BEER i o M 35 features are shown Table 3 Ch2 Max ME TU i L4 4 293V ZEE NE 1 Max lt ETT a n 4 Ch3 500mV 29 Sep 2004 15 110 40 12 30 04 Figure 45 Turn On into UVP on V3 The UV Fault Is Programmed To Be Non Latching Ch1 V3 Group C Ch2 V2 Ch3 V1 Group A Table 3 Summary of Protections Parameters and Features Type When Active Turn Low Side Propagation Disable Off Switch PT Tempera
46. se voltage error enable read as 0 1 enabled Value at POR reset 0 disabled Bit5 Tracking fault protection 1 latching 0 non latching Bit4 Overtemperature protection configuration 1 latching 0 non latching Bit3 Overcurrent protection configuration 1 latching 0 non latching Bit2 UVP Undervoltage protection configuration 1 latching 0 non latching Bit1 OVP Overvoltage protection configuration 1 latching 0 non latching BitO PVP Phase Voltage Protection 1 latching 0 non latching Figure 41 Protection Configuration Register PC1 If the non latching protection is selected a POL will attempt to restart every 130ms until the condition that triggered the protection is removed When restarting the output voltages follow tracking and sequencing settings If the latching type is selected a POL will turn off and stay off The POL can be turned on after 130ms if the condition that caused the fault is removed and the respective bit in the ST register was cleared or the Turn On command was recycled or the input voltage was recycled Page 21 of 34 ZY7120 20A DC DC Intelligent POL Data Sheet 3V to 13 2V Input 0 5V to 5 5V Output POWEr ONne hanging the Shape of Power All protections can be classified into three groups based on their effect on system operation warnings faults and errors 8 3 1 Warnings This group includ
47. sponds to 8 3V ms corresponds to 8 3V ms R Readable bit W Writable bit U Unimplemented bit read as 0 Value at POR reset NOOR WN Bit 3 SC Slew rate control at turn off 0 Slew rate control is disabled 1 Slew rate control is enabled Bit 2 0 F 2 0 Value of Vo falling slope corresponds to 0 1V ms default corresponds to 0 2V ms corresponds to 0 5V ms corresponds to 1 0V ms corresponds to 2 0V ms corresponds to 5 0V ms corresponds to 8 3V ms corresponds to 8 3V ms NOOR WN Figure 36 Tracking Configuration Register TC 8 3 Protections ZYT120 Series converters have a comprehensive set of programmable protections The set includes the output over and undervoltage protections overcurrent protection overtemperature protection tracking protection overtemperature warning and Power Good signal Status of protections is stored in the ST register shown in Figure 37 R 1 0 R 1 R 1 R 1 R 1 R 1 R 1 TP PG TR OT OC UV OV PV Bit 7 Bit 0 Bit7 Temperature Warning R Readable bit Bit6 Power Good Warning W Writable bit U Unimplemented bit read as 0 n Value at POR reset Bit5 Tracking Fault Bit4 Overtemperature Fault Bit3 Overcurrent Fault Bit2 UV Undervoltage Fault Bit 1 OV Overvoltage Error BitO Phase Voltage Error Note An activated warning fault error is encoded as
48. switching frequency 0 5 1 0MHz Programmable turn on and turn off delays Programmable turn on and turn off voltage slew rates with tracking protection Programmable feedback loop compensation Power Good signal with programmable limits Programmable fault management Start up into the load pre biased up to 100 Full rated current sink Real time voltage current and temperature measurements monitoring and reporting Small footprint SMT package 8x32mm Low profile of 14mm Compatible with conventional pick and place equipment Wide operating temperature range UL60950 recognized CSA C22 2 No 60950 00 certified and TUV EN60950 1 2001 certified The ZY7120 is an intelligent fully programmable step down point of load DC DC module integrating digital power conversion and intelligent power management When used with ZM7000 Series Digital Power Managers the ZY7120 completely eliminates the need for external components for sequencing tracking protection monitoring and reporting All parameters of the ZY7120 are programmable via the industry standard C communication bus and can be changed by a user at any time during product development and service REV 2 1 MAR 14 2007 WWW power one com Page 1 of 34 x 0 IB Aai ZY7120 20A DC DC Intelligent POL Data Sheet 3V to 13 2V Input 0 5V to 5 5V Output POWET ONE hanging the Shape of Power Reference Documents e ZM7XXX Digital Power Manager Data Sheet
49. t Propagate Auto Restart Propagate Auto Restart Propagate Disabled Address Select 2 50V 0 0 mV A 6 25 7 3 3 V 2 23 V 1 9 V O ms 0 5 V ms 25 ms 0 1 Vims 500 kHz i Figure 56 POL Group Configuration Window 9 Safety The ZY7120 POL converters do not provide isolation from input to output The input devices powering ZY7120 must provide relevant isolation requirements according to all IEC60950 based standards Nevertheless if the system using the converter needs to receive safety agency approval certain rules must be followed in the design of the system In particular all of the creepage and clearance requirements of the end use safety REV 2 1 MAR 14 2007 WWW power one com Page 31 of 34 requirements must be observed These requirements are included in UL60950 CSA60950 00 and EN60950 although specific applications may have other or additional requirements The ZY7120 POL converters have no internal fuse If required the external fuse needs to be provided to protect the converter from catastrophic failure Refer to the Input Fuse Selection for DC DC converters application note on www power one com for proper selection of the input fuse Both input traces and the ZY7120 20A DC DC Intelligent POL Data Sheet 3V to 13 2V Input 0 5V to 5 5V Output la POWET ONE hanging the Shape of Power chassis ground trace if applicable must be capable of conducting a current of 1 5 t
50. ta Sheet 3V to 13 2V Input 0 5V to 5 5V Output POWET ONE hanging the Shape of Power Vout 5 5 5 0 4 5 4 0 3 5 3 0 2 5 2 0 1 5 1 0 0 5 20 40 6 0 8 0 10 0 12 0 140 30 3 15 55 6225 13 2 Figure 1 Output Voltage as a Function of Input Voltage and Output Current 4 3 Protection Specifications Parameter Conditions Description Min Nom Max Units Output Overcurrent Protection Default Non Latching 130ms period Programmable Latching Non Latching Default 140 lout Programmable in 11 steps 140 lout Type Threshold 25 JolocP sET C i Threshold Accuracy Output Overvoltage Protection Default Non Latching 130ms period Programmable Latching Non Latching Default 130 Vo SET Programmable in 10 steps Jo VOo sET Threshold Accuracy Measured at Vo set 2 5V Dela From instant when threshold is exceeded until the turn off command is generated I N REV 2 1 MAR 14 2007 WWW power one com ZY7120 20A DC DC Intelligent POL Data Sheet 3V to 13 2V Input 0 5V to 5 5V Output POWET ONE hanging the Shape of Power Output Undervoltage Protection Default Non Latching 130ms period yp Programmable Latching Non Latching Default 75 Threshold Accuracy Measured at Vo set 2 5V Oa f Jo V UVP SET Dela From instant when threshold is exceeded until the turn off command is generated
51. the optimal voltage positioning is utilized the output voltage will stay within the regulation window Otherwise the output voltage will drop below the lower regulation limit To compensate for the voltage drop external output capacitance will need to be added thus increasing cost and complexity of the system The effect of optimal voltage positioning is shown in Figure 30 and Figure 31 In this case switching output load causes large peak to peak deviation of the output voltage By programming load regulation the peak to peak deviation is dramatically reduced Tek Stop Ch1 94 2mV 17 May 2004 19 80 09 34 36 Figure 30 Transient Response without Optimal Voltage Positioning Page 18 of 34 ZY7120 20A DC DC Intelligent POL Data Sheet 3V to 13 2V Input 0 5V to 5 5V Output hanging the Shape of Power Tek Stop Chl Pk Pk 57 6mV ST EECA Ce TPA 17 May 2004 1919 80 09 34 00 Figure 31 Transient Response with Optimal Voltage Positioning 8 2 Sequencing and Tracking Turn on delay turn off delay and rising and falling output voltage slew rates can be programmed in the GUI Sequencing Tracking window shown in Figure 32 or directly via the I C bus by writing into the DON DOF and TC registers respectively The registers are shown in Figure 33 Figure 34 and Figure 36 Sequencing Tracking Address 02 Apply Grou
52. tput V3 Ch 1 in the picture encounters the undervoltage fault after the turn on When the fault propagation is not enabled the POL turns off and generates the UV fault signal Because the UV fault triggers the regular turn off the POL meets its turn off delay and falling slew rate settings during the turn ff process as shown in Figure 45 Since the UV fault is programmed to be non latching the POL will attempt to restart every 130ms repeating the process described above until the condition causing the undervoltage is removed If the fault propagation between groups is enabled the POL powering the output V3 pulls its OK line low and the DPM propagates the signal to the POL powering the output V1 that belongs to other group Page 24 of 34 Overvoltage Error When Vour exceeds prebias Fast ZY7120 20A DC DC Intelligent POL Data Sheet SN 3V to 13 2V Input 0 5V to 5 5V Output POWES ONC hanging the Shape of Power The POL powering the output V1 Ch3 in the picture executes the regular turn off Since both V1 and V3 qc SIUE have the same delay and slew rate settings they will a com continue to turn off and on synchronously every 130ms as shown in Figure 46 until the condition causing the undervoltage is removed The POL um Le 3 120 V TE 14 21 powering the output V2 continues to ramp up until it fF dmM rebeeee een a 2 Max
53. ture Warning Whenever Vin is applied NO N A Sends signal to NO Warning E DPM Tracking Fault During ramp up Fast Regular turn off Overtemperature Whenever Vin is or Regular turn off Regular turn off Undervoltage During steady state Regular turn off On Fast turn off REV 2 1 MAR 14 2007 WWW power one com Page 25 of 34 ZY7120 20A DC DC Intelligent POL Data Sheet 3V to 13 2V Input 0 5V to 5 5V Output POWET ONE hanging the Shape of Power 8 4 PWM Parameters Z Series POLs utilize the digital PWM controller The controller enables users to program most of the PWM performance parameters such as switching frequency interleave duty cycle and feedback loop compensation 8 4 1 Switching Frequency The switching frequency can be programmed in the GUI PWM Controller window shown in Figure 47 or directly via the bus by writing into the INT register shown in Figure 48 Note that the content of the register can be changed only when the POL is turned off Switching actions of all POLS connected to the SD line are synchronized to the master clock generated by the DPM Each POL is equipped with a PLL and a frequency divider so they can operate at multiples including fractional of the master clock frequency as programmed by a user The POL converters can operate at 500 kHz 750 kHz and 1 MHz Although synchronized switching frequencies of different POLs are independent of each
54. uts ADDRO ADDR4 EN IM owane _ 95 v _ Vx MOMiwimuwae orav voos V _ O me ites fir Senmewoger o1xvoo v _ omues e 0 0 wp PS Puttupcurent source nputtorcedtow PG 2 mo m _ ok PMapcwensuemwtesiwOK _ _ VOS V _ hysteresis Sont wager v _ tOWmesormao m m Current Share Bus CS pin ws Pahupawentsouceatvos ov om 9 m wes iOWeweiuvixe os V _ ViH_CS HIGH level input voltage pid VDD 0 5 Vhyst_CS Hysteresis of input Schmitt trigger ed EE pud Maximum allowed rise time 10 90 VDD 100 ns REV 2 1 MAR 14 2007 WWW power one com Page 7 of 34 ZY7120 20A DC DC Intelligent POL Data Sheet 72 3V to 13 2V Input 0 5V to 5 5V Output POWES ONC hanging the Shape of Power 5 Typical Performance Characteristics os 94 5 1 Efficiency Curves 92 92 86 90 se 84 88 9 82 86 80 gt 78 37 76 2 82 74 80 72 78 70 Vout 1 2V Vout 2 5V 68 74 Vout 0 5V 1 2V Vout 2 5V 0 2 4
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POWER ONE ZY7120 20A DC DC Intelligent POL handbook