National Semiconductor DAC0830/DAC0832 8-Bit P Compatible Double-Buffered D to A Converters handbook
Contents
1. z S E Fe z w 0 025 AGAIN ERROR 5 0 050 Vec 15V Vaer 5V OR 12V Vaer 2 5V ers Vec REF 0 100 55 35 15 5 25 45 65 85 105 125 Ta AMBIENT TEMPERATURE C Ds00s608 34 FIGURE 18 2 8 Miscellaneous Application Hints These converters are CMOS products and reasonable care should be exercised in handling them to prevent catastrophic failures due to static discharge Conversion accuracy is only as good as the applied refer ence voltage so providing a stable source over time and tem perature changes is an important factor to consider A good ground is most desirable A single point ground dis tribution technique for analog signals and supply returns keeps other devices in a system from affecting the output of the DACs During power up supply voltage sequencing the 15V or 12V supply of the op amp may appear first This will cause the output of the op amp to bias near the negative supply po tential No harm is done to the DAC however as the on chip 15 KQ feedback resistor sufficiently limits the current flow from lour when this lead is internally clamped to one diode drop below ground Careful circuit construction with minimization of lead lengths around the analog circuitry is a primary concern Good high frequency supply decoupling will aid in preventing inadvert ant noise from appearing on the analog output Overall noise reduction and referenc2. VreFl THESE RESISTORS ARE AVAILABLE FROM BECKMAN INSTRUMENTS INC AS THEIR PART NO 694 3 R10K D FIGURE 9 2 6 Full Scale Adjustment resistors their temperature coefficients ideally would have to match that of the internal DAC resistors which is a highly im practical constraint For the values shown in Figure 10 if the resistor and the potentiometer each had a temperature coef ficient of 100 ppm C maximum the overall gain error tem perature coefficent would be degraded a maximum of 0 0025 C for an adjustment pot setting of less than 3 of Rio In the case where the matching of Rp to the R value of the R 2R ladder typically 0 2 is insufficient for full scale ac curacy in a particular application the Vper voltage can be adjusted or an external resistor and potentiometer can be added as shown in Figure 10 to provide a full scale adjust ment The temperature coefficients of the resistors used for this ad justment are of an important concern To prevent degrada tion of the gain error temperature coefficient by the external 13 www national com This Material Copyrighted By Its Respective Manufacturer DAC0830 Series Application Hints Continued 2 7 Using the DAC0830 in a Voltage Switching Configuration The R 2R ladder can also be operated as a voltage switch ing network In this mode the ladder is used in an inverted manner from the standard current switching configuration DIGITAL INPUT VREF DAC
3. 0 508 RAD TYP 0 037 0 005 0 940 0 127 0 005 0 055 0 005 180 asa 0 290 0 320 4 397 0 127 oan ica Na 7 366 GLASS SEALANT 0 508 1 524 86 94 0 008 0 012 0 203 0 305 a 0 310 0 410 on 0 060 0 018 0 003 7 874 10 41 1 524 0 457 0 076 MAX BOTH ENDS 0 190 0 010 2 540 0 254 A 0 0 125 0 200 MIN 3 175 5 080 J20A REV M Ceramic Dual In Line Package J Order Number DACO830LCuJ DAC0830LJ DACO832LJ or DACO832LCJ NS Package Number J20A www national com 22 This Material Copyrighted By Its Respective Manufacturer Physical Dimensions inches millimeters unless otherwise noted Continued a 0 495 0 512 12 598 13 005 30 TYP LEAD NO 1 4 i IDENT A woo z 0 010 MAX 0 254 B MAX TYP 0 004 0 012 ALL i 4 0 102 0 305 0 201 0 209 39 7 595 0 010 0 029 0 093 0 104 0 254 0 737 ea aa SEATING 0 009 0 013 cB pe 0 014 9 060 0 229 0 330 0 102 ee joss fe 2 060 a 0 014 0 020 ryp ALL LEAD TIPS 0 406 1 270 aE si 0 256 0 508 TYP ALL LEADS on ALL lene t J 0 008 typ 0 203 aaa REV P Molded Small Outline Package M Order Number DACO830LCM or DAC0832LCM NS Package Number M20B 1 013 1 040 0 092 x 0 030 25 73 26 42 2 337 X 0 762 0 032 0 005 MAX DP 0 813 0 127 Bel e RAD PIN
4. lo rC where C1 C2 G K Re and A R of DAC 15k 5 Ho 1for Ry Ry Ry e Range of f and Q is 7 16 to 1 for circuit shown The range can be extended to 255 to 1 by replacing R with a second DAC0830 driven by the same digital input word Maximum fox Q product should be 200 kHz 18 www national com By Its Respective Manufacturer This Material Copyrighted Applications continued DAC Controlled Function Generator 15 AMPLITUDE 15V 75k A 25k SINE WAVE UTPUT symmetry TRIM 15V WAVESHAPE TRIM 100 uF Qha 5 TRI N TRI WAVE 2k 15 99 DACOBI0 15 GNO GND LE 15 SQUARE WAVE OUTPUT DS005608 18 DAG controls the frequency of sine square and triangle outputs D f Z56200 for Vomax Yomin of square wave output and Ry 3 R 255 to 1 linear frequency range oscillator stops with D 0 Trim symmetry and wave shape for minimum sine wave distortion 19 www national com This Material Copyrighted By Its Respective Manufacturer Applications continued Two Terminal Floating 4 to 20 mA Current Loop Controller INPUT N4001 500Q i MA lt tout lt 20 mA DS005608 19 lout VREF z 256 xen 1 f DAC0830 linearly controls the current flow from the input terminal to the output terminal to be 4 mA for D 0 to 19 94 mA for D 255 Circuit operates with a terminal voltage differential of 16V to 55V Pz adjusts the magnitude
5. with the DAC1230 a 12 bit MICRO DAG In the event that a system s analog out put resolution and accuracy must be upgraded substituting the DAC1230 can be easily accomplished By tying address bit Ao to the ILE pin a two byte uP write instruction double precision which automatically increments the address for the second byte write starting with Ap 1 can be used This allows either an 8 bit or the 12 bit part to be used with no hardware or software changes For the simplest 8 bit ap plication this pin should be tied to Vgc also see other uses in section 1 1 Analog signal control versatility is provided by a precision R 2R ladder network which allows full 4 quadrant multiplica tion of a wide range bipolar reference voltage by an applied digital word 1 0 DIGITAL CONSIDERATIONS A most unique characteristic of these DAC s is that the 8 bit digital input byte is double buffered This means that the data must transfer through two independently controlled 8 bit latching registers before being applied to the R 2R ladder network to change the analog output The addition of a sec ond register allows two useful control features First any DAC in a system can simultaneously hold the current DAC data in one register DAC register and the next data word in the second register input register to allow fast updating of the DAC output on demand Second and probably more im portant double buffering allows any number of DAC s in a
6. 0 51 9 9140 13 0 10540 015 2 6720 38 0 165 0 180 typ 4 19 4 57 A 9 004 0 10 TYP V20A REY L Molded Chip Carrier V Order Number DAC0830LCV or DAC0832LCV NS Package Number V20A NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor National Semiconductor Corporation Europe Americas Fax 49 0 1 80 530 85 86 Tel 1 800 272 9959 Email europe support nsc com Fax 1 800 737 7018 Deutsch Tel 49 0 1 80 530 85 85 Email support nsc com English Tel 49 0 1 80 532 78 32 Frangais Tel 49 0 1 80 532 93 58 www national com Italiano Tel 49 0 1 80 534 16 80 National Semiconductor National Semiconductor Asia Pacific Customer Japan Ltd Response Group Tel 81 3 5639 7560 Tel 65 2544466 Fax 81 3 5639 7507 Fax 65 2504466 Email sea support nsc com National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specification
7. DAC from 15V to 5V offers a factor of 5 improvement in the magnitude of the feedthrough but at the expense of internal logic switching speed Finally increasing Co Figure 8 toa value consistent with the actual circuit bandwidth require ments can provide a substantial damping effect on any out put spikes This Material Copyrighted www national com By Its Respective Manufacturer DAC0830 Series Application Hints continued DATA BUS SYSTEM WRITE STROBE SYSTEM WRITE STROBE 250 ns NORMAL WRITE STROBE gt l DACOB30 i WR DATA BUS DATA VALID gt _ j SYSTEM DATA HOLD TIME lt 10ns ONE WAIT STATE 250 ns WR OUTPUT OF ONE SHOT DAC WR PULSE WIDTH 350 ns Ei DAC DATA HOLD TIME 160 ns D8005608 8 FIGURE 5 Accommodating a High Speed System 2 0 ANALOG CONSIDERATIONS The fundamental purpose of any D to A converter is to pro vide an accurate analog output quantity which is representa tive of the applied digital word In the case of the DACO830 the output louri is a current directly proportional to the product of the applied reference voltage and the digital input word For application versatility a second output lour2 is provided as a current directly proportional to the complement of the digital input Basically _ Vrer Digital Input Ous enn A pee 15 ka 256 io VREE 265 Digital Input OUT 15 ka 256
8. Figure 3 Itis important to note that the analog outputs that will change after a simultaneous transfer are those from the DAC s whose input register had been modified prior to the XFER command This Material Copyrighted www national com By Its Respective Manufacturer DAC0830 Series Application Hints continued CS XFER ADDRESS BUS SYSTEM DAC DISABLE SYSTEM WR STROBE TIE TO LOGIC 1 IF NOT NEEDED SEE SEC 1 1 WR2 ANALOG OUTPUT 1 ANALOG OUTPUT 2 ANALOG OUTPUT n DS005608 35 FIGURE 2 Controlling Mutiple DACs DATA BUS a E has INPUT LATCH Hr OUTPUT A7 DAC REGISTER LATCHED IFE gt iLE LOGIC 17 DS005608 36 FIGURE 3 The ILE pin is an active high chip select which can be de coded from the address bus as a qualifier for the normal CS signal generated during a write operation This can be used to provide a higher degree of decoding unique control sig nals for a particular DAC and thereby create a more efficient addressing scheme Another useful application of the ILE pin of each DAC ina multiple DAC system is to tie these inputs together and use this as a control line that can effectively freeze the outputs of all the DAC s at their present value Pulling this line low latches the input register and prevents new data from being written to the DAC This can be particularly useful in multi processing systems to all
9. Figure 4 Single buffering in a stand alone system is achieved by strobing WR low to update the DAC with CS WR3 and XFER grounded and ILE tied high 1 3 Flow Through Operation Though primarily designed to provide microprocessor inter face compatibility the MICRO DAC s can easily be config ured to allow the analog output to continuously reflect the state of an applied digital input This is most useful in appli cations where the DAC is used in a continuous feedback control loop and is driven by a binary up down counter or in function generation circuits where a ROM is continuously providing DAC data Simply grounding CS WR WR2 and XFER and tying ILE high allows both internal registers to follow the applied digital inputs flow through and directly affect the DAC analog out put 1 4 Control Signal Timing When interfacing these MICRO DAC to any microprocessor there are two important time relationships that must be con sidered to insure proper operation The first is the minimum WR strobe pulse width which is specified as 900 ns for all valid operating conditions of supply voltage and ambient temperature but typically a pulse width of only 180ns is ad equate if Veg 15Vpc A second consideration is that the guaranteed minimum data hold time of 50ns should be met or erroneous data can be latched This hold time is defined as the length of time data must be held valid on the digital in puts after a qualified
10. of the output current and P adjusts the zero to full scale range of output current Digital inputs can be supplied from a processor using opto isolators on each input or the DAC latches can flow through con nect control lines to pins 3 and 10 of the DAC and the input data can be set by SPST toggle switches to ground pins 3 and 10 www national com 20 This Material Copyrighted By Its Respective Manufacturer Applications continued DAC Controlled Exponential Time Response VINITIAL ar D TO DANDE 255 V pgg VOUT VIN 35g IN Ds005608 20 Output responds exponentially to input changes and automatically stops when Vour Vin Output time constant is directly proportional to the DAC input code and capacitor C Input voltage must be positive See section 2 7 Ordering Information 0 C to 70 40 C to 85 C 0 05 DACO830LCN DACO0830LCM DACO830LCV DAC0830LCJ 0 1 DAC0831LCN a aie 0 2 DACO0832LCN DAC0832LCM DACO0832LCV DAC0832LCJ E dee eld eee ll eee Ieee Package Outline N20A Molded M20B Small V20A Chip Carrier J20A Ceramic DIP Temperature Range DACO0830LJ Non Linearity DAC0832LJ 21 www national com This Material Copyrighted By Its Respective Manufacturer Physical DimenSiONS inches millimeters unless otherwise noted 0 985 0 025 25 019 0 635 RAD T 0 220 0 310 5 588 7 874 6 005 0 020 r 0 127
11. via CS WR strobe makes a low to high transition to latch the applied data If the controlling device or system does not inherently meet these timing specs the DAC can be treated as a slow memory or peripheral and utilize a technique to extend the write strobe A simple extension of the write time by adding a wait state can simultaneously hold the write strobe active and data valid on the bus to satisfy the minimum WR pulse width If this does not provide a sufficient data hold time at the end of the write cycle a negative edge triggered one shot can be included between the system write strobe and the WR pin of the DAC This is illustrated in Figure 5 for an exemplary system which provides a 250ns WR strobe time with a data hold time of less than 10ns The proper data set up time prior to the latching edge LO to HI transition of the WR strobe is insured if the WR pulse width is within spec and the data is valid on the bus for the duration of the DAC WR strobe 1 5 Digital Signal Feedthrough When data is latched in the internal registers but the digital inputs are changing state a narrow spike of current may flow out of the current output terminals This spike is caused by the rapid switching of internal logic gates that are responding to the input changes There are several recommendations to minimize this effect When latching data in the DAC always use the input register as the latch Second reducing the Vec supply for the
12. 5 ppm C resistance track ing temperature coefficient Two of the four available 10 kQ resistors can be paralleled to form R in Figure 9 and the other two can be used independenily as the resistances la beled 2R 2 5 Zero Adjustment For accurate conversions the input offset voltage of the out put amplifier must always be nulled Amplifier offset errors create an overall degradation of DAC linearity The fundamental purpose of zeroing is to make the voltage appearing at the DAC outputs as near OVpc as possible This is accomplished for the typical DAC op amp connec tion Figure 7 by shorting out Re the amplifier feedback re sistor and adjusting the Vog nulling potentiometer of the op amp until the output reads zero volts This is done of course with an applied digital code of all zeros if lour is driving the op amp all one s for lour2 The short around Ri is then re moved and the converter is zero adjusted This Material Copyrighted www national com By Its Respective Manufacturer DAC0830 Series Application Hints continued Cc louti VREF O DAC0830 loutz Ds005608 39 2 4 kQ RESISTOR ADDED FROM INPUT TO GROUND TO INSURE STABILITY FIGURE 8 DACO830 Ver O Ds005608 40 DIGITAL CODE 128 Vi V OUT REF 128 Vree 1LSB 128 Input Code IDEAL Vour VreF 1 LSB VreFl 1 LSB VREF 2 IVreFl 2 o 0 1 LSB 1 LSB M _rerl _ LsB Mage LSB Vrer
13. DACO830LCN LCWM amp FSR LCV DAC0831LCN FSR DACO832LCN LCWM amp FSR LCV Monotonicity 10V lt VREF LJ amp LCJ bits lt 10V bits Gain Error Max FS Gain Error Tempco Max Using internal Rip kK i FSC Power Supply Rejection All digital inputs latched high Vcc 14 5V to 15 5V 11 5V to 12 5V F FSR V 4 5V to 5 5V Reference Max kQ Input Min kQ Output Feedthrough Error Vaer 20 Vp p f 100 kHz mVp p ata inputs latched low 3 www national com This Material Copyrighted By Its Respective Manufacturer Electrical Characteristics continued Vrer 10 000 Vp unless otherwise noted Boldface limits apply over temperature TyinysTasTmax For all other limits Ta 25 C a Vec 5 Voc 5 H E E NDE Voc 12 Vpo 5 COS ee in DG to 15 Voc 5 Limit Parameter Conditions Note T Tested Design Units N kiy 2 Limit Limit Note 5 Note 6 CONVERTER CHARACTERISTICS Output Leakage lout1 All data inputs LJ amp LCJ 10 100 100 nA Current Max latched low LCN LCWM amp LCV 50 100 lout2 All data inputs LJ amp LOJ 100 100 nA latched high LCN LCWM amp LCV 50 100 Output louti All data inputs pF louti All data inputs pF latched high DIGITAL AND DC CHARACTERISTICS Digital Input Logic Low LJ 4 75V Voltages LJ 15 75V LCJ 4 75V Voc LCJ 15 75V LCWM fo Logic High 7 Voc Digital Input Digital inputs lt 0 8 Currents pA pA pA Supply Current mA Drain Electrical Characteristics V
14. NO 1 IDENT 0 260 0 005 6 604 0 127 PIN NO 1 IDENT n Beatin i MIN 0 300 0 320 OPTION 2 7 620 8 128 0 069 NOM 0 040 orrioN2 psa 0 065 1 524 2 ax are 3302 0 127 1 651 TYR 0 145 0 200 3 663 5 080 95 5 0 009 0 015 90 0 004 i 0 229 0 381 en 0 020 TYP 9 100 0 010 Des 0 125 0 140 0 508 9 060 0 005 2 540 40 254 0 018 0 003 3 175 3 556 MIN n 325 0040 1 524 0 127 0 457 0 076 0 015 1 016 f 255 ae N20A REV G Molded Dual In Line Package N Order Number DACO830LCN or DAC0832LCN NS Package Number N20A This Material Copyrighted 23 www national com By Its Respective Manufacturer 0 006 9 359 0 000 O PIN 1 IDENT 19 oy 0 065 aa 1 65 0 02940 003 o 74 0 08 YP Buffered D to A Converters ae bi Se Bo 4 3 3 by ot LIFE SUPPORT POLICY DAC0830 DAC0832 8 Bit uP Compatible Double 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user 0 15 8 89 foa l 0 01740 004 o 4340 10 P 18 Physical Dimensions inches millimeters unless otherwise noted Continued 0 31040 020 7 87 0 51 TY SEATING PLANE 0 020 MIN TYP 0 39040 005
15. O830 The reference voltage is connected to one of the current out put terminals lour for true binary digital control lout is for complementary binary and the output voltage is taken from the normal Vre_er pin The converter output is now a voltage in the range from OV to 255 256 Vper as a function of the ap plied digital code as shown in Figure 11 FULL SCALE ADJUSTMENT OVour Ver ZERO ADJUSTMENT OP AMP Vos ADJ DS005608 14 FIGURE 10 Adding Full Scale Adjustment OV lt Your lt Sii vaer MSB Ot LSB Dio ours 11 loutz 12 2 5 Voc REFERENCE DS005608 12 FIGURE 11 Voltage Mode Switching This configuration offers several useful application advan tages Since the output is a voltage an external op amp is not necessarily required but the output impedance of the DAC is fairly high equal to the specified reference input re sistance of 10 kQ to 20 kQ so an op amp may be used for buffering purposes Some of the advantages of this mode are illustrated in Figures 12 13 14 15 There are two important things to keep in mind when using this DAC in the voltage switching mode The applied refer ence voltage must be positive since there are internal para sitic diodes from ground to the lout and loure terminals which would turn on if the applied reference went negative There is also a dependence of conversion linearity and gain error on the voltage difference between Vec an
16. Op Amp 133k gt O 15 Voc Ay 4 O 10V lt Your lt 10v 238 0 lt Vpac lt 35 2 5V DS005608 60 FIGURE 14 Bipolar Output with Increased Output Voltage Swing 15 www national com This Material Copyrighted By Its Respective Manufacturer DAC0830 Series Application Hints Continue e Only a single 15V supply required Non interactive full scale and zero code output adjustments e Vmax and Viyjy must be 5VDC and OV 1 e Incremental Output Step O56 VMAX Vein D 255 e YOUT ZEG VMAX VMIN 5z VMIN 256 CHANGE iN ERROR 256 CODE D 15V D8005608 14 FIGURE 15 Single Supply DAC with Level Shift and Span Adjustable Output Gain and Linearity Error Variation vs Supply Voltage VOLTAGE MODE OPERATIO VREF AGAIN ERROR o 2 4 6 8 0 12 4 16 Ver SUPPLY VOLTAGE Vne DS005608 32 Note For these curves Vper is the voltage applied to pin 11 lout with pin 12 lout2 grounded FIGURE 16 Gain and Linearity Error Variation vs Reference Voltage VOLTAGE MODE OPERATION CHANGE IN ERROR T AGAIN ERROR Ta 25 C a 2 4 6 B W Veer REFERENCE VOLTAGE Vpc DS005608 33 FIGURE 17 www national com This Material Copyrighted 16 By Its Respective Manufacturer DAC0830 Series Application Hints Continued Gain and Linearity Error Variation vs Temperature
17. ROR g o0 iss GAIN ERAOR a 1 6 1 ne 2 Veo 18 p a 18 S 0 025 4p x B12 Fa a 12 z oP Voc 5Voc ua Z 08 fo das 2 0 025 z z 5 oos 0 4 0 4 0 075 Veo 15 Voe 0 0 0 1 55 35 15 5 25 45 65 85 105 125 5 10 15 55 35 15 5 25 45 65 85 105125 Ta AMBIENT TEMPERATURE C Vec SUPPLY VOLTAGE V Ta AMBIENT TEMPERATURE C DS005608 26 DS008608 27 DS005608 28 7 www national com This Material Copyrighted By Its Respective Manufacturer Typical Performance Characteristics continued Gain and Linearity Error Write Pulse Width Data Hold Time Variation vs Supply Voltage a 0 025 E ALINEARITY ERRI z a 000 ViH 5V a _0 025 Z aGAIN ERROR Z w S s Vec 5V 005 Vin 3 er Ss z 200 2 w 0 075 z Vec 12 S 2 2 H 5 0 100 100 E 5 E z Voc 12 Vin 3V 0 125 Voc 15V YIH 3V or 5 55 35 15 25 45 65 85 105125 55 35 15 5 26 4565 85 105129 0 5 10 15 Ta AMBIENT TEMPERATURE C Ta AMBIENT TEMPERATURE C Vcc SUPPLY VOLTAGE Vpc DS005608 29 DAC0830 Series Application Hints These DAC s are the industry s first microprocessor compat ible double buffered 8 bit multiplying D to A converters Double buffering allows the utmost application flexibility from a digital control point of view This 20 pin device is also pin for pin compatible with one exception
18. This Material Copyrighted 0 0 DAC0832LCM amp nbspJ 0 O national Semiconductor DAC0830 DAC0832 May 1999 8 Bit uP Compatible Double Buffered D to A Converters General Description The DAC0830 is an advanced CMOS Si Cr 8 bit multiplying DAC designed to interface directly with the 8080 8048 8085 Z80 and other popular microprocessors A deposited silicon chromium R 2R resistor ladder network divides the reference current and provides the circuit with excellent tem perature tracking characteristics 0 05 of Full Scale Range maximum linearity error over temperature The circuit uses CMOS current switches and control logic to achieve low power consumption and low output leakage current errors Special circuitry provides TTL logic input voltage level com patibility Double buffering allows these DACs to output a voltage cor responding to one digital word while holding the next digital word This permits the simultaneous updating of any number of DACs The DACO830 series are the 8 bit members of a family of microprocessor compatible DACs MICRO DAC Typical Application lt gt CONTADL BUS ts pata BUS 8080 BUS BI FET and MICRO DAC are trademarks of National Semiconductor Corporation Z80 is a registered trademark of Zilog Corporation 1999 National Semiconductor Corporation DS005608 Features m Double buffered single buffered or flow through digital data inputs Easy interchange and pi
19. com By Its Respective Manufacturer DAC0830 Series Application Hints Continues VREF ugt eee Bayne Rip lous loutz DS005608 37 FIGURE 6 DIGITAL INPUT Rm INTERNAL louti VREF O DACO830 Vout louts x Pin Yaer DIGITAL INPUT 19 Vos ADJUST D8S005608 38 FIGURE 7 2 3 Op Amp Considerations The op amp used in Figure 7 should have offset voltage null ing capability See Section 2 5 The selected op amp should have as low a value of input bias current as possible The product of the bias current times the feedback resistance creates an output voltage er ror which can be significant in low reference voltage applica tions BI FET op amps are highly recommended for use with these DACs because of their very low input current Transient response and settling time of the op amp are im portant in fast data throughput applications The largest sta bility problem is the feedback pole created by the feedback resistance Re and the output capacitance of the DAC This appears from the op amp output to the input and includes the stray capacitance at this node Addition of a lead capaci tance Co in Figure 8 greatly reduces overshoot and ringing at the output for a step change in DAC output current Finally the output voltage swing of the amplifier must be greater than Vpger to allow reaching the full scale output volt age Depending on the loading on the output o
20. d the voltage applied to the normal current output terminals This is a re sult of the voltage drive requirements of the ladder switches To ensure that all 8 switches turn on sufficiently so as not to add significant resistance to any leg of the ladder and thereby introduce additional linearity and gain errors it is recommended that the applied reference voltage be kept less than 5Vpc and Voc be at least 9V more positive than Vrer These restrictions ensure less than 0 1 linearity and gain error change Figures 16 17 18 characterize the ef fects of bringing Vrer and Vec closer together as well as typical temperature performance of this voltage switching configuration O HSY Voc Veer 2 5Voc DS005608 4 1 Voltage switching mode eliminates output signal inver sion and therefore a need for a negative power supply Zero code output voltage is limited by the low level output saturation voltage of the op amp The 2 kQ pull down re sistor helps to reduce this voltage Vog of the op amp has no effect on DAC linearity FIGURE 12 Single Supply DAC www national com This Material Copyrighted By Its Respective Manufacturer DAC0830 Series Application Hints continued 2 5V REFERENCE DACO830 Veer Dso0s608 42 D VouT 2 5V 2 1 Slewing and settling time for a full scale output change is 71 8 ws FIGURE 13 Obtaining a Bipolar Output from a Fixed Reference with a Single
21. e stability is of particular concern when using the higher accuracy versions the DAC0830 and DAC0831 or their advantages are wasted 3 0 GENERAL APPLICATION IDEAS The connections for the control pins of the digital input regis ters are purposely omitted Any of the control formats dis cussed in Section 1 of the accompanying text will work with any of the circuits shown The method used depends on the overall system provisions and requirements The digital input code is referred to as D and represents the decimal equivalent value of the 8 bit binary input for ex ample Binary Input D Decimal Equivalent This Material Copyrighted www national com By Its Respective Manufacturer Applications Capacitance Multiplier DAC Controlled Amplifier Volume Control DIGITAL INPUTS i our pacoe3a louti DACO830 Vaer sa da Ceouiv L DS005608 43 Dsoo0s608 44 Vin 256 bd Vor 256 e Ceauv C 1 e When D 0 the amplifier will go open loop and n P p the output will saturate e Maximum voltage across the equivalent capacitance is e Feedback impedance from the input to the out limited to Yomax cp om 1 5 D put varies from 15 kQ to as the input code changes from full scale to zero Cz is used to improve settling time of op amp Variable fo Variable Qo Constant BW Bandpass Filter R5 DS005608 17 Ra k 1 _ KD Rg t Ry _ Qo V356 Rak 1 PBW 3 racleAg a fo d
22. emiconductor Sales Office Dual In Line Package ceramic 300 C Distributors for availability and specifications Surface Mount Package Supply Voltage Veg 17 Voc Vapor Phase 60 sec 215 C Voltage at Any Digital Input Vee to GND Infrared 15 sec 220 C Voltage at Veer Input 25V r Per Storage Temperature Range 65 C to 150 C Operating Conditions Package Dissipation Temperature Range TMINSTAST wax at T 25 C Note 3 500 mW Part numbers with LCN suffix 0 C to 70 C DC Voltage Applied to Part numbers with LCWM suffix 0 C to 70 C lout OF lour2 Note 4 100 mV to Vee Part numbers with LCV suffix 0 C to 70 C ESD Susceptability Note 4 800V Part numbers with LCJ suffix 40 C to 85 C Part numbers with LJ suffix 55 C to 125 C Voltage at Any Digital Input Voc to GND Electrical Characteristics Vrer 10 000 Voc unless otherwise noted Boldface limits apply over temperature Tun lt Ta lt Tmax For all other limits Ta 25 C 59 vermis Pepai to 15 Vpc 5 imi Parameter Conditions De Limit Units CONVERTER CHARACTERISTICS Resolution bits Linearity Error Max Zero and full scale adjusted 10V lt Vpers 10V DACO830LJ amp LCJ FSR DACO832LJ amp LCJ FSR DACO830LCN LCWM amp FSR LCV DAC0831LCN FSR DACO832LCN LCWM amp FSR LCV Differential Nonlinearity Zero and full scale adjusted Max 10V lt VRers 10V DACO830LJ amp LCJ FSR DACO832LJ amp LCJ FSR
23. f the amplifier and the available op amp supply voltages only 12 volts in many development systems a reference voltage less than 10 volts may be necessary to obtain the full analog output voltage range 2 4 Bipolar Output Voltage with a Fixed Reference The addition of a second op amp to the previous circuitry can be used to generate a bipolar output voltage from a fixed ref erence voltage This in effect gives sign significance to the MSB of the digital input word and allows two quadrant multi plication of the reference voltage The polarity of the refer ence can also be reversed to realize full 4 quadrant multipli cation VReFx tDigital Code Voy7 This circuit is shown in Figure 9 This configuration features several improvements over exist ing circuits for bipolar outputs with other multiplying DACs Only the offset voltage of amplifier 1 has to be nulled to pre serve linearity of the DAC The offset voltage error of the second op amp although a constant output voltage error has no effect on linearity It should be nulled only if absolute output accuracy is required Finally the values of the resis tors around the second amplifier do not have to match the in ternal DAC resistors they need only to match and tempera ture track each other A thin film 4 resistor network available from Beckman Instruments Inc part no 694 3 R10K D is ideally suited for this application These resistors are matched to 0 1 and exhibit only
24. n compatible with 12 bit DAC1230 series Direct interface to all popular microprocessors Linearity specified with zero and full scale adjust only NOT BEST STRAIGHT LINE FIT Works with 10V reference full 4 quadrant multiplication Can be used in the voltage switching mode Logic inputs which meet TTL voltage level specs 1 4V logic threshold Operates STAND ALONE without uP if desired Available in 20 pin small outline or molded chip carrier package Key Specifications m Current settling time m Resolution 8 bits m Linearity 8 9 or 10 bits guaranteed over temp m Gain Tempco 0 0002 FSC w Low power dissipation 20 mW m Single power supply 5 to 15 Vpe 1 us www national com By Its Respective Manufacturer SIBHOAUOD Y 0 q paiayjng ajqnog ajquedwog dri g 8 zesoova oes0ova Connection Diagrams Top views Dual In Line and Molded Chip Carrier Package Small Outline Packages eae WR XFER Dl Di Dlg ts Vec 18 17 16 15 14 19 3 war he BYTE BYTE2 t ILE BYTE1 BYTE2 t GND WR y Dis XFER a Diz Dla 5 Dh Dis WR Dip LSB Dle GND VREF Oly MSB Re loutz Diz Dip Diy Dlo Veer ann loun DS005608 22 DS005608 21 www national com 2 This Material Copyrighted By Its Respective Manufacturer Absolute Maximum Ratings Notes 1 2 Lead Temperature Soldering 10 sec If Military Aerospace specified devices are required Dual In Line Package plastic 260 C please contact the National S
25. of the final output value Full scale settling time requires a zero to full scale or full scale to zero output change Full Scale Error Full scale error is a measure of the output error between an ideal DAC and the actual device output Ideally for the DAC0830 series full scale is Vae 1LSB For Veer 10V and unipolar operation VeuLt scaLe 10 0000V 39mV 9 961V Full scale error is adjustable to zero This Material Copyrighted www national com By Its Respective Manufacturer Definition of TerMS Continued Differential Nonlinearity The difference between any two consecutive codes in the transfer curve from the theoretical 1 LSB to differential nonlinearity MSB D m zz Monotonic If the output of a DAC increases for increasing digital input code then the DAC is monotonic An 8 bit DAC which is monotonic to 8 bits simply means that increasing digital input codes will produce an increasing analog output B BIT MULTIPLYING D A CONVERTER I 10 OUTPUTS FOLLOW D INPUTS a GND Q 0 DATA AT D IS LATCHED Dso0s608 4 FIGURE 1 DAC0830 Functional Diagram Typical Performance Characteristics Digital Input Threshold Digital Input Threshold Gain and Linearity Error vs Temperature vs Vec Variation vs Temperature 24 2 4 0 1 0 075 _ 2 0 2 0 LINEARITY ER
26. ow a processor other than the one controlling the DAC s to take over control of the data bus and control lines If this second system were to use the same ad dresses as those decoded for DAC control but for a different purpose the ILE function would prevent the DAC s from be ing erroneously altered In a Stand Alone system the control signals are generated by discrete logic In this case double buffering can be con trolled by simply taking CS and XFER to a logic 0 ILE toa logic 1 and pulling WR low to load data to the input latch Pulling WR low will then update the analog output A logic 4 on either of these lines will prevent the changing of the analog output This Material Copyrighted www national com By Its Respective Manufacturer DAC0830 Series Application Hints Continues DATA BUS OG OUTPUT UPDATED ILE LOGIC 1 WR2 and XFER GROUNDED DATA LATCHED DS005608 7 FIGURE 4 1 2 Single Buffered Operation In a microprocessor controlled system where maximum data throughput to the DAC is of primary concern or when only one DAC of several needs to be updated at a time a single buffered configuration can be used One of the two in ternal registers allows the data to flow through and the other register will serve as the data latch Digital signal feedthrough see Section 1 5 is minimized if the input register is used as the data latch Timing for this mode is shown in
27. r ground potential OVp lt as possible With VRer 10V every millivolt appearing at ei ther lour OF loute Wil cause a 0 01 linearity error In most applications this output current is converted to a voltage by using an op amp as s The inverting input of t hown in Figure 7 he op amp is a virtual ground created by the feedback from i s output through the internal 15 KO re sistor R All of the output current determined by the digital input and the reference voltage will flow through Ri to the output of the amplifier Two quadrant operation can be ob tained by reversing the polarity of Vacr thus causing lour to flow into the DAC and be sourced from the output of the am plifier The output voltage in either case is always equal to loutiXRi and is the opposite polarity of the reference volt age The reference can be either a stable DC voltage source or an AC signal anywhere in the range from 10V to 10V The DAC can be thought of as a digitally controlled attenuator the output voltage is always less than or equal to the applied reference voltage The Vre_r terminal of the device presents a nominal impedance of 15 kQ to ground to external circuitry Always use the internal Ry resistor to create an output volt age since this resistor matches and tracks with tempera ture the value of the resistors used to generate the output current lout This Material Copyrighted 1 www national
28. re used in the on chip R 2R ladder and tracks these resistors over temperature Vier Reference Voltage Input This input connecis an external precision voltage source to the internal R 2R ladder Veer can be selected over the range of 10 to 10V This is also the analog voltage in put for a 4 quadrant multiplying DAC application Veo Digital Supply Voltage This is the power supply pin for the part Vec can be from 5 to 15Vpc Operation is optimum for 15Vpe GND The pin 10 voltage must be at the same ground potential as lout and loute for current switching applications Any difference of potential Vog pin 10 will result in a linearity change of Vos pin 10 3VREF For example if Veer 10V and pin 10 is 9mV offset from lout and lourte the linearity change will be 0 03 Pin 3 can be offset 100mvV with no linearity change but the logic input threshold will shift e LSB EAROR BAND 1LSB ERROR ACTUAL ANALOG OUTPUT Dsoos608 24 DIGITAL INPUT DS005608 25 c Shifting fs adj to pass best straight line test iterations of the adjustment The end point test uses a standard zero and F S adjustment procedure and is a much more stringent test for DAC linearity Power Supply Sensitivity Power supply sensitivity is a measure of the effect of power supply changes on the DAC full scale output Settling Time Settling time is the time required from a code transition until the DAC output reaches within V2LSB
29. rer 10 000 Voc unless otherwise noted Boldface limits apply over temperature Tmmn lt Ta lt Tmax For all other limits Ta 25 C Vec 12 Vpct5 Veo 15 75 Voc to 15 Vpo 5 Tested Limit Note 5 Design Limit Typ Note 12 AC CHARACTERISTICS Current Setting ViL OV ViH 5V 1 0 fee Meese a Write and XFER ViL OV Viq 5V 11 100 fraewavin So Control Setup Time Control Hold Time Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions Note 2 All voltages are measured with respect to GND unless otherwise specified www national com 4 This Material Copyrighted By Its Respective Manufacturer Electrical Characteristics continued Note 3 The maximum power dissipation must be derated at elevated temperatures and is dictated by Tjmax 84a and the ambient temperature Ta The maximum allowable power dissipation at any temperature is Pp Tymax Ta ja or the number given in the Absolute Maximum Ratings whichever is lower For this device Tumax 125 C plastic or 150 C ceramic and the typical junction to ambient thermal resistance of the J package when board mounted is 80 C W For the N pack age this number increases to 100 C W and for the V package this number is 120 C W Note 4 For current switching applications both lout and lout must go to g
30. rm Note 13 Human body model 100 pF discharged through a 1 5 kQ resistor Switching Waveform ILE CS Wh 50 50 Vit Vin DATA BITS Vii SETTLED T0 louti loute LSB DS005608 2 5 www national com This Material Copyrighted By Its Respective Manufacturer Definition of Package Pinouts Control Signals All control signals level actuated CS Chip Select active low The CS in combination with ILE will enable WR ILE Input Latch Enable active high The ILE in combi nation with CS enables WR WR Write 1 The active low WR is used to load the digi tal input data bits Dl into the input latch The data in the input latch is latched when WR is high To update the input latch CS and WR must be low while ILE is high WR Write 2 active low This signal in combination with XFER causes the 8 bit data which is available in the input latch to transfer to the DAC register XFER Transfer control signal active low The XFER will enable WRz Other Pin Functions DI DIz Digital Inputs Dl is the least significant bit LSB and DI is the most significant bit MSB lour DAC Current Output 1 lour is a maximum fora digital code of all 1 s in the DAC register and is zero for all O s in DAC register loutz2 DAC Current Output 2 lourz is a constant minus louti OF lout loure constant I full scale for a fixed reference voltage Rip Feedback Resistor The feedback resi
31. round or the Virtual Ground of an operational amplifier The linearity error is degraded by approximately Vos Vref For example if Vaef 10V then a 1 mV offset Vos on Iouti oF lourt2 will introduce an additional 0 01 linearity error Note 5 Tested limits are guaranteed to National s AOQL Average Outgoing Quality Level Note 6 Guaranteed but not 100 production tested These limits are not used to calculate outgoing quality levels Note 7 Guaranteed at VpRer 10 Voc and Vger t1 Voc Note 8 The unit FSR stands for Full Scale Range Linearity Error and Power Supply Rejection specs are based on this unit to eliminate dependence on a par ticular Vper value and to indicate the true performance of the part The Linearity Error specification of the DACO0830 is 0 05 of FSR MAX This guarantees that after performing a zero and full scale adjustment see Sections 2 5 and 2 6 the plot of the 256 analog voltage outputs will each be within 0 05 xVpe_r of a straight line which passes through zero and full scale Note 9 Boldface tested limits apply to the LJ and LCJ suffix parts only Note 10 A 100nA leakage current with Rp 20k and Vrer 10V corresponds to a zero error of 100x10 9x20x105 x100 10 which is 0 02 of FS Note 11 The entire write pulse must occur within the valid data interval for the specified tw tpg tpp and tg to apply Note 12 Typicals are at 25 C and represent most likely parametric no
32. s This Material Copyrighted By Its Respective Manufacturer
33. stor is pro Linearity Error ACTUAL Ye LSB ERROR ANALOG OUTPUT ANALOG OUTPUT IDEAL RESPONSE DIGITAL INPUT DS005608 23 a End point test after zero and fs adj Definition of Terms Resolution Resolution is directly related to the number of switches or bits within the DAC For example the DAC0830 has 2 or 256 steps and therefore has 8 bit resolution Linearity Error Linearity Error is the maximum deviation from a straight line passing through the endpoints of the DAC transfer characteristic Itis measured after adjusting for zero and full scale Linearity error is a parameter intrinsic to the device and cannot be externally adjusted National s linearity end point test a and the best straight line test b c used by other suppliers are illustrated above The end point test greatly simplifies the adjustment proce dure by eliminating the need for multiple iterations of check ing the linearity and then adjusting full scale until the linearity is met The end point test guarantees that linearity is met after a single full scale adjust One adjustment vs multiple ACTUAL IDEAL RESPONSE DIGITAL INPUT b Best straight line vided on the IC chip for use as the shunt feedback resistor for the external op amp which is used to provide an output voltage for the DAC This on chip resistor should always be used not an exter nal resistor since it matches the resistors which a
34. system to be updated to their new analog output levels si multaneously via a common strobe signal DS005608 30 DS005608 31 The timing requirements and logic level convention of the register control signals have been designed to minimize or eliminate external interfacing logic when applied to most popular microprocessors and development systems It is easy to think of these converters as 8 bit write only memory locations that provide an analog output quantity All inputs to these DAC s meet TTL voltage level specs and can also be driven directly with high voltage CMOS logic in non microprocessor based systems To prevent damage to the chip from static discharge all unused digital inputs should be tied to Vec or ground If any of the digital inputs are inadvertantly left floating the DAC interprets the pin as a logic 1 1 1 Double Buffered Operation Updating the analog output of these DAC s in a double buffered manner is basically a two step or double write operation In a microprocessor system two unique sys tem addresses must be decoded one for the input latch con trolled by the CS pin and a second for the DAC latch which is controlled by the XFER line If more than one DAC is being driven Figure 2 the CS line of each DAC would typically be decoded individually but all of the converters could share a common XFER address to allow simultaneous updating of any number of DAC s The timing for this operation is shown
35. where the digital input is the decimal base 10 equivalent of the applied 8 bit binary word 0 to 255 Vrer is the voltage at pin 8 and 15 kQ is the nominal value of the internal resis tance R of the R 2R ladder network discussed in Section 2 1 Several factors external to the DAC itself must be consid ered to maintain analog accuracy and are covered in subse quent sections 2 1 The Current Switching R 2R Ladder The analog circuitry Figure 6 consists of a silicon chromium SiCr or Si chrome thin film R 2R ladder which is deposited on the surface oxide of the monolithic chip As a result there are no parasitic diode problems with the ladder as there may be with diffused resistors so the reference voltage Veer can range 10V to 10V even if Vec for the device is 5Vbpc The digital input code to the DAC simply controls the position of the SPDT current switches and steers the available ladder current to either lour Or lour as determined by the logic in put level 1 or 0 respectively as shown in Figure 6 The MOS switches operate in the current mode with a small volt age drop across them and can therefore switch currents of either polarity This is the basis for the 4 quadrant multiplying feature of this DAC 2 2 Basic Unipolar Output Voltage To maintain linearity o plied digital code it is the current output pin output current with changes in the ap important that the voltages at both of s be as nea
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National Semiconductor DAC0830/DAC0832 8 Bit P Compatible Double Buffered D to A Converters handbook