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BURR BROWN OPA121 handbook

1. INPUT VOLTAGE NOISE SPECTRAL DENSITY vs TEMPERATURE 1k 1k 1k S 100 100 KM KP KU 100 G E 10 10 2 SE 5 2 A 5 1 1 oO N a KM o 10 E ZS 0 1 0 1 1 0 01 0 01 1 10 100 1k 10k 100k 1M 50 25 0 25 50 75 100 125 Frequency Hz Ambient Temperature C BIAS AND OFFSET CURRENT POWER SUPPLY REJECTION vs INPUT COMMON MODE VOLTAGE vs FREQUENCY 10 10 140 120 a B a ze e 100 1 tho 3 5 80 E 5 g 6 Oo en Qn bi Q S o nu 2 m 0 5 40 2 O a 20 0 01 0 01 0 15 10 5 0 45 10 15 1 10 100 1k 10k 100k 1M 10M Common Mode Voltage V Frequency Hz COMMON MODE REJECTION vs FREQUENCY OPEN LOOP FREQUENCY RESPONSE 140 140 KM KM m 120 120 45 D 4 S 100 100 Gai 5 a Be O Kei bi SN ge 80 S 80 g O oO S 60 S 60 Phase S 40 40 Margin 135 E 65 O 20 20 0 0 180 1 10 100 1k 10k 100k 1M 10M 1 10 100 1k 10k 100k 1M 10M Frequency Hz Frequency Hz BURR BROWN OPA121 4 Offset Current pA Phase Shift Degrees TYPICAL PERFORMANCE CURVES conT Ta
2. 1 R 2kQ 0 01 10V Step Overload Recovery 50 Overdrive Gain 1 RATED OUTPUT Voltage Output R 2kQ Current Output Vo 10VDC Output Resistance DC Open Loop Load Capacitance Stability Gain 1 Short Circuit Current POWER SUPPLY Rated Voltage Voltage Range Derated Performance Current Quiescent lo OMADC TEMPERATURE RANGE Specification Ambient Temperature Operating Ambient Temperature Storage Ambient Temperature 8 Junction Ambient NOTES 1 Sample tested 2 Offset voltage offset current and bias current are specified with the units fully warmed up 3 Overload recovery is defined as the time required for the output to return from saturation to linear operation following the removal of a 50 input overdrive 4 100 C W for KU grade The information provided herein is believed to be reliable however BURR BROWN assumes no responsibility for inaccuracies or omissions BURR BROWN assumes no responsibility for the use of this information and all use of such information shall be entirely at the user s own risk Prices and specifications are subject to change without notice No patent rights or licenses to any of the circuits described herein are implied or granted to any third party BURR BROWN does not authorize or warrant any BURR BROWN product for use in life support devices and or systems BURR BROWN OPA121 2 ELECTRICAL FULL TEMPERATURE RANGE SPECIFICATIONS At Vc
3. 25 C Voc 15VDC unless otherwise noted LARGE SIGNAL TRANSIENT RESPONSE 15 o D S 5 0 gt 5 ZS O 15 0 25 50 Time us INPUT CURRENTS vs INPUT VOLTAGE WITH Voc PINS GROUNDED 2 i in zl Maximum Safe Current ai BE JEE CAE Input Current mA oO RELL LLL LA Sd SE e ke ke ke Le 2 15 10 5 0 5 10 15 nput Voltage V APPLICATIONS INFORMATION OFFSET VOLTAGE ADJUSTMENT The OPA121 offset voltage is laser trimmed and will require no further trim for most applications As with most ampli fiers externally trimming the remaining offset can change drift performance by about 0 3uV C for each 100uV of adjusted offset Note that the trim Figure 1 is similar to operational amplifiers such as 741 and AD547 The OPA121 can replace most BIFET amplifiers by leaving the external null circuit unconnected INPUT PROTECTION Conventional monolithic FET operational amplifiers require external current limiting resistors to protect their inputs against destructive currents that can flow when input FET gate to substrate isolation diodes are forward biased Most BIFET amplifiers can be destroyed by the loss of V cc Unlike BIFET amplifiers the Difet OPA121 requires input current limiting resistors only if its input voltage
4. Junction Temperature NOTES 1 Packages must be derated based on go 150 C W P package 0 200 C W M package 100 C W U package Top View P Package Plastic Mini DIP 2 Short circuit may be to power supply common only Rating applies to U Package Plastic SOIC 25 C ambient Observe dissipation limit and T PACKAGE INFORMATION Offset Trim Substrate PACKAGE DRAWING MODEL PACKAGE NUMBER OPA121KM TO 99 OPA121KP 8 Pin Plastic DIP OPA121KU 8 Pin SOIC in Voo In Output Offset Trim NOTE 1 For detailed drawing and dimension table please see end of data sheet or Appendix D of Burr Brown IC Data Book ORDERING INFORMATION TEMPERATURE MODEL PACKAGE RANGE OPA121KM TO 99 0 C to 70 C OPA121KP 8 Pin Plastic DIP 0 C to 70 C OPA121KU 8 Pin SOIC 0 C to 70 C BURR BROWN 3 OPA121 TYPICAL PERFORMANCE CURVES Ta 25 C Voc 15VDC unless otherwise noted BIAS AND OFFSET CURRENT
5. in put leads and should be connected to a low impedance point which is at the signal input potential The amplifier case should be connected to any input shield or guard via pin 8 This insures that the amplifier itself is fully surrounded by guard potential minimizing both leak age and noise pickup see Figure 2 If guarding is not required pin 8 case should be connected to ground BIAS CURRENT CHANGE VERSUS COMMON MODE VOLTAGE The input bias currents of most popular BIFET operational amplifiers are affected by common mode voltage Figure 3 Higher input FET gate to drain voltage causes leakage and ionization bias currents to increase Due to its cascode input stage the extremely low bias current of the OPA121 is not compromised by common mode voltage Teflon E I du Pont de Nemours amp Co BURR BROWN OPA121 Non Inverting Buffer TO 99 Bottom View e 5 450 BOARD LAYOUT FOR INPUT GUARDING Guard top and bottom of board Alternate use Teflon standoff for sensitive input pins LF156 157 Input Bias Current pA 5 Common Mode Voltage VDC FIGURE 3 Input Bias Current vs Common Mode Voltage
6. 0 0 OPALIN OO BURR BROWN OPA121 Low Cost Precision Difet OPERATIONAL AMPLIFIER FEATURES LOW NOISE 6nV VHz typ at 10kHz LOW BIAS CURRENT 5pA max LOW OFFSET 2mV max LOW DRIFT 3uV C typ HIGH OPEN LOOP GAIN 110dB min HIGH COMMON MODE REJECTION 86dB min DESCRIPTION The OPA121 is a precision monolithic dielectrically isolated FET Difet operational amplifier Out standing performance characteristics are now available for low cost applications Noise bias current voltage offset drift open loop gain common mode rejection and power supply rejection are superior to BIFET amplifiers Very low bias current is obtained by dielectric isolation with on chip guarding Laser trimming of thin film resistors gives very low offset and drift Extremely low noise is achieved with new circuit design techniques patented A new cascode design allows high precision input specifica tions and reduced susceptibility to flicker noise Standard 741 pin configuration allows upgrading of existing designs to higher performance levels Difet Burr Brown Corp BIFET National Semiconductor Corp International Airport Industrial Park Tel 520 746 1111 Mailing Address PO Box 11400 Twx 910 952 1111 Cable BBRCORP 1984 Burr Brown Corporation Tucson AZ 85734 Telex 066 6491 PDS 539F APPLICATIONS OPTOELECTRONICS DATA ACQUISITION TEST EQUIPMENT MEDICAL EQUI
7. PMENT RADIATION HARD EQUIPMENT Case TO 99 and Substrate 7 SH Noise Free Cascode Patented OPA121 Simplified Circuit Street Address 6730 S Tucson Blvd Tucson AZ 85706 FAX 520 889 1510 Immediate Product Info 800 548 6132 Printed in U S A September 1993 SPECIFICATIONS ELECTRICAL At Vcc 15VDC and T4 25 C unless otherwise noted Pin 8 connected to ground OPA121KM OPA121KP KU PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX INPUT NOISE Voltage fo 10Hz nV NHz fo 100Hz nV VHz fo 1kHz nV NHz fo 10kHz nV NHz fg 10Hz to 10kHz 5 Vrms fg 0 1Hz to 10 Hz d uVp p Current fg 0 1Hz to 10Hz 2 fA p p fo 0 1Hz thru 20kHz 1 1 fA VHz OFFSET VOLTAGE Input Offset Voltage Vom OVDC Average Drift Ta Twin to Tmax Supply Rejection BIAS CURRENT Input Bias Current Vom OVDC Device Operating OFFSET CURRENT Input Offset Current Vom OVDC Device Operating IMPEDANCE Differential 1013 4 1013 4 Common Mode 1014 3 10 4 3 VOLTAGE RANGE Common Mode Input Range 11 11 Common Mode Rejection Vin 10VDC OPEN LOOP GAIN DC Open Loop Voltage Gain R 2 2kQ FREQUENCY RESPONSE Unity Gain Small Signal Full Power Response 20Vp p R 2kQ Slew Rate Vo 10V R 2kQ Settling Time 0 1 Gain
8. c t15VDC and T4 Tmn tO Tmax unless otherwise noted OPA121KM OPA121KP KU PARAMETER CONDITIONS MIN TYP TYP TEMPERATURE RANGE Specification Range Ambient Temperature INPUT OFFSET VOLTAGE Input Offset Voltage Vom OVDC Average Drift Supply Rejection BIAS CURRENT Input Bias Current Vom OVDC Device Operating OFFSET CURRENT Input Offset Current Vom OVDC Device Operating VOLTAGE RANGE Common Mode Input Range Common Mode Rejection Vin HOND OPEN LOOP GAIN DC Open Loop Voltage Gain D 2kQ RATED OUTPUT Voltage Output RL 2kQ Current Output Vo 10VDC Short Circuit Current Vo OVDC POWER SUPPLY Current Quiescent lo OMADC NOTE 1 Offset voltage offset current and bias current are measured with the units fully warmed up ABSOLUTE MAXIMUM RATINGS CONNECTION DIAGRAMS 18VDC Top View M Package TO 99 Hermetic Internal Power Dissipation 500 MW Substrate and Case Differential Input Voltage 36VDC Input Voltage Range iccccccsicsccscscctcsscsesastsossenshessasecasanstbessuden dastened 18VDC Offset Storage Temperature Range Trim 1 M package 65 C to 150 C P U packages 55 C to 125 C Operating Temperature Range M package 40 C to 85 C P U packages 25 C to 85 C Lead Temperature M P packages soldering 10s 3800 C U package soldering 3s we 260 C Output Short Circuit Duration Continuous
9. is greater SMALL SIGNAL TRANSIENT RESPONSE 80 1 S 40 E o D 0 o gt 5 g fo 40 20mV 80 0 1 2 3 4 5 Time us 10mV Typical Trim Range 10kQ to 1MQ Trim Potentiometer 100k Recommended FIGURE 1 Offset Voltage Trim than 6V more negative than Vcc A 10kQ series resistor will limit input current to a safe level with up to 15V input levels even if both supply voltages are lost Static damage can cause subtle changes in amplifier input characteristics without necessarily destroying the device In precision operational amplifiers both bipolar and FET types BURR BROWN OPA121 this may cause a noticeable degradation of offset voltage and drift Static protection is recommended when handling any precision IC operational amplifier GUARDING AND SHIELDING As in any situation where high impedances are involved careful shielding is required to reduce hum pickup in input leads If large feedback resistors are used they should also be shielded along with the external input circuitry Leakage currents across printed circuit boards can easily exceed the bias current of the OPA121 To avoid leakage problems it is recommended that the signal input lead of the OPA121 be wired to a Teflon standoff If the OPA121 is to be soldered directly into a printed circuit board utmost care must be used in planning the board layout A guard pattern should completely surround the high impedance

BURR BROWN OPA121 handbook

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