IDT IDT2305 handbook
Contents
1. REF CLK2 CLK1 GND gt WO PD ao N APPLICATIONS e SDRAM Telecom e Datacom PC Motherboards Workstations e Critical Path Delay Designs PIN DESCRIPTION Functional Description Input reference clock 5 Volttolerantinput CLK2 Output clock CLK1 Output clock GND Ground CLK3 Output clock Vpop 3 3V Supply CLK4 Output clock CLKOUT Output clock internal feedback on this pin NOTES 1 Weak pull down 2 Weak pull down on all outputs IDT2305 3 3V ZERO DELAY CLOCK BUFFER COMMERCIAL ANDINDUSTRIAL TEMPERATURE RANGES OPERATING CONDITIONS COMMERCIAL Supply Voltage Operating Temperature Ambient Temperature Load Capacitance lt LOOMHz oO Load Capacitance 100MHz 133MHz Input Capacitance Ta S 8 Output LOW Voltage Standard Drive loL 8mA High Drive loL 12mA 1H Output HIGH Voltage Standard Drive IOH 8mA High Drive IOH 12mA 1H Supply Current Unloaded Outputs at 66 66MHz 1 2 SWITCHING CHARACTERISTICS 2305 1 COMMERCIAL OO os j 10pF Load 10 30pF Load Measured between 0 8V and 2V Measured between 0 8V and 2V All outputs equally loaded Measured at VpD 2 on the CLKOUT pins of devices Measured at 66 66MHz loaded outputs Stable power supply valid clock presented on REF pin NOTES 1 REF Input has a threshold voltage of Vop 2 2 All parameters specified with loaded outputs IDT23052. 3 3V ZERO DELAY CLOCK BUFFER COMMERCIAL ANDINDUSTRIAL TEMPERATURE RANGES 1 2 SWITCHING CHARACTERISTICS 2305 1H COMMERCIAL Parameter SSCaniions in Ty Max Unit Output Frequency 10pF Load Eka MHz 30pFLoad S y y y ooj hwo yea eean o o Cooyesesa mesra Four aoe e o s CRs Seeonee SiC ts Cramme S easter avensav iC ts Oe aroase o aje oly REE Ring Edge 0 CLKOUT Risma Eige Measured o fw Deveto Devcesten measurenatvonizonme CLOUT pnsoraenes o mo s Cowpaseneae vessen remeno svart V sing Testor 1 vis C oyceiocjce anes pe measiredares soure oadenompas ao PLL Lock Time Stable power supply valid clock presented on REF pin 1 m NOTES 1 REF Input has a threshold voltage of Vpp 2 2 All parameters specified with loaded outputs OPERATING CONDITIONS INDUSTRIAL ma OOO OO a te oeer S a S es Eoo M a Load Capacitance 100MHZz 133MHz CIN Input Capacitance 7 pF DC ELECTRICAL CHARACTERISTICS INDUSTRIAL e SSCS e SOS Output LOW Voltage Standard Drive lo 8mA High Drive lot 12mA 1H Output HIGH Voltage Standard Drive High Drive lOH 12mA 1H Supply Current Unloaded Outputs at 66 66MHz IDT2305 3 3V ZERO DELAY CLOCK BUFFER COMMERCIAL ANDINDUSTRIAL TEMPERATURE RANGES 1 2 SWITCHING CHARACTERISTICS 2305 1 INDUSTRIAL 10pF Load 10 30pF Load Measured at 1 4V Fout 66 66MHz Ou
3. gt ll zL xz 2 2 S 33MHz S 33MHz 66MHz 2 66MHz 5 100MHz 5 100MHz Q a 133MHz 40 40 3 3 1 3 2 3 3 3 4 3 5 3 6 3 3 1 3 2 3 3 3 4 3 5 3 6 voo V Vop V Duty Cycle vs Frequency Duty Cycle vs Frequency for 30pf loads over temperature 3 3V for 10pF loads over temperature 3 3V 60 60 Ge forecast a Se Sees od ee gt ee ee ae ee OE ye DG Pea sasSe Sar e era eee y OO aera San ee pee ee ees a i SE E SBA pron nnn 2 o R Y S S 2 rat A 44 44 caer aa a ee a ee ae 42 40 40 20 40 60 80 100 120 140 20 40 60 80 100 120 140 Frequency MHz Frequency MHz IDD vs Number of Loaded Outputs IDD vs Number of Loaded Outputs for 30pf loads over frequency 3 3V 25C for 10pF loads over frequency 3 3V 25C 140 140 120 MONG eo ee en ne ee eee ae 100 OO er a ee ee 80 ws lt 33MHz lt x 33MHz E 66MHz E 66MHz a 60 __ 100MHz 100MHz 40 20 0 0 0 2 4 6 8 0 2 4 6 8 Number of Loaded Outputs Number of Loaded Outputs NOTES 1 Duty Cycle is taken from typical chip measured at 1 4V 2 lbp data is calculated from Ipp Icore nCVf where Icore is the unloaded current n Number of outputs C Capacitance load per output F V Supply Voltage V f Frequency Hz IDT2305 3 3V ZERO DELAY CLOCK BUFFER COMMERCIAL ANDINDUSTRIAL TEMPERATURE RANGES TYP
4. 2 18 1 DT2305 hy 3 3V ZERO DELAY IDT2305 CLOCK BUFFER FEATURES Phase Lock Loop Clock Distribution 10MHz to 133MHz operating frequency Distributes one clock input to one bank of five outputs Zero Input Output Delay Output Skew lt 250ps Low jitter lt 200 ps cycle to cycle IDT2305 1 for Standard Drive IDT2305 1H for High Drive No external RC network required Operates at 3 3V VDD Power down mode Available in SOIC package DESCRIPTION The IDT2305 is a high speed phase lock loop PLL clock buffer designed to address high speed clock distribution applications The zero delay is achieved by aligning the phase between the incoming clock and the output clock operable within the range of 10 to 133MHz The IDT 2305 is an 8 pin version ofthe IDT2309 IDT2305 accepts one reference input and drives outfive low skew clocks The 1H version of this device operates up to 133MHz frequency and has a higher drive than the 1 device All parts have on chip PLLs which lock to an input clock on the REF pin The PLL feedback is on chip and is obtained from the CLKOUT pad Inthe absence of an input clock the IDT2305 enters power down In this mode the device will draw less than 25pA the outputs are tri stated and the PLL is not running resulting in a significant reduction of power The IDT2305 is characterized for both Industrial and Commercial operation FUNCTIONAL BLO
5. CK DIAGRAM i gt CLKOUT PLL gt 3 eki REF 1 gt Control i Logic M gt 2 CLK2 D gt 5 CLK3 gt CLK4 The IDT logo is a registered trademark of Integrated Device Technology Inc COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES APRIL 2001 2001 Integrated Device Technology Inc DSC 5174 4 IDT2305 3 3V ZERO DELAY CLOCK BUFFER COMMERCIAL ANDINDUSTRIAL TEMPERATURE RANGES PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS i CLKOUT Input Voltage Range REF VI Input Voltage Range 0 5to VoD mey nputCiampcuren lt 0 lo Vo 0 to VDD Continuous Output Current CLK3 Von or GND TA 55 C Maximum Power Dissipation 0 7 instill air Storage Temperature Range 65to 150 SOIC Commercial Temperature Oto 70 TOP VIEW Range Industrial Temperature 40 to 85 Range NOTES 1 Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed 3 The maximum package power dissipation is calculated using a junction temperature of 150 C and a board trace length of 750 mils
6. ICAL DUTY CYCLE AND Ibo TRENDS FOR IDT2305 1H Duty Cycle vs VDD for 30pf loads over frequency 3 3V 25C Q v S 33MHz 66MHz 100MHz a 3 3 1 3 2 3 3 3 4 3 5 3 6 Vpop V Duty Cycle vs Frequency for 30pf loads over temperature 3 3V 60 58 i eps eee et go if 13 lt p ne ia aa a f E a D a Ee ea a ee ee ee G L a 52 O ea dor aa ee ee a a a a 40C a S oc a EENS cree ee e aa 256 48 a 70C Sakti 85C 46 44 AD Pose Sate aos ease SCR Saas Soe ee Serer ee oe Soe eeseeaoe 40 20 40 60 80 100 120 140 Frequency MHz IDD vs Number of Loaded Outputs for 30pf loads over frequency 3 3V 25C 33MHz 66MHz 100MHz Number of Loaded Outputs NOTES 1 Duty Cycle is taken from typical chip measured at 1 4V Duty Cycle Duty Cycle IDD mA Duty Cycle vs VDD for 10pF loads over frequency 3 3V 25C 60 58 56 OA pre ee Fe Re ee enc tet a ee a if 33MHz 66MHz 100MHz 133MHz 50 ot 40 Vpop V Duty Cycle vs Frequency for 10pF loads over temperature 3 3V 60 58 56 BT PY N eee 42 40 20 40 60 80 100 120 140 Frequency MHz IDD vs Number of Loaded Outputs for 10pF loa
7. ds over frequency 3 3V 25C 160 33MHz 66MHz 100MHz Number of Loaded Outputs 2 Ibo data is calculated from IDD ICORE nCVf where ICORE is the unloaded current n Number of outputs C Capacitance load per output F V Supply Voltage V f Frequency Hz IDT2305 3 3V ZERO DELAY CLOCK BUFFER COMMERCIAL ANDINDUSTRIAL TEMPERATURE RANGES ORDERINGINFORMATION IDT _ XXXXX XX X Device Type Package Process Blank Commercial 0 C to 70 C Industrial 40 C to 85 C DC Small Outline DCG SOIC Green 2305 1 Zero Delay Clock Buffer 2305 1H High Drive Output CORPORATE HEADQUARTERS for SALES for Tech Support DT 2975 Stender Way 800 345 7015 or 408 727 6116 logichelp idt com e Santa Clara CA 95054 fax 408 492 8674 408 654 6459 www idt com
8. tputs For zero output to output skew all outputs must be loaded equally REF TO CLKA CLKB RELAY vs OUTPUT LOAD DIFFERENCE BETWEEN CLKOUT PIN AND CLKAICLKB PINS 1500 1000 500 500 REF to CLKAICLKB Delay ps 1000 1500 OUTPUT LOAD DIFFERENCE BETWEEN CLKOUT PIN AND CLKA CLKB PINS pF IDT2305 3 3V ZERO DELAY CLOCK BUFFER COMMERCIAL ANDINDUSTRIAL TEMPERATURE RANGES SWITCHING WAVEFORMS 1 4V TOONS ae Output w N to a Output 3 3V Output ov All Outputs Rise Fall Time Input to Output Propagation Delay CLKout Device 1 CLKout Device 2 t7 Vopd 2 Device to Device Skew TEST CIRCUITS ad VDD L a a CLKout L e CLKout OTRE a OUTPUTS _ 0 1uF AN OUTPUTS a Croa i 1KQ R TJ VDD s i i 0 14nF An aa GND GND GND GND Test Circuit 1 all Parameters Except t8 Test Circuit 2 t8 Output Slew Rate On 1H Devices IDT2305 3 3V ZERO DELAY CLOCK BUFFER COMMERCIAL ANDINDUSTRIAL TEMPERATURE RANGES TYPICAL DUTY CYCLE AND IDD TRENDS FOR IDT 2305 1 Duty Cycle vs VDD for 30pf loads over frequency 3 3V 25C Duty Cycle vs VDD for 10pF loads over frequency 3 3V 25C 60 60 Oe ee eee es ey ee ty ji 58 aaa aa a 56 gt eee Pcs ct rae ayieier re Gag a pee ee
9. tputto Output Skew Delay REF Rising Edge to CLKOUT Rising Edge Stable power supply valid clock presented on REF pin NOTES 1 REF Input has a threshold voltage of Vpp 2 2 All parameters specified with loaded outputs 1 2 SWITCHING CHARACTERISTICS 2305 1H INDUSTRIAL 10pF Load Alloutputs equally loaded Measured at VpD 2 on the CLKOUT pins of devices Measured between 0 8V and 2V using Test Circuit 2 Measured at 66 66MHz loaded outputs Stable power supply valid clock presented on REF pin NOTES 1 REF Input has a threshold voltage of Vpp 2 2 All parameters specified with loaded outputs IDT2305 3 3V ZERO DELAY CLOCK BUFFER COMMERCIAL ANDINDUSTRIAL TEMPERATURE RANGES ZERO DELAY ANDSKEW CONTROL All outputs should be uniformly loaded in order to achieve Zero I O Delay Since the CLKOUT pin is the internal feedback for the PLL its relative loading can affect and adjust the input output delay The Output Load Difference diagram illustrates the PLL s relative loading with respect to the other outputs that can adjust the Input Output I O Delay For designs utilizing zero I O Delay all outputs including CLKOUT must be equally loaded Even if the output is not used it must have a capacitive load equal to that onthe other outputs in order to obtain true zero I O Delay If 1 O Delay adjustments are needed use the Output Load Difference diagram to calculate loading differences between the CLKOUT pin and other ou
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IDT IDT2305 handbook