FAIRCHILD 6N137 HCPL-2630 HCPL-2601 HCPL-2631 HCPL-2611 handbook
Contents
1. Fig 7 Pulse Width Distortion vs Temperature Fig 8 Rise and Fall Time vs Temperature 80 600 TIN in 60 TEN E E Conditions 2 Conditions is rem o 400 IF 2 7 5 mA 5 RL 4kQ E Vcc 25V RL 4kO tr E 0 S 300 a BL E RL 1 KQ tr P d RL 350 0 bd ZS 20 8 200 RL 350 O tr o ac 3 400 a E y E a 0 z 0 RL 1K0 a R 4kO th RL 350 Q 60 40 20 0 20 40 60 80 100 60 40 20 0 20 40 60 80 100 TA Temperature C TA Temperature C Fig 9 Enable Propagation Delay vs Temperature Fig 10 Switching Time vs Temperature 120 T T 120 RL 4k TELH 100 ee a Ne be T T E S 9 Ej A 80 e c RL 4k 9 TPLH S 60L S RL 1kQTPLH Ri 1k TELH z S RL 350 Q TELH S o RL 350 0 TPLH S 40 o n D 2 E 20 30 m RL 350 0 RL 1kQ D RL 1k0 TEHL RL 4kQ J TPHL Res fikta 20 AL 350 0 60 40 20 0 20 40 60 80 100 60 40 20 0 20 40 60 80 100 TA Temperature C TA Temperature C Fig 11 High Level Output Current vs Temperature 20 Conditions Voc 5 5V Vo 5 5V js Ve 2 0V 5 lF 250 uA 5 o 5 a 5 10 o 9 gt En i 5 x S 0 60 40 20 0 20 40 60 80 100 Ta Temperature C www fairchildsemi com 6 OF 11 7 9 01 DS300202 EE LOGIC GATE OPTOCOUPLERS SEMICONDUCTOR SINGLE CHANNEL DUAL CHANNEL 6N137 HCPL 2630 HCPL 2601 HCPL 2631 HCPL 2611 A2. A 0 1 HF bypass capacitor must be connected between pins 8 and 5 See note 1 2001 Fairchild Semiconductor Corporation DS300202 7 9 01 1 OF 11 www fairchildsemi com FAIRCHILD HIGH SPEED 10 MBit s Saas LOGIC GATE OPTOCOUPLERS SEMICONDUCTOR SINGLE CHANNEL DUAL CHANNEL 6N137 HCPL 2630 HCPL 2601 HCPL 2631 HCPL 2611 ABSOLUTE MAXIMUM RATINGS No derating required up to 85 C Parameter Storage Temperature 55 to 125 Operating Temperature 40 to 85 Lead Solder Temperature 260 for 10 sec EMITTER DC Average Forward Single channel Input Current Dual channel Each channel Enable Input Voltage Single channel Not to exceed Vcc by more than 500 mV Reverse Input Voltage Each channel Power Dissipation Single channel Dual channel Each channel DETECTOR V Supply Voltage oe 1 minute max Output Current Single channel Dual channel Each channel Output Voltage Each channel Collector Output Single channel Power Dissipation Dual channel Each channel Parameter Input Current Low Level Input Current High Level Supply Voltage Output Enable Voltage Low Level Enable Voltage High Level Low Level Supply Current Fan Out TTL load 6 3 mA is a guard banded value which allows for at least 20 CTR degradation Initial input current threshold value is 5 0 mA or less www fairchildsemi com 2 OF 11 7 9 01 DS300202 E
3. t amp ou g e O oi D 03 S a d o z 02 001 g 1l 4 lg 9 6 mA lu Soo 1 lo 64 gp 0 001 0 0 40 20 0 20 40 60 80 0 9 1 0 14 12 13 14 1 5 1 6 Ta Ambient Temperature C Ve Forward Voltage V Fig 3 Switching Time vs Forward Current Fig 4 Low Level Output Current vs Ambient Temperature 120 50 Vec 25V lp 15 mA 100 T 45 E GT TT E lp 10 mA z S amp 80 40 6 5 RL 4kQ Tp 5 lk 5mA ie a S 60 5 835 F 9 2 E 40 E 30 Conditions a S Voc 5V 4 Ve 2V d R 1k RL 1KQ Teu 7 go 9 Vor 0 6 V D 4kOQ Teu Ri 350 Tp RL 350 kQ 0 i 20 5 7 9 11 13 15 40 20 0 20 40 60 80 lg Forward Current mA Ta Ambient Temperature C Fig 5 Input Threshold Current Fig 6 Output Voltage vs Input Forward Current vs Ambient Temperature A 4 T Conditions Vec 5 0 V Voss 06V R_ 3500 8 R 3500 g 3 4 S R 4k Q 5 S L RL 1kQ o o9 3 D gt 5 ZS g o E o 5 s gt 1 t nk E RL 4k0 1 0 40 20 0 20 40 60 80 0 1 2 3 4 5 6 Ta Ambient Temperature C Ip Forward Current mA DS300202 7 9 01 5 OF 11 www fairchildsemi com SSS aaa FAIRCHILD HIGH SPEED 10 MBit s EE LOGIC GATE OPTOCOUPLERS SEMICONDUCTOR SINGLE CHANNEL DUAL CHANNEL 6N137 HCPL 2630 HCPL 2601 HCPL 2631 HCPL 2611
4. Enable input propagation delay is measured from the 1 5 V level on the LOW to HIGH transition of the input voltage pulse to the 1 5 V level on the HIGH to LOW transition of the output voltage pulse 10 CM The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the high state i e Mou gt 2 0 V Measured in volts per microsecond V us 11 CM The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the low output state i e Vout lt 0 8 V Measured in volts per microsecond V us 12 Device considered a two terminal device Pins 1 2 3 and 4 shorted together and Pins 5 6 7 and 8 shorted together E e e oN www fairchildsemi com 4 OF 11 7 9 01 DS300202 FAIRCHILD HIGH SPEED 10 MBit s LOGIC GATE OPTOCOUPLERS SEMICONDUCTOR SINGLE CHANNEL DUAL CHANNEL 6N137 HCPL 2630 HCPL 2601 HCPL 2631 HCPL 2611 TYPICAL PERFORMANCE CURVES Fig 1 Low Level Output Voltage vs Ambient Temperature Fig 2 Input Diode Forward Voltage vs Forward Current 0 8 T Conditions Ip 5mA 30 0 7 H Ve 2V 16 Vec 5 5V lo z 16 mA 10 06 o loL 12 8 mA o lt x 0 5 E
5. APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component in any component of a life support systems which a are intended for surgical device or system whose failure to perform can be implant into the body or b support or sustain life reasonably expected to cause the failure of the life and c whose failure to perform when properly support device or system or to affect its safety or used in accordance with instructions for use provided effectiveness in labeling can be reasonably expected to result in a significant injury of the user DS300202 7 9 01 11 OF 11 www fairchildsemi com
6. pf bypass Pulse Generator trz5ns Zo 500 7 5 mA Au x bypass Fig 13 Test Circuit tg and feu DS300202 7 9 01 7 OF 11 www fairchildsemi com HIGH SPEED 10 MBit s FAIRCHILD Saas LOGIC GATE OPTOCOUPLERS SEMICONDUCTOR SINGLE CHANNEL DUAL CHANNEL 6N137 HCPL 2630 HCPL 2601 HCPL 2631 HCPL 2611 o 45V 3500 V Output PP Vo Pulse Gen 7 Eg5esases Peak E X DV 5V CMH Switching Pos A 0 LIE Vo Min ace ee Vo Max V Switching Pos B 7 5 mA o CML Fig 14 Test Circuit Common Mode Transient Immunity www fairchildsemi com 8 OF 11 7 9 01 DS300202 FAIRCHILD HIGH SPEED 10 MBit s LOGIC GATE OPTOCOUPLERS SEMICONDUCTOR SINGLE CHANNEL DUAL CHANNEL 6N137 HCPL 2630 HCPL 2601 HCPL 2631 HCPL 2611 Package Dimensions Through Hole Package Dimensions Surface Mount 0 390 9 91 0 370 9 40 0 390 9 91 0 370 9 40 a 0 070 178 _ 0070 1 78 L 0 045 1 14 0 045 1 14 0 020 0 51 1 MIN 0 016 0 41 0 020 0 51 MIN i i 0 008 0 20 aa i d i 0 154 3 90 0 120 3 05 0 300 7 62 TYP SEATING PLANE 0045 1 14 1 i i 0 022 0 56 0 022 0 56 _ 7 0016 0 41 0 315 8 00 0 016 0 41 0 016 0 40 o MIN 0 008 020 Vie 0 100 2 54 0 405 10 30 a 0 100 2 54 TYP TYR m MIN Lead Coplanarity 0 004 0 10 MAX 0 270 6 86 0 2
7. 50 6 35 rori 0 390 9 91 0 370 9 40 0 070 1 78 0 045 1 14 SEATING PLANE 0 200 5 08 0 140 3 55 NOTE 0 004 0 10 MIN d f All dimensions are in inches millimeters 1 0 120 3 05 d WM u 0 022 0 56 0 016 0 41 Hi 0 016 0 40 0 008 0 20 0 100 2 54 TYP 0 400 10 16 TYP DS300202 7 9 01 9 OF 11 www fairchildsemi com EE LOGIC GATE OPTOCOUPLERS SEMICONDUCTOR SINGLE CHANNEL DUAL CHANNEL 6N137 HCPL 2630 HCPL 2601 HCPL 2631 HCPL 2611 ORDERING INFORMATION Order Entry Identifier Description S Surface Mount Lead Bend SD Surface Mount Tape and reel 0 4 Lead Spacing 1 55 0 05 1 75 x 0 10 User Direction of Feed www fairchildsemi com 10 OF 11 7 9 01 DS300202 EE LOGIC GATE OPTOCOUPLERS SEMICONDUCTOR SINGLE CHANNEL DUAL CHANNEL 6N137 HCPL 2630 HCPL 2601 HCPL 2631 HCPL 2611 DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY FUNCTION OR DESIGN FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HERE IN NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS NOR THE RIGHTS OF OTHERS LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN
8. A Vep 3 5 V to Output Low Level RL 350 Q C 15 pF Note 9 Fig 13 Common Mode Transient Immunity Ta 25 C Now 50 V Peak at Output High Level IF 0 mA Vou Min 2 0 V 6N137 HCPL 2630 R 350 Q Note 10 HCPL 2601 HCPL 2631 Fig 14 HCPL 2611 Mou 400 V RL 350 Q Ur 7 5 mA VoL Max 0 8 V Common Mode 6N137 HCPL 2630 Wou 50 V Peak Transient Immunity HCPL 2601 HCPL 2631 TA 25 C at Output Low Level Note 11 Fig 14 HCPL 2611 Ta 25 C Moul 400 V Output Rise Time 10 90 Output Fall Time 90 1096 DS300202 7 9 01 3 OF 11 www fairchildsemi com SaaS aa FAIRCHILD HIGH SPEED 10 MBit s EE LOGIC GATE OPTOCOUPLERS SEMICONDUCTOR SINGLE CHANNEL DUAL CHANNEL 6N137 HCPL 2630 HCPL 2601 HCPL 2631 HCPL 2611 TRANSFER CHARACTERISTICS T 40 C to 85 C Unless otherwise specified DC Characteristics Test Conditions High Level Output Current Voc 5 5 V Vo 5 5 V lp 250 pA Vg 2 0 V Note 2 Low Level Output Current Voc 5 5 V Ip 5 mA Vg 2 0 V lc 13 mA Note 2 Vcc 5 5 V Vo 0 6 V Vg 2 0 V Io 18 mA Input Threshold Current ISOLATION CHARACTERISTICS T 40 C to 85 C Unless otherwise specified Characteristics Test Conditions Input Output Relative humidity 45 Insulation Leakage Current Ta 25 C t 5 s uo 3000 VDC Note 12 Withstand Insulation Test Volt
9. E LOGIC GATE OPTOCOUPLERS SEMICONDUCTOR SINGLE CHANNEL DUAL CHANNEL 6N137 HCPL 2630 HCPL 2601 HCPL 2631 HCPL 2611 ELECTRICAL CHARACTERISTICS T 40 C to 85 C Unless otherwise specified INDIVIDUAL COMPONENT CHARACTERISTICS Parameter Test Conditions EMITTER Ur 10 mA Input Forward Voltage Input Reverse Breakdown Voltage IR 10 pA Input Capacitance Vp 0 f 1 MHz Input Diode Temperature Coefficient Ic 10 mA DETECTOR High Level Supply Current Single Channel Vcc 5 5 V Ip 0 mA Dual Channel Vg 0 5 V Low Level Supply Current Single Channel Vcc 5 5 V Ip 10 mA Dual Channel Vg 0 5 V Low Level Enable Current Vcc 5 5 V Ve 0 5 V High Level Enable Current Vcc 5 5 V Ve 20V High Level Enable Voltage Vcc 5 5 V IF 10 mA Low Level Enable Voltage Vcc 5 5 V Ip 10 mA Note 3 AC Characteristics Propagation Delay Time Note 4 Ta 25 C to Output High Level D 350 C 15 pF Fig 12 TPLH Propagation Delay Time Note 5 Ta 25 C to Output Low Level RL 350 C 15 pF Fig 12 TPHL Pulse Width Distortion RL 350 C 15 pF Fig 12 Tea Tou Div 350 0 C 15 pF Note 6 Fig 12 RL 350 Q C 15 pF Note 7 Fig 12 Enable Propagation Delay Time Ip 7 5 mA Vep 3 5 V to Output High Level Ri 350 Q C 15 pF Note 8 Fig 13 Enable Propagation Delay Time Ip 7 5 m
10. Zhi dE FAIRCHILD HIGH SPEED 10 MBit s LOGIC GATE OPTOCOUPLERS ha Sea SEMICONDUCTOR SINGLE CHANNEL DUAL CHANNEL 6N137 HCPL 2630 HCPL 2601 HCPL 2631 HCPL 2611 DESCRIPTION The 6N137 HCPL 2601 2611 single channel and HCPL 2630 2631 dual channel optocouplers consist of a 850 nm AIGaAS LED optically coupled to a very high speed integrated photodetector logic gate with a strobable output This output features an open collector thereby permitting wired OR outputs The coupled parameters are guaranteed over the temperature range of 40 C to 85 C A maximum input signal of 5 mA will provide a minimum output sink current of 13 mA fan out of 8 An internal noise shield provides superior common mode rejection of typically 10 kV us The HCPL 2601 and HCPL 2631 has a minimum CMR of 5 kV us The HCPL 2611 has a minimum CMR of 10 kV us FEATURES Very high speed 10 MBit s e Superior CMR 10 kV us Double working voltage 480V Fan out of 8 over 40 C to 85 C Logic gate output Strobable output Wired OR open collector e U L recognized File E90700 APPLICATIONS Ground loop elimination e LSTTL to TTL LSTTL or 5 volt CMOS Line receiver data transmission 6N137 HCPL 2630 Data multiplexing HCPL 2601 HCPL 2631 Switching power supplies HCPL 2611 Pulse transformer replacement Computer peripheral interface TRUTH TABLE Positive Logic Output H
11. age RH lt 50 Ty 25 C Note 12 t 1 min Resistance Input to Output Vi o 500 V Note 12 Capacitance Input to Output f 1 MHz Note 12 All typical values are at Voc 5 V Ta 25 C NOTES The Vcc supply to each optoisolator must be bypassed by a 0 1uF capacitor or larger This can be either a ceramic or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible to the package Vcc and GND pins of each device 2 Each channel Enable Input No pull up resistor required as the device has an internal pull up resistor 4 tpi Propagation delay is measured from the 3 75 mA level on the HIGH to LOW transition of the input current pulse to the 1 5 V level on the LOW to HIGH transition of the output voltage pulse tpi Propagation delay is measured from the 3 75 mA level on the LOW to HIGH transition of the input current pulse to the 1 5 V level on the HIGH to LOW transition of the output voltage pulse 6 t Rise time is measured from the 90 to the 10 levels on the LOW to HIGH transition of the output pulse t Fall time is measured from the 10 to the 90 levels on the HIGH to LOW transition of the output pulse tg 4 Enable input propagation delay is measured from the 1 5 V level on the HIGH to LOW transition of the input voltage pulse to the 1 5 V level on the LOW to HIGH transition of the output voltage pulse 9 jeu
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