FAIRCHILD Single-channel: 6N135 6N136 HCPL-2503 HCPL-4502 Dual-Channel: HCPL-2530 HCPL-2531 High Speed Transistor Optocouplers handbook
Contents
1. B o a WW N l lt ir o z 04 1 10 100 F FORWARD CURRENT mA Fig 3 Output Current vs Output Voltage 16 Ta 25 C lp 40 mA 14 Vcc 5V lp 35 mA lt n lp 30 mA E pom Zz Ww 10 lp 2 25 mA a 2 o 8 lp 20 mA Eb gt gs lp 2 15 mA 3 i lp 10 mA o EUR 2 lp 5 mA 0 0 2 4 6 8 10 12 1 16 18 20 Vo OUTPUT VOLTAGE V Fig 5 Propagation Delay vs Temperature 4 1 K TPLH T z l LLI a z o z g a o a n e TPHL 9 K TPLH 60 40 20 TA 0 20 40 TEMPERATURE C 60 80 100 NORMALIZED CTR lou LOGIC HIGH OUTPUT CURRENT nA Tp PROPAGATION DELAY ns Fig 2 Normalized CTR vs Temperature Normalized to Ta 25 C 60 1000 100 40 20 0 20 40 60 TA TEMPERATURE C 80 100 Fig 4 Logic High Output Current vs Temperature 10 1000 40 20 0 20 40 60 Ta TEMPERATURE C 80 100 Fig 6 Propagation Delay vs Load Resistance RL LOAD RESISTANCE kQ 7 Single channel 6N135 6N136 HCPL 2503 HCPL 4502 Dual Channel HCPL 2530 HCPL 2531 Rev 1 0 3 www fairchildsemi com Jauueu2 ajfuig jauueu eng zoGr 1d9H 062 1d9H 9 LN9 SELNI s18jdno30jdg 10sisue1j paads ufilH LESZ 1d9H O Gz 1d9H Noise Pulse Noise2. Generator tr 5ns E Shield Vec Generator Ir Shield Vcc 1 8 tr 5ns 8 Pul ulse Zo 509 N RL i Vot Zo 500 10 D C Vf 100us Voz ae MONITOR Ha Ip Monitor P GND R Rm 4 4 Vri 10 DUTY CYCLE 2 Vf lt 1001S m i 1 5 uF Test Circuit for 6N135 6N136 HCPL 2503 and HCPL 4502 Test Circuit for HCPL 2530 and HCPL 2531 5V Teu TeLH Fig 7 Switching Time Test Circuit eee 1 ield loc 45V RL R Vo B uF 0 1 uF Vem k D Vem Pulse Gen Pulse Gen Test Circuit for 6N135 6N136 HCPL 2503 and HCPL 4502 Test Circuit for HCPL 2530 and HCPL 2531 Vem 10 V Vo im 5v Switch at A Ip 0 mA Vo lt a Switch at A Ip 16 mA Fig 8 Common Mode Immunity Test Circuit 8 Single channel 6N135 6N136 HCPL 2503 HCPL 4502 Dual Channel HCPL 2530 HCPL 2531 Rev 1 0 3 www fairchildsemi com Jauueu2 ajfuig Jauueu jeng zoGr 1d9H 062 1d9H 9 LN9 SELNI s18 dno30jdQ 10 sisuejj paads YI Lecz 1d9H 0 G2 1d2H Package Dimensions Through Hole 0 270 6 86 0 250 6 35 0 200 5 08 0 140 3 55 SEATING PLANE 0 154 3 90 0 120 3 05 15 ieee 0 200 iu 62 0 008 0 20 0 022 0 56 6016 041 E 0 016 0 40 100 2 54 TYP 0 270 6 86 0 250 6 35 0 390 9 91 0 370 9 40 0 0
3. 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which a are intended for surgical implant into support device or system whose failure to perform can the body or b support or sustain life or c whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system or to affect its safety or with instructions for use provided in the labeling can be effectiveness reasonably expected to result in significant injury to the user PRODUCT STATUS DEFINITIONS Definition of Terms Advance Information Formative or This datasheet contains the design specifications for In Design product development Specifications may change in any manner without notice Preliminary First Production This datasheet contains preliminary data and supplementary data will be published at a later date Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design No Identification Needed Full Production This datasheet contains final specifications Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor The datasheet is printed for reference information only Rev 116 12 www fair
4. Derate linearly above 70 C free air temperature at a rate of 2 0 mW C Current Transfer Ratio is defined as a ratio of output collector current Io to the forward LED input current lp times 100 The 4 1 kQ load represents 1 LSTTL unit load of 0 36 mA and 6 1kQ pull up resistor The 1 9 kQ load represents 1 TTL unit load of 1 6 mA and 5 6 kQ pull up resistor Common mode transient immunity in logic high level is the maximum tolerable positive dV dt on the leading edge of the com mon mode pulse signal Vcy to assure that the output will remain in a logic high state i e Vo gt 2 0 V Common mode transient immunity in logic low level is the maximum tolerable negative dV dt on the trailing edge of the common mode pulse signal Vom to assure that the output will remain in a logic low state i e Vo lt 0 8 V 9 Device is considered a two terminal device Pins 1 2 3 and 4 are shorted together and Pins 5 6 7 and 8 are shorted together 10 Measured between pins 1 and 2 shorted together and pins 3 and 4 shorted together O N D Ui SON 6 www fairchildsemi com Single channel 6N135 6N136 HCPL 2503 HCPL 4502 Dual Channel HCPL 2530 HCPL 2531 Rev 1 0 3 S1a dnos0 dQ 10jsisue1 paads ufiH Lecz 1d9H O amp SZ 1d9H Jeuueu jeng ZOSP 1d9H E0GZ 1d9H 9ELN SELNI Jeuueu ajBurs Fig 1 Normalized CTR vs Forward Current
5. 2 HCPL 2530 HCPL 2531 Pin 7 is not connected in Part Number HCPL 4502 2005 Fairchild Semiconductor Corporation 1 www fairchildsemi com Single channel 6N135 6N136 HCPL 2503 HCPL 4502 Dual Channel HCPL 2530 HCPL 2531 Rev 1 0 3 s18jdno30jdQ 10jsisue1j paads YIH LESZ 1d9H O SZ 1d9H 1 UULYJ IENd z Gt 1d9H 0SZ 1d9H 9 LN9 SELNI jauueua ajBurs Absolute Maximum Ratings T 25 C unless otherwise specified Parameter Symbol Value Units Storage Temperature TsrG 55 to 125 C Operating Temperature Topr 55 to 100 C Lead Solder Temperature TsoL 260 for 10 sec C EMITTER DC Average Forward Input Current Each Channel Note 1 lp avg 25 mA Peak Forward Input Current 50 duty cycle 1 ms P W IE pk 50 mA Each Channel Note 2 Peak Transient Input Current lt 1 us P W 300 pps lp trans 1 0 A Each Channel Reverse Input Voltage Each Channel Vn 5 V Input Power Dissipation 6N135 6N136 and HCPL 2503 4502 Pp 100 mW HCPL 2530 2531 Each Channel Note 3 45 DETECTOR Average Output Current Each Channel l avg 8 mA Peak Output Current Each Channel lo pk 16 mA Emitter Base Reverse Voltage 6N135 6N136 and HCPL 2503 only VeBR 5 V Supply Voltage Voc 0 5 to 30 V Output Voltage Vo 0 5 to 20 V Base Current 6N135 6N136 and HCPL 2503 only lp 5 mA Output power 6N135 6N136 HCPL 2503 HCPL 4502 Note 4 PD 100 mW dissi
6. 70 1 78 0 045 1 14 0 200 5 08 0 140 3 55 0 004 0 10 MIN SEATING PLANE 0 154 3 90 0 120 3 05 0022 0 56 j 0 016 0 40 0 016 0 41 0 008 0 20 LL 0 400 10 16 ad 0 100 2 54 TYP TY NOTE All dimensions are in inches millimeters Package Dimensions Surface Mount 0 390 9 91 0 370 9 40 0 270 6 86 0 250 6 35 0 070 1 78 0 045 1 14 0 300 7 62 TYP 0 020 0 51 0 016 0 41 MI N 0 008 a 20 MTS 0 56 0 045 1 14 E 0 41 0 315 8 00 0 idis a 54 MIN 0 ana te 30 Lead Coplanarity 0 004 0 10 MAX Recommended Pad Layout for Surface Mount Leadform 7 5 LJ 1 E 0 060 1 52 0 100 2 54 D 0 295 7 49 0 415 10 54 7 0 030 0 76 LILIE IL 9 Single channel 6N135 6N136 HCPL 2503 HCPL 4502 Dual Channel HCPL 2530 HCPL 2531 Rev 1 0 3 www fairchildsemi com s18jdno30jdg 10jsisue1j paads YIH LESZ 1d9H O SZ 1d9H auueu jeng z ct 1d9H 0SZ 1d9H 9 LN9 SELNI jauueua ajBurs Ordering Information Option Example Part Number Description S 6N135S Surface Mount Lead Bend SD 6N135SD Surface Mount Tape and reel Ww 6N135W 0 4 Lead Spacing V 6N135V VDE0884 TV 6N135TV VDE0884 0 4 lead spacing SV 6N135SV VDE0884 surface mount SDV 6N135SDV VDE0884 surface mount tape and reel Marking Information Definitions 1 Fairchild lo
7. AHN 136fH hv f PERGGSEDIXGIUNCUNCHESUENISU July 2005 FAIRCHILD et SEMICONDUCTOR Single channel 6N135 6N136 HCPL 2503 HCPL 4502 Dual Channel HCPL 2530 HCPL 2531 High Speed Transistor Optocouplers Features Description W High speed 1 MBit s The HCPL 4502 HCPL 2503 6N135 6 and HCPL 2530 HCPL E Superior CMR 10 kV us 2531 optocouplers consist of an AlGaAs LED optically coupled E Dual Channel HCPL 2530 HCPL 2531 to a high speed photodetector transistor W Double working voltage 480V RMS A separate connection for the bias of the photodiode improves E CTR guaranteed 0 70 C the speed by several orders of magnitude over conventional phototransistor optocouplers by reducing the base collector me ML racognizsd Eile 4 E90700 capacitance of the input transistor Applications An internal noise shield provides superior common mode rejec tion of 10kV us An improved package allows superior insulation W Line receivers permitting a 480 V working voltage compared to industry stan W Pulse transformer replacement dard of 220 V E Output interface to CMOS LSTTL TTL W Wide bandwidth analog coupling Package Schematic Nc 1 8 Voc MI i T 8 Vac V Y A F1 2 7 V5 2 i 7 Vor v REN l F i 3 6 V5 8 IN 6 V V i F2 i nic fal E ils GND h 5 GND 6N135 6N136 HCPL 2503 HCPL 450
8. CPL 4502 Note 8 Fig 8 HCPL 2503 HCPL 2531 All Typicals at TA 25 C 5 Single channel 6N135 6N136 HCPL 2503 HCPL 4502 Dual Channel HCPL 2530 HCPL 2531 Rev 1 0 3 www fairchildsemi com S1a dnos0 dQ 10jsisue1 paads ufiH Lecz 1d9H O amp SZ 1d9H Jeuueu jeng ZOSP 1d9H E0GZ 1d9H 9ELN9 SELNI auUeYs ajGuis Isolation Characteristics T 0 to 70 C Unless otherwise specified Characteristics Test Conditions Symbol Min Typ Max Unit Input output Relative humidity 45 l o 1 0 uA insulation leakage current TA 25 C t 5s Vi o 3000 VDC Note 9 Withstand insulation test voltage RH lt 50 Ty 25 C Viso 2500 VRMS Note 9 t 1 min Resistance input to output Note 9 V 500 VDC Rio 107 Q Capacitance input to output Note 9 f 1 MHz C o 0 6 pF DC Current gain lo 3 mA Vo 2 5 V HFE 150 Input Input RH x 45 Vi 500 VDC Note 10 li 0 005 uA Insulation leakage current t 5 s HCPL 2530 2531 only Input Input Resistance Vi 500 VDC Note 10 Ru 10 Q HCPL 2530 2531 only Input Input Capacitance f 1 MHz Note 10 Ci 0 03 pF HCPL 2530 2531 only Notes Derate linearly above 70 C free air temperature at a rate of 0 8 mA C Derate linearly above 70 C free air temperature at a rate of 1 6 mA C Derate linearly above 70 C free air temperature at a rate of 0 9 mW C
9. als at TA 25 C 3 www fairchildsemi com Single channel 6N135 6N136 HCPL 2503 HCPL 4502 Dual Channel HCPL 2530 HCPL 2531 Rev 1 0 3 S1a dnos0 dQ 10jsisue1 paads ufiH LEGZ 1d9H 0 GZ 1d9H Jeuueu jeng z Gr 1d9H E0GZ 1d9H 9ELN9 SELNI jeuueu ajBurs Transfer Characteristics T 0 to 70 C Unless otherwise specified Parameter Test Conditions Symbol Device Min Typ Max Unit COUPLED Ip 16 mA Vo 0 4 V CTR 6N135 7 18 50 Vec 4 5 V Ta 25 C HCPL 2530 Current transfer ratio 6N136 19 27 50 Note 5 HCPL 4502 HCPL 2531 HCPL 2503 12 27 Ip 16 mA Vcc 4 5V Vo 0 4V 6N135 21 926 VoL 0 5V HCPL 2530 Vo_ 0 4V 6N136 15 30 HCPL 4502 Vo 0 5V HCPL 2531 VoL 0 4V HCPL 2503 9 30 Ip 16 mA l 1 1 mA VoL 6N135 0 18 0 4 V Logic low output voltage Vcc 4 5 V Ta 25 C HCPL 2530 0 18 0 5 output voltage Ip 16 mA l 3 mA 6N136 0 25 0 4 Vec 4 5 V Ta 25 C HCPL 2503 HCPL 2531 0 25 0 5 Ip 16 mA l 0 8 mA 6N135 0 5 Vcc 4 5 V HCPL 2530 Ip 16 mA lo 2 4 mA HCPL 4502 0 5 Vcc 4 5 V HCPL 2531 All Typicals at TA 25 C 4 Single channel 6N135 6N136 HCPL 2503 HCPL 4502 Dual Channel HCPL 2530 HCPL 2531 Rev 1 0 3 www fairchildsemi com S1a dnos0 dQ 10jsisue1 paads ufiH Lecz 1d9H 0 GZ 1d9H Jeuueu jeng ZOSP 1d9H E0GZ 1d9H 9ELNO SELNI jeu
10. childsemi com Single channel 6N135 6N136 HCPL 2503 HCPL 4502 Dual Channel HCPL 2530 HCPL 2531 Rev 1 0 3 s19jdno30jdg 10sisue1j paads YIH LESZ 1d9H O SZ 1d9H auueu jeng z ct 1d9H 0SZ 1d9H 9 LN9 SELNI jauueua ajfurs
11. go Device number See order entry table VDE mark Note Only appears on parts ordered with VDE option Two digit year code e g 03 Two digit work week ranging from 01 to 53 Assembly package code 10 Single channel 6N135 6N136 HCPL 2503 HCPL 4502 Dual Channel HCPL 2530 HCPL 2531 Rev 1 0 3 www fairchildsemi com S1a dnos0 dQ 10jsisue1 paads ufiH Lecz 1d9H 0 GZ 1d9H Jeuueu jeng z Gr 1d9H E0GZ 1d9H 9ELN9 SELNI Jeuueu ajBurs Carrier Tape Specifications 4 90 0 20 1 55 0 05 0 30 0 05 1 75 0 10 y 0 1 MAX 10 30 0 20 User Direction of Feed Reflow Profile 215C 10 30 s b 225C peak p Time above 183C 60 150 sec Temperature C Ramp up 3C sec 15 2 25 3 Time Minute Peak reflow temperature 225C package surface temperature e Time of temperature higher than 183C for 60 150 seconds One time soldering reflow is recommended 11 Single channel 6N135 6N136 HCPL 2503 HCPL 4502 Dual Channel HCPL 2530 HCPL 2531 Rev 1 0 3 www fairchildsemi com s4 dn030 d0 J0js sued paads YIH LESZ 1d9H O SZ 1d9H auUeYD eNG z Gt 1d9H 0SZ 1d9H 9 LN9 SELNI jauueua ajBurs TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of al
12. l such trademarks ACEx FAST ISOPLANAR PowerSaver SuperSOT 8 ActiveArray FASTr LitleFET PowerTrench SyncFET Bottomless Fpgrw MICROCOUPLER QFET TinyLogic Build it Now FRFET MicroFET Qs TINYOPTO CoolFET GlobalOptoisolator MicroPak QT Optoelectronics TruTranslation CROSSVOLT GTO MICROWIRE Quiet Series UHC DOME HiSeC MSX RapidConfigure UltraFET EcoSPARK Ie MSXPro RapidConnect UniFET E CMOS i Lo OCX uSerDes VCX EnSigna ImpliedDisconnect OCXPro SILENT SWITCHER Wire FACT IntelliMAX OPTOLOGIC SMART START FACT Quiet Series OPTOPLANAR SPM PACMAN Stealth Across the board Around the world f POP SuperFET The Power Franchise Programmable Active Droop ONERE steer PowerEdge SuperSOT 6 DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TOANY PRODUCTS HEREIN TO IMPROVE RELIABILITY FUNCTION OR DESIGN FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS NOR THE RIGHTS OF OTHERS LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein
13. pation HCPL 2530 HCPL 2531 Each Channel 35 mW 2 www fairchildsemi com Single channel 6N135 6N136 HCPL 2503 HCPL 4502 Dual Channel HCPL 2530 HCPL 2531 Rev 1 0 3 S1a dnos0 dQ 10jsisue1 paads ufiH Lecz 1d9H 0 GZ 1d9H Jeuueu jeng z Gr 1d9H E0GZ 1d9H 9ELN9 SELNI Jeuueu ajBurs Electrical Characteristics T 0 to 70 C Unless otherwise specified Individual Component Characteristics Parameter Test Conditions Symbol Device Min Typ Max Unit EMITTER Ip 16 mA T4 225 C Ve 1 45 1 7 V Input Forward Voltage Ip 16 mA 1 8 Input Reverse Breakdown Voltage IR 10 pA Byn 5 0 V Temperature coefficient of Ip 16 mA AVE ATA 1 6 mV C forward voltage DETECTOR Logic high output current Ip 0 mA Vo Vcc 5 5 V lou All 0 001 0 5 yA TA 25 C Ip 0 mA Vo Vec 15 V 6N135 0 005 1 TA 25 C 6N136 HCPL 4502 HCPL 2503 Ip 0 mA Vo Voc 15 V All 50 Logic low supply current Ip 16 mA Vo Open loc 6N135 120 200 pA Voc 15 V 6N136 HCPL 4502 HCPL 2503 Ip4 lF2 16 mA Vo Open HCPL 2530 200 400 Voc 15 V HCPL 2531 Logic high supply current Ip 0 mA Vo Open Voc 15 locH 6N135 1 yA V 6N136 TA 25 C HCPL 4502 HCPL 2503 Ip 0 mA Vo Open 6N135 2 Vec 15 V 6N136 HCPL 4502 HCPL 2503 Ip 0 mA Vo Open HCPL 2530 0 02 4 Voc 15 V HCPL 2531 All Typic
14. ueu ajBurs Switching Characteristics T4 0 to 70 C unless otherwise specified Voc 5 V Parameter Test Conditions Symbol Device Min Typ Max Unit Propagation delay Ta 25 C Ry 4 1 KQ Ip 16 mA Note 6 Fig 7 6N135 0 45 1 5 us time to logic low TPHL HCPL 2530 Rr 1 9 KO Ip 16 mA Note 7 Fig 7 6N136 0 45 0 8 us TA 25 C HCPL 4502 HCPL 2503 HCPL 2531 RL 4 1 KO lp 16 mA Note 6 Fig 7 6N135 2 0 us HCPL 2530 Rr 1 9 KO lp 16 mA Note 7 Fig 7 6N136 1 0 us HCPL 4502 HCPL 2503 HCPL 2531 Propagation delay Ty 25 C R 4 1 KQ lp 16 mA Note 6 Fig 7 TpPLH 6N135 0 5 1 5 us time to logic high HCPL 2530 Ri 1 9 kQ lp 16 mA Note 7 Fig 7 6N136 0 3 0 8 us Ta 25 C HCPL 4502 HCPL 2503 HCPL 2531 RL 4 1 KO Ip 16 mA Note 6 Fig 7 6N135 2 0 us HCPL 2530 Ry 1 9 KQ Ip 16 mA Note 7 Fig 7 6N136 1 0 us HCPL 4502 HCPL 2503 HCPL 2531 Common mode Ip 0 mA Voy 10 Vp_p Ry 4 1 kQ ICMyl 6N135 10 000 V us transient Note 8 Fig 8 TA 25 C HCPL 2530 d lg 0 mA Vom 10 Vp p 6N136 10 000 Vis logie Migr Ta 25 C Ry 1 9 kQ HCPL 4502 Note 8 Fig 8 HCPL 2503 HCPL 2531 Common mode Ip 16 MA Voy 10 Vp p Ry 2 4 1 kQ IOMII 6N135 10 000 V us transient Note 8 Fig 8 TA 25 C HCPL 2530 immuna ar lp 16 mA Vow 10 Vp p 6N136 10 000 V us logic low Ri 1 9 kQ H
Download Pdf Manuals
Related Search