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ST ST93C06 ST93C06C DATA SHEET

1. tcLcH must be greater or equal to 1 us For example if tche is 250 ns then tcicu must be atleast 750 ns S SV DF P SK Figure 4 Synchronous Timing Start and Op Code Input OP CODE OP CODE OP CODE OP CODE 4 amp START 4 OP CODE INPUT n CP Oox AI00819C 4 15 ss SGS THOMSON A S ST93C06 ST93C06C Figure 5 Synchronous Timing Read or Write Q15 Q7 amp ADDRESS INPUT amp DATA OUTPUT AI00820C tSHQV tSLQZ amp ADDRESS DATA INPUT WRITE CYCLE DESCRIPTION cont d The DU Don t Use pin does not affect the function of the memory and it is reserved for use by SGS THOMSON during test sequences The pin may be left unconnected or may be connected to Vcc or Vss Direct connection of DU to Vss is recom mended for the lowest standby power consump tion Al01429 MEMORY ORGANIZATION The ST93C06 is organized as 32 bytes x 8 bits or 16 words x 16 bits If the ORG input is left uncon nected or connected to Vcc the x16 organization is selected when ORG is connected to Ground Vss the x8 organization is selected When the ST93C06 is in standby mode the ORG input should be unconnected or set to either Vss or Vcc in order to achieve the minimum power consump tion Any voltage between Vss and Vcc applied to ORG may increase the standby current value MSON TS
2. ST92C08 363 THOMSON ST93C06 ST93C06C 256 bit 16 x 16 or 92 x 8 SERIAL MICROWIRE EEPROM 1 MILLION ERASE WRITE CYCLES with 40 YEARS DATA RETENTION DUAL ORGANIZATION 16 x 16 or 32 x 8 BYTE WORD and ENTIRE MEMORY PROGRAMMING INSTRUCTIONS SELF TIMED PROGRAMMING CYCLE with AUTO ERASE mg READY BUSY SIGNAL DURING PROGRAMMING m SINGLE 5V 10 SUPPLY VOLTAGE m SEQUENTIAL READ OPERATION 5ms TYPICAL PROGRAMMING TIME m ENHANCED ESD LATCH UP PERFORMANCES for C VERSION ST93C06 and ST93C06C are replaced by the M93C06 DESCRIPTION The ST93C06 and ST93C06C are 256 bit Electri cally Erasable Programmable Memory EEPROM fabricated with SGS THOMSON s High Endurance Single Polysilicon CMOS technology In the text the two products are referred to as ST93CO06 The memory is divided into either 32 x 8 bit bytes or 16 x 16 bit words The organization may be selected by a signal applied on the ORG input The memory is accessed through a serial input D and by a set of instructions which includes Read a byte word Write a byte word Erase a byte word Erase All and Write All A Read instruction loads the address of the first byte word to be read into an internal address pointer Table 1 Signal Names gt mamma Organisation Select Supply Voltage V Vss Ground June 1997 NOT FOR NEW DESIGN 1 1 PSDIP8 B 0 4mm Frame SO8 M 150mil Width Figure 1
3. ky MICROELECTRONICS ST93C06 ST93C06C POWER ON DATA PROTECTION In order to prevent data corruption and inadvertent write operations during power up a Power On Reset POR circuit resets all internal programming circuitry and sets the device in the Write Disable mode When Vcc reaches its functional value the device is properly reset in the Write Disable mode and is ready to decode and execute an incoming instruction A stable Vcc must be applied before any logic signal INSTRUCTIONS The ST93C06 has seven instructions as shown in Table 6 The op codes of the instructions are made up of 4 bits some instructions use only the first two bits others use all four bits to define the op code The op code is followed by an address for the byte word which is four bits long for the x16 organi zation or five bits long for the x8 organization Each instruction is preceded by the rising edge of the signal applied on the S input assuming that clock C and data input D are low followed by a first clock pulse which is ignored by the ST93C06 optional clock pulse for the ST93C06C The data input D is then sampled upon the following rising edges of the clock C untill a 1 is sampled and decoded by the ST93C06 as a Start bit Even though the first clock pulse is ignored it recom mended to pull low the data input D during this first clock pulse in order to keep the timing upwardly compatible with other ST93Cxx devices The ST93C06 i
4. 0 8V OUTPUT Al00815 Table 3 Capacitance Ta 25 C f 1 MHz Note 1 Sampled only not 100 tested Table 4 DC Characteristics TA 0 to 70 C or 40 to 85 C Voc 5V 10 Supply Current TTL Inputs S Vin f 1 MHz cc Supply Current CMOS Inputs S Vin f 1 MHz 2 2 0 3 vw Input Low Voltage D C S Cee r usan mR re wma pv o Lec ves 1 S Vss C Vss ORG Vss or Vcc Output Low Voltage lt lt Output High Voltage lt SGS THOMSON _ SS YA MICROELECTRONICS ST93C06 ST93CO6C Table 5 AC Characteristics TA 0 to 70 C or 40 to 85 C Vcc 5V 10 at Parameter Testconamon umn max unt tess Chip Seat tightocoacran of w toe OodkLowtohiseectign Input Valid to Clock High o ns SS Temp Range grade 1 100 ns tcHDx tpiH Clock High to Input Transition Temp Range grades 3 6 Clock High to Output Low o so om ST93C06 300 ns C 2 e sa ton Geek tow eos ez e m ma Notes 1 Chip Select must bebrought low for a minimum of 250 ns tsisu between consecutive instruction cycles 2 The Clock frequency specification calls for a minimum clock period of 1 us therefore the sum of the timings 1
5. Al01395 The ST93C46C has an on board counter which counts the clock pulses from the Start bit until the falling edge of the Chip Select signal For the WRITE instructions the number of clock pulses incoming to the counter must be exactly 18 with the Organisation by 8 from the Start bit to the falling edge of Chip Select signal 1 Start bit 2 bits of Op code 7 bits of Address 8 bits of Data 18 if so the ST93C06C executes the WRITE instruction if the number of clock pulses is not equal to 18 the instruction will not be executed and data will not be corrupted In the same way when the Organisation by 16 is selected the number of clock pulses incoming to the counter must be exactly 25 1 Start bit 2 bits of Op code 6 bits of Address 16 bits of Data 25 from the Start bit to the falling edge of Chip Select signal if so the 5 93 06 executes the WRITE instruction if the number of clock pulses is not equal to 25 the instruction will not be executed and data will not be corrupted The clock pulse counter is active only on ERASE and WRITE in structions WRITE ERASE ERAL WRALL MSON NS ky MICROELECTRONICS ST93C06 ST93C06C ORDERING INFORMATION SCHEME Example ST93C06C M 1 OTR Revision Temperature Range blank CMOS F3 B PSDIP8 1 0to70 C 013TR Tape amp Reel Tech 0 4mm Frame 6 40 to 85 C Packing C CMOSF4 M 508 2 150mil Width 3 40 to 125 C Notes 1 ST93C
6. DUMMY AI00823B Notes 1 An n 3 forx16 org and4 for x8 org 2 Xn n 3 forx16 org and4 for x8 org Figure8 WRAL Sequence ere tr rar iar D b 0 X0IDn LJ n dab J L I OP Mt ld DATAIN gt BUSY READY CODE ADDR DUMMY AI00824B Note 1 n x16 org and 4 for x8 org 8 15 SGS THOMSON YA MICROELECTRONICS ST93C06 ST93C06C Erase All The Erase All instruction ERAL erases the whole memory all memory bits are set to 1 A dummy address is input during the instruction transfer and the erase is made in the same way as the ERASE instruction If the ST93C06 is still performing the erase cycle the Busy signal Q 0 willbe returned if S is driven high and the ST93C06 will ignore any data on the bus When the erase cycle is com pleted the Ready signal Q 1 will indicate if S is driven high that the ST93CO06 is ready to receive a new instruction Write All For correct operation an ERAL instruction should be executed before the WRAL instruction the WRAL instruction DOES NOT perform an automat ic erase before writing The Write All instruction WRAL writes the Data Inputbyte or word to all the addresses of the memory If the ST93C06 is still performing the write cycle the Busy signal Q 0 will be returned if S is driven high and the ST93C06 will ignore any data on the bus When the write cycle is completed the Ready signal Q 1
7. will indicate if S is driven high that the ST93CO06 is ready to receive a new instruction READY BUSY Status During every programming cycle after a WRITE ERASE WRAL or ERAL instruction the Data Out put Q indicates the Ready Busy status of the Figure 9 ST93C06 Timing Dummy Clock pulse memory when the Chip Select S is driven High Once the ST93C06 is Ready the Ready Busy status is available on the Data Output Q until a new start bit is decoded or the Chip Select S is brought Low COMMON 1 O OPERATION The Data Output Q and Data Input D signals can be connected together through a current limiting resistor to form a common one wire data bus Some precautions must be taken when operating the memory with this connection mostly to prevent a short circuit between the last entered address bit A0 and the first data bit output by Q The reader may also refer to the SGS THOMSON application note MICROWIRE EEPROM Common I O Opera tion DIFFERENCES BETWEEN ST93C06 AND ST93CO6C Each instruction of the ST93C06 requires an Addi tional Dummy clock pulse after the rising edge of the Chip Select input S and before the START bit see Figure 9 When replacing the ST93C06 with the ST93CO06C in an application it must be checked that this Dummy Clock cycle DOES NOT HAPPEN when D 1 ifitis so this clock pulse will latch an information which is decoded by the ST93CO06C as a START bit see Figure 10 and the fol
8. 06CB1 is available with 0 25mm lead Frame only 2 Temperature range on special request only Devices are shipped from the factory with the memory content set at all 1 s FFFFh for x16 FFh for x8 For alist of available options Package etc or for further information on any aspect of this device please contact the SGS THOMSON Sales Office nearest to you 12 15 SGS THOMSON Sa Mf BUGROBLECTRIONICS ST93C06 ST93C06C PSDIP8 8 pin Plastic Skinny DIP 0 4mm lead frame PSDIP8 PSDIP a Drawing is notto scale SGS THOMSON _ CS JA ST93C06 ST93CO6C 508 8 lead Plastic Small Outline 150 mils body width SO8 Drawing is not to scale 14 15 SGS THOMSON A A ST93C06 ST93C06C Information furnished is believed to be accurate and reliable However SGS THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringementof patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of SGS THOMSON Microelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written a
9. Logic Diagram ST93C06 ST93C06C AI00816B 1 15 This is information on a product still in production but not recommended for new designs ST93C06 ST93CO6C Figure 2A DIP Pin Connections ST93C06 ST93C06C AI00817B Warning DU Don t Use Table 2 Absolute Maximum Ratings TLEAD Vio Vcc Parameter Ambient Operating Temperature Storage Temperature Lead Temperature Soldering SO8 package PSDIP8 package Input or Output Voltages Q Vor or Hi Z 0 3 to Vcc 0 5 Supply Voltage 0 3 to 6 5 Electrostatic Discharge Voltage Human Body model e Electrostatic Discharge Voltage Machine model 3 Figure 2B SO Pin Connections ST93C06 ST93C06C AI00818C Warning DU Don t Use Sr 215 o 40 sec 10 sec ST93C06 ST93C06C ST93C06 ST93C06C 2000 500 Notes 1 Except for the rating Operating Temperature Range stresses above those listed in the Table Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability Refer also to the SGS THOMSON SURE Program and other relevant quality documents 2 MIL STD 883C 3015 7 100pF 1500 2 3 EIAJ IC 121 Condition C 200pF 0 Q DESCRIPTION con
10. cycle is completed the Ready signal Q 1 will indicate if S is driven high that the ST93C06 is ready to receive a new instruction Write The Write instruction WRITE is followed by the address and the 8 or 16 data bits to be written Data input is sampled on the Low to High transition of the clock After the last data bit has been sampled Chip Select S must be brought Low before the next rising edge of the clock C in order to start the ERASE WRITE S DISABLE D xj hl OP CODE AI00822D self timed programming cycle If the ST93CO06 is still performing the write cycle the Busy signal Q 0 will be returned if S is driven high and the ST93C06 will ignore any data on the bus When the write cycle is completed the Ready signal Q 1 will indicate if S is driven high that the ST93C06 is ready to receive a new instruction Programming is internally self timed the external clock signal on C input may be disconnected or left running after the start of a programming cycle and does not require an Erase instruction prior to the Write in struction The Write instruction includes an auto matic erase cycle before programing data 1 1 1 7 5 ky MICROELECTRONICS ST93C06 ST93CO6C Figure 7 ERASE ERAL Sequences 1 pe al OP Mt BUSY 4 READY CODE ADDR STATUS FT b hh x L 1 OP M d 44 BUSY et READY gt i CODE ADDR
11. lowing bits will be decoded witha shift of one bit START Bit Al01334 MSON SG ky MICROELECTRONICS ST93C06 ST93CO6C Figure 10 Comparative Timings WRONG TIMING For ST93C06 Dummy Clock pulse START Bit For ST93CO6C START Bit Bit 1 GOOD TIMING For ST93C06 Dummy Clock pulse START Bit For ST93C06C Nothing happens Bit 1 waits for D 1 Al01335 10 15 SGS THOMSON YA MICROELECTRONICS ST93C06 ST93C06C Figure 11 WRITE Swquence with One Clock Glitch Glitch DIFFERENCES BETWEEN ST93C06 AND ST93C06C cont d The ST93C06C is an enhanced version of the ST93CO06A and offers the following extra features EnhancedESD voltage Functional security filtering glitches on the clock input C Refer to Table 2 Absolute Maximum Ratings for more about ESD limits The following description will detail the Clock pulses counter available only on the ST93CO06C In anormal environment the ST93C06 is expected to receive the exact amount of data on the D input that is the exact amount of clock pulses on the C input In a noisy environment the amount of pulses re ceived on the clock input C may be greater than the clock pulses delivered by the Master Microcon troller driving the ST93CO6C In such a case a part of the instruction is delayed by one bit see Figure 11 and it may induce an erroneous write of data at a wrong address ADDRESS AND DATA ARE SHIFTED BY ONE BIT
12. o issue the EWDS instruction after every write cycle The READ instruction is not affected by the EWEN or EWDS instructions Erase The Erase instruction ERASE programs the ad dressed memory byte or word bits to 1 Once the addressis correctly decoded the falling edge ofthe Chip Select input S triggers a self timed erase cycle READ Read Data from Memory 10XX A4 A0 Q7 Q0 A3 A0 Q15 Q0 WRITE Write Data to Memory 01XX A4 A0 D7 D0 D15 D0 A3 A0 EWEN Erase Write Enable 0011 XXXXX x8 Org x16 Org Description Op Code Address Address ORG 0 ORG 1 ERASE Erase Byte or Word 11XX A4 A0 ERAL Erase All Memory 0010 XXXXX Write All Memory i _ WRAL with same Bata 0001 XXXXX D7 D0 XX XX D15 D0 Note X don t care bit EWDS Erase Write Disable 0000 XXXXX 615 SGS THONISON YA MICROELECTRONICS ST93C06 ST93C06C Figure 6 READ WRITE EWEN EWDS Sequences s E An E ET 13 1 J L d a L Jo b J x OP E OUT CODE ADDR T u KIZ An 4 CHECK rare TOTO STATUS L Jal J L dala b Ja c 8 E OP DATA IN PET CODE ADDR FT b of x Ll gt OP CODE ERASE WRITE ENABLE Notes 1 An n 3 for x16 org and 4 for x8 org 2 n 3 for x16 org and 4 for x8 org If the ST93C06 is still performing the erase cycle the Busy signal Q 0 will be returned if S is driven high and the ST93C06 will ignore any data on the bus When the erase
13. pproval of SGS THOMSON Microelectronics 1997 SGS THOMSON Microelectronics All Rights Reserved MICROWIRE isa registered trademark of National Semiconductor Corp SGS THOMSON Microelectronics GROUP OF COMPANIES Australia Brazil Canada China France Germany Hong Kong Italy Japan Korea Malaysia Malta Morocco The Netherlands Singapore Spain Sweden Switzerland Taiwan Thailand United Kingdom U S A SGS THONISON 15 15 YA
14. s fabricated in CMOS technology and is therefore able to run from zero Hz static input signals up to the maximum ratings specified in Table 5 Table 6 Instruction Set Read The Read instruction READ outputs serial data on the Data Output Q When a READ instruction is received the instruction and address are de coded and the data from the memory is transferred into an output shiftregister Adummy 0 bit is output first followed by the 8 bit byte or the 16 bit word with the MSB first Output data changes are triggered by the Low to High transition of the Clock C The ST93C06 will automatically increment the address and will clock out the next byte word as long as the Chip Select input S is held High In this case the dummy 0 bit is NOT output between bytes words and a continuous stream of data can be read Erase Write Enable and Disable The Erase Write Enable instruction EWEN authorizes the following Erase Write instructions to be executed the Erase Write Disable instruction EWDS disables the execution of the following Erase Write instructions When power is first ap plied the ST93C06 enters the Disable mode When the Erase Write Enable instruction EWEN is executed Write instructions remain enabled until an Erase Write Disable instruction EWDS is exe cuted or if the Power on reset circuit becomes active due to a reduced Vcc To protectthe memory contents from accidental corruption it is advisable t
15. t d The data contained at this address is then clocked out serially The address pointer is automatically incremented after the data is output and if the Chip Select input S is held High the ST93C06 can output a sequential stream of data bytes words In this way the memory can be read as a data stream from 8 to 256 bits long or continuously as the address counter automatically rolls over to 00 when the highest address is reached Program ming is internally self timed the external clock 2 15 signal on C input may be disconnected or left running after the start of a Write cycle and does not require an erase cycle prior to the Write instruc tion The Write instruction writes 8 or 16 bits at one time into one of the 32 bytes or 16 words After the start of the programming cycle aBusy Ready signal is available on the Data output Q when Chip Select S is driven High The design of the ST93C06 and the High Endur ance CMOS technology used for its fabrication give an Erase Write cycle Endurance of 1 000 000 cy cles and a data retention of 40 years SGS THONISON YA ST93C06 ST93C06C AC MEASUREMENT CONDITIONS Input Rise and Fall Times lt 20ns Input Pulse Voltages 0 4V to 2 4V Input Timing Reference Voltages 1V to 2 0V Output Timing Reference Voltages 0 8V to 2 0V Note that Output Hi Z is defined as the point where data is no longer driven Figure 3 AC Testing Input Output Waveforms 2 0V

ST ST93C06 ST93C06C DATA SHEET

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