ON semiconductor CS1112 Quad Power Output Driver handbook
Contents
1. CS1112 CS1112 Quad Power Output Driver The CS1112 is a Power Output Driver The IC incorporates four protected DMOS low side drivers designed to drive inductive and resistive loads in an automotive environment The outputs are controlled by an 8 bit serial peripheral interface SPI or its associated parallel input Each output contains overcurrent protection open load detection and inductive flyback clamps The device is overvoltage protected Overcurrent and open load faults are reported over the SPI port and at the STATUS lead Control SPI communication is initiated by asserting CSB low Data at the SI lead is transferred on the rising edge of SCLK The MSB is transferred first The outputs become active at the rising edge of CSB Diagnostic status bits are transferred out the SO lead at the falling edge of SCLK The SO lead is high impedance while CSB is high An open drain output STATUS reports a fault short to Vpwr GND or open load has occurred at one or more of the outputs Protection Each output independently detects shorts to Vpwr while the output is and open load short to ground while the output is off The fault register will be set if a fault occurs at the output The fault register will be reset if the fault condition is removed from the output The fault data is latched when CSB is asserted low If an overcurrent condition or short circuit to VBATT occurs the output goes into2. Industries LLC SCILLC ON Semiconductor and Lu are trademarks of Semiconductor Components Industries LLC SCILLC SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors
3. Vpp 0 3 V Single Pulse Avalanche Energy I 450 mA Out 0 1 2 3 50 mJ Operating Junction Temperature Ty 40 to 150 ESD Capability Human Body Model 1 5 kV Lead Temperature Soldering Reflow SMD styles only Note 1 230 peak 1 60 second maximum above 183 The maximum package power dissipation must be observed http onsemi com 2 ELECTRICAL CHARACTERISTICS CS1112 9 0 V lt Vpwr lt 17 V 4 5 V lt Vpp lt 5 5 V 40 C lt Tj lt 125 C 5 5 V lt Vpwr lt 25 V Outputs Functional unless otherwise specified Characteristic Test Conditions Min Typ Max Unit Supply Voltages and Currents Vpp Power On Reset Threshold Outputs Latched Off By Event 2 5 3 0 3 5 V Vpp Power On Reset Hysteresis 200 mV Vpwg Undervoltage Outputs Latched Off By Event 4 0 4 5 5 0 Vpwn Overvoltage Lockout Outputs Latched Off By Event 30 35 45 V Digital Supply Current ly ppy All Outputs On 350 mA 5 0 mA Analog Supply Current ly pwR All Outputs On 350 mA 5 0 mA Sleep Current ly pwr Vpp lt 0 5 V 10 Digital Inputs and Outputs Vin High SI SCLK CSB INO IN1 IN2 INS 70 N od Vin Low SI SCLK CSB INO IN1 IN2 INS 30 VDD VIN Hysteresis 230 mV Input Pulldown Current SI INO IN1 IN2 IN3 Vin 30
4. a low duty cycle mode for the duration of the fault The outputs are disabled during an overvoltage or undervoltage condition Features 4 0 MHz Serial Input Bus Parallel Input Control 1 0 O DMOS Drivers typ Power On Reset Internal Flyback Clamps Status Output Fault Protection 46 V Peak Transient Power Limiting Undervoltage Overvoltage Fault Reporting Open Load Short Circuit 8 Internally Fused Leads Semiconductor Components Industries LLC 2000 1 October 2000 Rev 10 ON Semiconductor http onsemi com SO 24L DW SUFFIX CASE 751E PIN CONNECTIONS AND MARKING DIAGRAM CHHSO MMAXTMV A Assembly Location WL L Wafer Lot YY Y Year WW W Work Week ORDERING INFORMATION Device Packege Shipping CS1112YDWF24 SO 24L 31 Units Rail CS1112YDWFR24 SO 24L 1000 Tape amp Reel Publication Order Number CS1112 D CS1112 APPLICATION DIAGRAM IN1 IN2 IN3 IN4 Vpp VpwR Q CMOS DMOS Serial Shift Low Side Registers and Switches and Latches Protection Circuitry Micro Controller with Bus Fault Reporting Status ABSOLUTE MAXIMUM RATINGS Rating Value Unit DC Supply Vpwr 0 3 to 30 V Output DC Voltage Out 0 1 2 3 46 V Vpp Supply Voltage 0 3 to 7 0 V Peak Transient 1 0 ms rise time 300 ms period 32 V Load Dump 14 V Vpwr 46 V Digital Input Voltage 0 3 to
5. harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer PUBLICATION ORDERING INFORMATION NORTH AMERICA Literature Fulfillment Literature Distribution Center for ON Semiconductor P O Box 5163 Denver Colorado 80217 USA Phone 303 675 2175 or 800 344 3860 Toll Free USA Canada Fax 303 675 2176 or 800 344 3867 Toll Free USA Canada Email ONlit hibbertco com CENTRAL SOUTH AMERICA Spanish Phone 303 308 7143 Mon Fri 8 00am to 5 00pm MST Email ONlit spanish hibbertco com ASIA PACIFIC LDC for ON Semiconductor Asia Support Phone 303 675 2121 Tue Fri 9 00am to 1 00pm Hong Kong Time Fax Response Line 303 675 2167 or 800 344 3810 Toll Free USA Canada American Technical Support 800 282 9855 Toll Free USA Canada EUROPE LDC for ON Semiconductor European Support German Phone 1 303 308 7140 Mon Fri 2 30pm to 7 00pm CET Email ONlit german hibbertco com French Phone 1 303 308 7141 Mon Fri 2 00pm to 7 00pm CET Email ONIit french Qhibbertco com English Phone 1 303 308 7142 Mon Fri 12 00pm to 5 00pm GMT Email ONlit hibbertco com EUROPEAN TOLL FREE ACCESS 00 800 4422 3781 Availabl
6. 40 C lt Ty lt 125 C 5 5 V Vpwr lt 25 V Outputs Functional unless otherwise specified Characteristic Test Conditions Min Typ Max Unit Serial Peripheral Interface 14 V SCLK Clock Period Co 200 pF 250 ns MAX Input Capacitance SI SCLK Note 1 12 pF VouT High SO 1 0 Vpp 1 0 uj VouT Low SO loL 1 0 mA S 53 0 5 SCLK High Time 4 0 MHz SCLK 2 0 V to 2 0 V 125 ns See Figure 1 SCLK Low Time 4 0 MHz SCLK 0 8 V to 0 8 V 125 ns See Figure 1 SI Setup Time SI 0 8 V 2 0 V to SCLK 2 0 V at 4 0 MHz 25 ns Note 1 see Figure 1 SI Hold Time SCLK 2 0 V to SI 0 8 V 2 0 V at 4 0 MHz 25 ns Note 1 see Figure 1 SO Rise Time 200 pF 0 1 Vpp to 0 9 Vpp 25 50 ns Note 1 SO Fall Time 200 pF 0 9 Vpp to 0 1 Vpp 50 ns Note 1 CSB Setup Time CSB 0 8 V to SCLK 2 0 V 60 ns see Figure 1 Note 1 CSB Hold Time SCLK 0 8 V to CSB 20V 75 ns see Figure 1 Note 1 SO Delay Time SCLK 0 8 V to SO Data Valid Vpp 5 0 V 65 125 ns 200 pF at 4 0 MHz see Figure 1 Note 1 Xfer Delay Time CSB rising edge to next falling edge 1 0 x us Note 1 1 Guaranteed by design PACKAGE PIN DESCRIPTION PACKAGE PIN 24 Lead SOIC PIN SYMBOL FUNCTION 1 VD
7. D Input voltage to bias logic and control circuitry 2 VPWR Input voltage to bias gate drive circuitry 3 OUTO Open drain output one 4 INO Parallel input one 5 6 7 8 GND Ground Reference 17 18 19 20 9 IN1 Parallel input two 10 OUT1 Open drain output two 11 SI SPI serial input 12 CSB SPI active low chip select 13 SCLK SPI clock input 14 SO SPI serial output http onsemi com 4 CS1112 PACKAGE PIN DESCRIPTION continued PACKAGE PIN 24 Lead SOIC PIN SYMBOL FUNCTION 15 OUT2 Open drain output three 16 IN2 Parallel input three 21 IN3 Parallel input four 22 OUT3 Open drain output four 23 STATUS Open drain output which is asserted when an open load or overcurrent condition occurs at any of the outputs 24 Rosc 82 kQ resistor tied to ground to set up accurate internal cur rent sources CIRCUIT DESCRIPTION Typical Operation OUTS Turning the output drivers on is an OR function with Control of the CS1112 can be done using the Serial the SPI input and the parallel inputs Peripheral Interface SPI port using the Data Input Note To prevent damage to the IC or the output load Vpp information in Table 1 or the outputs can be controlled via must be above the Power on Reset threshold 3 5 V before the parallel inputs INO IN1 IN2 IN3 INO controls OUTO INO IN1 IN2 or IN3 are asserted high lt 70 V pp controls OUT1 IN2 controls OUT2
8. Semiconductor s POWERSENSE process technology POWERSENSE combines the robustness of Bipolar with the dense logic capability of CMOS and the power capabilities of DMOS Power consumption is kept to a minimum using POWERSENSE in comparison to a bipolar technology A bipolar process requires DC bias currents to power up the integrated circuit This is needed in many applications requiring analog circuitry but is not needed here Digital POWERSENSE logic dissipates power only when switching because that is when transient gate charging current flows POWERSENSE logic requires little space and is a good economical solution The DMOS side of the process provides a robust user interface to the outside world on each of the outputs Peak transient capability of each output is rated at a maximum of 46 V typical of an automotive load dump transient The CS1112 uses quasi vertical DMOS transistors resulting in an output resistance Rps on at each output of less than 1 0 13 V and 500 mA 25 C The part can be put in a sleep mode where the part draws less than 2 0 WA of bias current from Vpwr The part enters this sleep mode when Vpp lt 0 5 V Maximum quiescent current for the device is 5 0 mA maximum for any combination of output drivers enabled Fault reporting is controlled by the CS1112 Overcurrent and short to VBATT are detected when the output is on Open load and short to ground are detected when the output is off Faults are rep
9. Vpp B 25 uA Input Pullup Current CSB Vin 70 Vpp 25 uA Status Low Istatus 0 5 mA 0 1 0 5 V Fault Detection Timing Overcurrent Sense Time tes Overcurrent Sense Time Rosc 82 25 62 5 100 us Overcurrent Shutdown Time Overcurrent Shutdown Time Rosc 82 kQ 1 60 3 94 6 3 ms Fault Duty Cycle After the first fault cycle Note 1 1 4 1 56 1 7 96 Open Load Trip Point IN Low 40 50 60 N od Open Load Sense Time Open Load Sense Time Rosc 82 kQ 12 5 100 hs Power Outputs VDRAIN Clamp Ip 20 mA tcLAMP 100 hs 48 52 64 V Drain Leakage Current VDRAIN 17 V 25 Drain Leakage Current VDRAIN 46 V 400 Rps oN Vpwn 13 V Ip 0 5 1 0 2 0 Current Limit Note 2 3 0 4 5 6 0 A Reverse Diode Drop Reverse Diode Drop 350 mA 1 4 Fall Time Delay toni VewR 13V Ri oap 33 10 us Note 3 see Figure 2 Rise Time Delay tyi VewR 13 V Ri oap 33 15 us Note 3 see Figure 2 Rise Time t 13 V 33 0 4 10 us Fall Time t 13 V 33 0 4 10 us 1 Guaranteed by design 2 A duty cycle mode will initiate at a minimum of 1 0 A and before the current limit 3 Output turn on delay and turn off delay from rising edge of CSB to the output reaching 50 of Vpwr http onsemi com 3 CS1112 ELECTRICAL CHARACTERISTICS continued 9 0 V lt Vpwr lt 17 V 4 5 V lt Vpp lt 5 5 V
10. and IN3 controls TIMING DIAGRAM SCLK Don t Care SI OUT1 Turn OFF OUT3 Time Table 1 SPI Inputs D7 D6 D5 D4 D3 D2 D1 DO X X X X OUT3 OUT2 OUT1 OUTO MSB LSB X Don t Care MSB is Transferred first http onsemi com 5 CS1112 SERIAL PERIPHERAL INTERFACE TIMING REQUIREMENTS CSB Setup CSB Hold CSB i amp Xfer Dela et NS OUTx pn jt m i Bape CE een 7096 Vpp i a 31 3096 V i o ee toh SO Delay SO Rise Fall Figure 1 Figure 2 BLOCK DIAGRAM INO IN1 IN2 IN3 Overvoltage Undervoltage QOUT1 Lockout Gate OUT3 Drive Serial Peripheral Interface Rs Serial D O ee o GND Fault Timer AH Data 0 Shorted Load O STATUS http onsemi com 6 CS1112 APPLICATION INFORMATION CIRCUIT DESCRIPTION The CS1112 was developed for use in very noisy and very harsh environments such as seen in an automobile system The device has four low side switches all controlled through an 8 bit Serial Peripheral Interface SPI port Control of the outputs is also OR d with parallel inputs This is a critical feature enhancement over similar devices because of the ease in which the parallel inputs can be used to control the outputs in a Pulse Width Modulation PWM mode Creating a PWM mode using just the serial port input is not a practical application This part uses ON
11. e from Germany France Italy UK Ireland Toll Free from Hong Kong amp Singapore 001 800 4422 3781 Email ONlit asia hibbertco com JAPAN ON Semiconductor Japan Customer Focus Center 4 32 1 Nishi Gotanda Shinagawa ku Tokyo Japan 141 0031 Phone 81 3 5740 2745 Email r14525 onsemi com ON Semiconductor Website http onsemi com For additional information please contact your local Sales Representative CS1112 D
12. ently query the device serially to determine its origin http onsemi com 9 CS1112 PACKAGE DIMENSIONS SO 24L DW SUFFIX CASE 751 04 ISSUE E 24 13 NOTES k 1 DIMENSIONING AND TOLERANCING PER ANSI Y14 5M 1982 4 2 CONTROLLING DIMENSION MILLIMETER B 3 DIMENSIONS A AND B DO NOT INCLUDE E x B 12x P MOLD PROTRUSION 4 MAXIMUM MOLD PROTRUSION 0 15 0 006 r 0 010 0 25 B PER SIDE iun Y 5 DIMENSION D DOES NOT INCLUDE DAMBAR 1 2 PROTRUSION ALLOWABLE DAMBAR PROTRUSION SHALL BE 0 13 0 005 TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION 24x D J Y MILLIMETERS INCHES 0 010 0 25 9 BO DIM MAX MIN A 1525 15 54 0 601 0 612 F 740 7 60 0 292 0299 C 235 265 0093 0 104 x45 D 035 049 0 014 0 019 041 0 90 0016 0 035 vni G 1 27 BSC 0 050 BSC J 023 0 32 0 009 0 013 013 029 0 005 0 011 T x M 0 89 09 8 SEATING M P 1005 1055 0 395 0 415 PLANE 2x G K R 025 075 0 010 0 029 PACKAGE THERMAL DATA Parameter SO 24L Unit Resc Typical 9 C W Resa Typical 55 C W http onsemi com 10 CS1112 Notes http onsemi com 11 CS1112 POWERSENSE is a trademark of Semiconductor Components
13. ght low activating the SPI port 16 new bits are clocked into the SI pin As the new bits are being clocked in the first 8 bits being clocked out of the SO pin are the fault bits followed by the first 8 bits which were clocked in the verification bits The verification bits should replicate the command bits http onsemi com 7 CS1112 Serial clock frequencies up to 4 0 MHz can be used by the CS1112 Internal pull up circuitry is provided on the Chip Select Bar CSB pin Internal active pulldowns are provided on the parallel input pins INO IN1 IN2 IN3 and SI pin A product highlight of this part is its ability to be daisy chained with other parts which follow the SPI protocol as defined in Figure 1 Figure 4 displays this aspect The serial output of each device is fed into the serial input of the next device All data bits are clocked into their respective registers while the CSB pin is low The drivers are switched to the resulting command when the CSB pin is brought back high CSB 5 Any IC using Any IC using SPI protocol SPI protocol Figure 4 Multiple SPI port devices can also be connected in a parallel fashion Figure 5 instead of the daisy chained connection previously shown The microprocessor controls the CS1112 in a multiplex fashion allowing the serial data input to be input to the device when the device is activated through the CSB pin This creates a system whose number of outputs is a mu
14. igital word is clocked into the IC a transition from low to high on the CSB pin translates the last 4 bits of information turning the outputs on or off An internal active pull up is connected to this input CMOS logic levels are required on this pin SCLK The SCLK Serial Clock clocks the internal shift registers This pin controls the data being shifted into the SI pin and data being shifted out of the SO pin CMOS logic levels are required on this pin INO IN1 IN2 IN3 These pins control their corresponding numbered output These are the parallel input pins which may be used to PWM the outputs They have 230 mV of hysteresis These inputs are OR d with their corresponding input bit in the serial control byte An internal active pull down is connected to these pins CMOS logic levels are required on these pins OUTO OUT1 OUT2 OUT3 These pins are the output low side driver pins They all have typically 1 0 Q at 13 V Current limit on these pins has a minimum specification of 3 0 A A low duty cycle mode 1 596 typ will initiate at a minimum of 1A and before the current limit Vpwr 14 V Battery voltage input 5 0 mA max is needed Vpp 5 0 V Supply input 5 0 mA max is needed STATUS Open drain output This pin goes low when an open load or overcurrent condition occurs on any of the outputs This provides immediate notification to the controller that a fault is present The controller can subsequ
15. ltiple of 4 Figure 5 displays a 12 output setup CS1112 SI OUTO CS1112 OUTO SCLK OUTI CS1112 SI OUTO SCLK OUT Figure 5 Figure 6 displays the device controlling 4 outputs with the use of its SPI port Figure 7 displays the device controlling 1 output with the SPI port and 3 outputs being controlled with the parallel inputs allowing them to run in a PWM mode SPI Controlled Outputs Parallel Inputs Control Figure 7 The 51112 provides a very efficient way of controlling 4 output drivers by minimizing the number of I O pins through use of the SPI port and still provides the flexibility of pulse width modulating the output drivers where needed The use of the SPI also allows the integrated circuit to communicate directly with the microprocessor While designed for an automotive environment the CS1112 can be used in other applications in the computer market industrial market telecommunications market or any other instance where numerous drivers are needed All parts are 100 tested and guaranteed to meet all parameters specified the electrical characteristics These specifications cover the entire voltage range for Vpwg 9 0 V to 17 V and Vpp 4 5 V to 5 5 V http onsemi com 8 CS1112 FAULT MODE OPERATION The CS1112 provides protection for a multitude of system faults and conditions These include Overvoltage Current Limit Open Circuit Output Short to Power Output Short to Grou
16. nd and Flyback Clamp Overvoltage The IC is constantly monitoring the voltage on the Vpwr pin If the voltage on this pin exceeds the Overvoltage Shutdown Threshold typically 35 V all outputs immediately turn off The programmed outputs via serial or parallel input turn back on once the voltage is brought back down below this level Current Limit Short to VBATT When the output current exceeds the Overcurrent 4 5 A typical for the Short Circuit Overcurrent Sense Time typically 62 5 us as it would do during an output short to VBATT its fault status bit will be latched to a logic one The fault status bit remains latched until the rising edge of CSB The output will go into a low duty cycle mode typically 1 56 as long as the overcurrent condition exists and the channel is on This protects the integrated circuit from damaging itself due to its thermal limits Open Circuit Short to Ground Open circuit conditions are detected while the outputs are off A fault bit is set when the Open Load Off Detection Voltage typically 0 5 x Vpp is present for the Open Load Off Sense Time typically 62 5 us as it would do during an output short to ground Flyback Clamp While the flyback clamp is not a fault mode it is a protection feature of the CS1112 When driving inductive loads it is normal to observe high voltage spikes on the output pin due to the stored energy in the windings when the device is turned off On chip clamps on
17. orted out of the serial output SO pin as a new 8 bit word is being fed into the serial input SD pin Figure 3 highlights the SPI interface between the microprocessor and the CS1112 The SPI control inputs and all other logic inputs are compatible with 5 0 V CMOS logic levels Parallel Inputs Control Fault Reporting Figure 3 The four communication lines which define the SPI interface are the SI SO CSB and SCLK The parallel inputs which control the outputs can also connect to the same microprocessor a separate microprocessor or any other sensor or electrical device which meets the voltage requirements of the CS1112 ViN max VDD 0 3 V SPI communication is as follows 2 scenarios 1 8 Bit Normal Operation CSB pin is brought low activating the SPI port Faults detected since the last CSB low to high transition are latched into the serial register when CSB goes low 8 command bits are clocked into the SI pin The four fault bits are clocked out of the SO pin CSB pin is brought high translating the final 4 bits to the outputs turning them on or off Faults are then detected and saved in the fault register when CSB goes low 2 16 Bit Operation For Command Verify CSB pin is brought low activating the SPI port 16 bits are clocked into the SI pin the last 4 are the 4 control pins for the four outputs CSB pin is brought high translating the last 4 bits to the outputs turning them on or off CSB pin is brou
18. the outputs limit the voltage amplitude on the pin to prevent damage to the device Each output has an Output Clamp which limits the output voltage to 52 V typical when measured at 20 mA for 100 us PIN FUNCTION DESCRIPTION SI The SI Serial Input receives serial 8 bit or 16 bit words sent most significant bit first Data is clocked in on the rising edge of SCLK An internal active pull down is connected to this input CMOS logic levels are required on this pin so The SO Serial Output can be connected to the serial data input pin of the microprocessor or it can be daisy chained to the serial input SI of another SPI compatible device This pin is tri stated unless a low CSB pin selects the device The signal on this pin is clocked from the falling edge of the SCLK pin The serial output data provides fault information for each output and returns most significant bit bit 7 first Bits 0 through 3 are output fault bits for outputs 0 through 3 respectively In 8 bit SPI mode bits 0 3 under normal conditions return all zeros representing no faults A 1 indicates a fault The output from this pin conforms to CMOS logic levels Rosc An 82 kQ resistor tied to ground sets up an accurate internal current source CSB The CSB Chip Select Bar is the select pin when the microprocessor wants to communicate with the CS1112 A low on this pin enables the SPI communication with the device and enables the SO pin After the d
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ON semiconductor CS1112 Quad Power Output Driver handbook