Philips BSP121 N-channel enhancement mode vertical D-MOS transistor handbook
Contents
1. 1998 Apr 01 MDA749 0 8 50 0 50 100 150 Vas th at T k os ho Vesan 425 C Veasith at 1 mA typical values Philips Semiconductors Product specification N channel enhancement mode vertical D MOS transistor BSP121 MDA750 28 k 24 2 1 6 1 2 0 8 0 4 50 0 50 100 7 0 150 Fig 10 he Roscom at Tj Ros on at 25 C at 400 mA 10 V typical values 1998 Apr 01 7 Philips Semiconductors Product specification N channel enhancement mode vertical BSP121 D MOS transistor PACKAGE OUTLINE Plastic surface mounted package collector pad for good heat transfer 4 leads SOT223 detail X 4 mm Lilia scale DIMENSIONS mm are the original dimensions UNIT A bp by D 3 1 6 7 mm 2 9 6 3 OUTLINE REFERENCES EUROPEAN VERSION JEDEC EIAJ PROJECTION ISSUE DATE EHH SOT223 oa 97 02 28 1998 Apr 01 8 Philips Semiconductors Product specification N channel enhancement mode vertical BSP121 D MOS transistor DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specific2. 2576 BSP1214 py 5 DISCRETE SEMICONDUCTORS DATA SHEET BSP121 N channel enhancement mode vertical D MOS transistor Product specification 1998 Apr 01 Supersedes data of April 1995 File under Discrete Semiconductors SC13b Philips PHILIPS Semiconductors DH LI p Philips Semiconductors Product specification N channel enhancement mode vertical BSP121 D MOS transistor DESCRIPTION QUICK REFERENCE DATA N channel enhancement mode Drain source voltage Vos max 200 V vertical D MOS transistor in a Gate source voltage open drain Veso max 20 V miniature SOT223 envelope and Drai nt DC miax 350 mA designed for use as a line current ANSTO ATE a i interrupter in telephone sets and for Total power dissipation up to application in relay high speed and Tamb 25 C Prot max 1 5 W line transformer drivers Drain source on resistance ESA typ lb 400 mA Vas 10V Rpscon Ea 60 Q FEATURES i e Direct interface to C MOS TTL Transfer admittance EE etc lo 400 mA Vos 25 V Yil o dee e High speed switching e No secondary breakdown PINNING SOT223 1 gate 2 drain 3 source 4 drain Marking code BSP121 PIN CONFIGURATION Top view MAM054 Fig 1 Simplified outline and symbol 1998 Apr 01 2 Philips Semiconductors N channel enhancement mode vertical D MOS transistor RATINGS Limiting values in accordance with the Absolute Maximum System IEC 134 Drain source voltage Vps Gate sou
3. 94088 3409 Tel 1 800 234 7381 Uruguay see South America Vietnam see Singapore Yugoslavia PHILIPS Trg N Pasica 5 v 11000 BEOGRAD Tel 381 11 625 344 Fax 381 11 635 777 Internet http www semiconductors philips com SCA59 All rights are reserved Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner The information presented in this document does not form part of any quotation or contract is believed to be accurate and reliable and may be changed without notice No liability will be accepted by the publisher for any consequence of its use Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights Printed in The Netherlands 135108 00 03 pp12 Philips Semiconductors Date of release 1998 Apr 01 Document order number 9397 750 03676 Lets make things better S PHILIPS
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5. V Vas 0 to 10 V ton Bin E i t typ 15 ns ot max 20 ns 1998 Apr 01 4 Philips Semiconductors Product specification N channel enhancement mode vertical D MOS transistor BSP121 TEEN 90 DD INPUT 10 10M OUTPUT ipi o OV 50 9 off z7 2 MBB691 MBB692 Fig 2 Switching time test circuit Fig 3 Input and output waveforms 2 MBB693 MDA745 Prot W 1 6 1 2 0 8 0 4 0 0 50 100 150 200 25 Tamb C Vps V Fig 4 Power derating curve Fig 5 Output characteristic Tj 25 C typical value 1998 Apr 01 5 Philips Semiconductors N channel enhancement mode vertical D MOS transistor MDA746 0 8 0 4 Fig 6 Transfer characteristic Vps 10 V Tj 25 C typical values Product specification BSP 121 MDA747 160 Cc pF 120 80 Ciss 40 Coss 4 Crss 0 0 5 10 15 20 5 Vps V Fig 7 Capacitance as a function of drain source voltage Ves 0 f 1 MHz Tj 25 C typical values MDA748 104 ID mA V 10V 103 GS 5V 4V 102 10 6 8 10 12 14 Rpson Fig 8 Tj 25 C typical values
6. ations for product development Preliminary specification This data sheet contains preliminary data supplementary data may be published later Product specification This data sheet contains final product specifications Application information Where application information is given it is advisory and does not form part of the specification LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale 1998 Apr 01 9 Philips Semiconductors Product specification N channel enhancement mode vertical D MOS transistor BSP121 NOTES 1998 Apr 01 10 Philips Semiconductors Product specification N channel enhancement mode vertical D MOS transistor BSP121 NOTES 1998 Apr 01 11 Philips Semiconductors Argentina see South America Australia 34 Waterloo Road NORTH RYDE NSW 2113 Tel 61 2 9805 4455 Fax 61 2 9805 4466 Austria Computerstr 6 A 1101 WIEN P O Box 213 Tel 43 160 1010 Fax 43 160 101 1210 Belarus Hotel Minsk Business Center Bld 3 r 1211 Volodarski Str 6 220050 MINSK Tel 375 172 200 733 Fax 375 172 200 773 Belgium see The Netherland
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8. rce voltage open drain Veso Drain current DC Ib Drain current peak IDM Total power dissipation up to Tamb 25 C note 1 Piot Storage temperature range Tsto Junction temperature T THERMAL RESISTANCE From junction to ambient note 1 Rthj a Note Product specification BSP121 max 200 V max 20 V max 350 mA max 1 2 A max 15 W 65 to 150 C max 150 C 83 3 K W 1 Device mounted on an epoxy printed circuit board 40 mm x 40 mm x 1 5 mm mounting pad for the drain lead min 6 cm2 1998 Apr 01 3 Philips Semiconductors Product specification N channel enhancement mode vertical BSP121 D MOS transistor CHARACTERISTICS Tj 25 C unless otherwise specified Drain source breakdown voltage Ip 10 uA Vas 0 V BR DSS min 200 V Drain source leakage current Vos 160 V Ves 0 Ibss max 1 0 uA Vps 60V Vas 0 Ibss max 200 nA Gate source leakage current Ves 20 V Vps 0 tlass max 100 nA Gate threshold voltage TSN min i Ip 1 mA Vos Vas Vasith mak 28 V Drain source on resistance i dene lb 400 mA Vas 10 V Rpscon nes 6 0 Q Transfer admittance Ba ane Ip 400 mA Vos 25 V NA B de Input capacitance at f 1 MHz f EE Vos 25 V Ves 0 Ciss ih 60 br Output capacitance at f 1 MHz Vos 25 V Vas 0 C Yp 13 pF DS YGS oss max 25 pF Feedback capacitance at f 1 MHz Be oe Vos 25 V Ves 0 Crss dao 10 OF Switching times see Figs 2 and 3 ee Ip 250 MA Vop 50
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Philips BSP121 N channel enhancement mode vertical D MOS transistor handbook