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ANALOG DEVICES AD744 Precision 500 ns Settling BiFET Op Amp handbook

1. AD744BQ 0 ANALOG DEVICES Precision 500 ns Settling BiFET Op Amp AD744 FEATURES AC PERFORMANCE 500 ns Settling to 0 01 for 10 V Step 1 5 ps Settling to 0 0025 for 10 V Step 75 Slew Rate 0 0003 Total Harmonic Distortion THD 13 MHz Gain Bandwidth Internal Compensation 2200 MHz Gain Bandwidth G 1000 External Decompensation 21000 pF Capacitive Load Drive Capability with 10 V ps Slew Rate External Compensation DC PERFORMANCE 0 5 mV max Offset Voltage AD744B 10 pV C max Drift AD744B 250 V mV min Open Loop Gain AD744B Available in Plastic Mini DIP Plastic SOIC Hermetic Cerdip Hermetic Metal Can Packages and Chip Form Surface Mount SOIC Package Available in Tape and Reel in Accordance with EIA 481A Standard APPLICATIONS Output Buffers for 12 Bit 14 Bit and 16 Bit DACs ADC Buffers Cable Drivers Wideband Preamplifiers and Active Filters PRODUCT DESCRIPTION The AD744 is a fast settling precision FET input monolithic operational amplifier It offers the excellent dc characteristics of the AD711 BiFET family with enhanced settling slew rate and bandwidth The AD744 also offers the option of using custom compensation to achieve exceptional capacitive load drive capability The single pole response of the AD744 provides fast settling 500 ns to 0 01 This feature combined with its high dc preci sion makes it suitable for use as a buffer amplifier for 12 bit 14
2. DECOMPENSATION Figure 28 AD744 Simplified Schematic The slew rate and gain bandwidth product of the AD744 are in versely proportional to the value of the compensation capacitor Therefore when trying to maximize the speed of the amplifier the value of should be minimized can also be used to slow the amplifier to a point where the slew rate is perfectly symmetrical and well controlled Figure 29 sum marizes the effect of external compensation on slew rate and bandwidth SLEW V us GAIN BANDWIDTH MHz Ccomp PF Figure 29 Gain Bandwidth and Slew Rate vs The following section provides tables to show what values will provide the necessary compensation for given circuit configurations and capacitive loads In each case the recommended is a minimum value A larger Ccomp can always be used but slew rate and bandwidth performance will be degraded Figure 30 shows the AD744 configured as a unity gain voltage follower In this case a minimum compensation capacitor of 5 pF is necessary for stable operation Larger compensation ca pacitors can be used for driving larger capacitive loads Table I outlines recommended minimum values for based on the desired capacitive load It also gives the slew rate and band width
3. 0744 ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE Supply Voltage xs a emt Ree eA 18 V Internal Power Dissipation 500 mW Temperature Package l put Voltage eed 18 V Model Range Option Output Short Circuit Duration Indefinite AD744 N 0 C to 70 C N 8 Differential Input Voltage Vs and Vs AD744KN 0 C to 70 C N 8 Storage Temperature Range 65 C to 150 C AD744 R 0 C to 70 C SO 8 Storage Temperature Range 65 C to 125 C AD744KR 0 C to 70 SO 8 Operating Temperature Range AD744AQ 40 to 85 C Q 8 ADTAJK beta hematite A t E ue to nae AD744B0 40 C 85 Q8 AUT paana oP ERS AD744AH 40 to 85 C H 08A ZI AD744 CHIPS 0 C to 70 Die Lead Temperature Range Soldering 60 seconds 300 C AD744 R REEL 0 C to 70 Tape Reel 13 on above those listed under Absolute Maximum Ratings may cause perma AD 744JR REEL Taps Reel ol nent damage to the device This is a stress rating only functional operation of the AD744KR REEL 0 C to 70 C Tape Reel 13 device at these or any other conditions above those indicated in the operational AD744KR REEL 7 0 C to 70 C Tape Reel 7 section of this specification is not implied Exposure to absolute maximum rating AD744TA 883B 55 C to 125 C H 08 conditions for extended periods may affect device reliability Thermal Characteris
4. OUTLINE DIMENSIONS Dimensions shown in inches and mm TO 99 H Package 0 185 4 70 9321 REFERENCE PLANE 0 165 4 19 0 5 12 70 MIN EQUALLY 0 2 5 1 TYP 0 370 9 40 SS spaced 0 335 8 50 0 335 8 50 0 305 7 75 t b EE Se 8 LEADS ee 0 04 1 0 MAX e 0 019 0 48 0 034 0 86 XS ree INSULATION _ 0 016 0 41 DIA 0 028 0 71 045 1 1 0 05 1 27 MAX 1 lt 0 020 0 51 SEATING PLANE BOTTOM VIEW Mini DIP N Package 0 39 9 91 MAX 8 5 0 31 gt 0 25 7 87 6 35 ei 4 je PIN 1 9 10 254 0 035 0 01 0 165 0 01 0 89 0 25 4 19 0 25 EY 0 18 0 03 0 128 4 57 0 76 wl gt 0 011 0 003 0 018 0 003 0 033 SEATING 015 0 28 0 08 0 46 0 08 0 84 PLANE NOM Cerdip Q Package 0 005 0 13 0 055 1 35 MIN MAX 0 310 7 87 PIN 1 0 220 5 59 EX a 0 1 2 54 BSC 0 405 10 29 MAX 0 32 8 13 0 29 7 37 0 06 1 52 0 20 5 08 0 015 0 38 MAX Y Y 0 15 0 200 5 08 3 81 0 125 3 18 x MIN gt 0 015 0 38 SEATING 15 0 023 0 58 0 07 1 78 PLANE 0 008 0 20 0 014 0 36 0 03 0 76 Small Outline SO 8 Package 0 193 0 008 4 90 0 10 8 5 0 154 0 004 0 236 0 012 3 91 0 10 ri 4 6 00 0 20 LVUTUIL d PIN 1 Ab NIU 0 050 1 27 0 008 0 004 BSC 0 203 0 075 0 098 0 006 Y 2490 28 4 gt e
5. 4 gt j a 0 017 0 003 0 033 0 017 SEATING 0 011 0 002 PLANE 0 42 0 07 0 269 0 03 0 83 0 43 12 REV C C00833a 0 7 00 rev C PRINTED IN U S A
6. digital signal processing DSP front ends The AD744 is available in five performance grades The AD744J and AD744K are rated over the commercial temperature range of 0 C to 70 C The AD744A and AD744B are rated over the industrial temperature range of 40 C to 85 The AD744T is rated over the military temperature range of 55 C to 125 C and is available processed to MIL STD 883B Rev C The AD744 is available in an 8 lead plastic mini DIP 8 lead small outline 8 lead cerdip or TO 99 metal can PRODUCT HIGHLIGHTS 1 The AD744 is a high speed BiFET op amp that offers excel lent performance at competitive prices It outperforms the OPA602 OPA606 LF356 and LF400 2 The AD744 offers exceptional dynamic response It settles to 0 01 in 500 ns and has a 100 tested minimum slew rate of 50 V us AD744B 3 The combination of Analog Devices advanced processing technology laser wafer drift trimming and well matched ionimplanted JFETs provide outstanding dc precision Input offset voltage input bias current and input offset current are specified in the warmed up condition all are 100 tested One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 World Wide Web Site http www analog com Fax 781 326 8703 Analog Devices Inc 2000 AD 7144 SPEC CATI NS 25 C and 15 V dc unless otherwise noted AD744J AIS AD744K B T Model Conditions M
7. GAIN Vo 10V Ryoap 2 2 200 400 250 400 V mV Tmn to Tmax 100 100 V mV OUTPUT CHARACTERISTICS Voltage Rioap2 2 KQ 13 12 5 13 9 13 3 13 12 5 13 9 13 3 V Tun to Tmax 12 13 8 13 1 12 13 8 13 1 V Current Short Circuit 25 25 mA Capacitive Load Gain 1 1000 1000 pF POWER SUPPLY Rated Performance 15 15 V Operating Range t4 5 18 t4 5 18 V Quiescent Current 3 5 0 3 5 0 mA NOTES Input offset voltage specifications are guaranteed after 5 minutes of operation at TA 25 C PSRR test conditions 15 V Vs 12 V to 18 V and V 12 V to 18 V Vs 15 V Bias Current Specifications are guaranteed maximum at either input after 5 minutes of operation at T 25 C For higher temperature the current doubles every 10 C Gain 1 2 k 10 pF refer to Figure 25 gt Defined as voltage between inputs such that neither exceeds 10 V from ground Typically exceeding 14 1 V negative common mode voltage on either input results in an output phase reversal Open Loop Gain is specified with Vos both nulled and unnulled Capacitive load drive specified for Ccomp 20 pF with the device connected as shown in Figure 32 Under these conditions slew rate 14 and 0 01 settling time 1 5 us typical Refer to Table II for optimum compensation while driving a capacitive load Specifications subject to change without notice All min and max specifications are guaranteed 2 REV C
8. bit or 16 bit DACs and ADCs Furthermore the AD744 s low total harmonic distortion THD level of 0 0003 and gain band width product of 13 MHz make it an ideal amplifier for demanding audio applications It is also an excellent choice for use in active filters in 12 bit 14 bit and 16 bit data acquisition systems The AD744 is internally compensated for stable operation as a unity gain inverter or as a noninverting amplifier with a gain of two or greater External compensation may be applied to the AD744 for stable operation as a unity gain follower External compensation also allows the AD744 to drive 1000 pF capacitive loads slewing at 10 V us with full stability Alternatively external decompensation may be used to increase the gain bandwidth of the AD744 to over 200 MHz at high REV C Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices CONNECTION DIAGRAMS TO 99 H Package NULL COMPENSATION NOTE PIN 4 CONNECTED TO CASE 8 Lead Plastic Mini DIP N 8 Lead SOIC R Package and 8 Lead Cerdip Q Packages NULL NULL DECOMPENSATION COMPENSATION gains This makes the AD744 ideal for use as ac preamps in
9. 6 INPUT BIAS CURRENT pA GAIN BANDWIDTH PRODUCT MHz 14 SHORT CIRCUIT CURRENT LIMIT mA 12 10 m Teo 20 0 20 40 60 80 100 120 140 COMMON MODE VOLTAGE Volts ul M ERE 2 M ho 90 10051204190 VEMPERAT REC OC Figure 7 Input Bias Current vs Figure 8 Short Circuit Current Figure 9 Gain Bandwidth Common Mode Voltage Limit vs Temperature Product vs Temperature 4 REV C a 30 45 v 1 z 5 5 20 8 4 1 2 9 10 09 2 gt 9 2 a 5kt Rioao E OpF OR Croan z CIN 8 50pF V 40 20 N Load 10k 100k 10M 100M SHE UEM Hz Figure 10 Open Loop Gain and Phase Margin vs Frequency Ccomp 0 pF m 1 2 E o 2 tc Vs 15 Vout SINE WAVE INPU 25 C Resource 1k 100 1k 10k 100k 1M FREQUENCY Hz Figure 13 Common Mode and Power Supply Rejection vs Frequency OUTPUT VOLTAGE Volts p p OPEN LOOP GAIN dB 0744 120 115 a E gno 0 Za 8 OpF X 2105 NP 2g no lt OpF OR 1000pF 100 Ccomp 25pF 0 5 10 15 1M FREQUENCY Hs SUPPLY VOLTAGE VOLTS Figure 12 Open Loop Gain vs Supply Voltage Figure 11 Open Loop Gain and Phase Margin vs Frequency Ccomp 25 pF OUTPUT SWING FROM 0V TO VOLTS 100k 1M FREQUENCY Hz 0 2 0 3 0 4 0 5 SETTLING TIME p
10. GURE 21 Figure 36 A High Performance 3 Op Amp Instrumentation Amplifier Circuit REV C 0744 Table IV Performance Summary for the 3 Op Amp Instrumentation Amplifier Circuit Gain RG Bandwidth T Settle 0 01 1 NC 3 5 MHz 1 5 us 2 20 kQ 2 5 MHz 1 0 us 10 2 22 1 MHz 2 Us 100 202 Q 290 kHz 5 us Figure 37 The Pulse Response of the 3 Op Amp Instrumentation Amplifier Gain 1 Horizontal Scale 0 5 u V div Vertical Scale 5 V div Gain 10 Figure 38 Settling Time of the 3 Op Amp Instrumentation Amplifier Horizontal Scale 500 ns div Vertical Scale Pulse Input 5 V div Output Settling 1 mV div Minimizing Settling Time in Real World Applications An amplifier with a single pole or ideal integrator open loop frequency response will achieve the minimum possible settling time for any given unity gain bandwidth However when this ideal amplifier is used in a practical circuit the actual settling time is increased above the minimum value because of added time constants which are introduced due to additional capacitance on the amplifier s summing junction The following discussion will explain how to minimize this increase in settling time by the selection of the proper value for feedback capacitor If an op amp is modeled as an ideal integrator with a unity gain crossover frequency fo Equation 1 will accurately describe the small signal behavior of the circuit o
11. MHz 100 1Ok 101 100 760 kHz 76 MHz 100 100k 1001 1000 225 kHz 225 MHz REV C 9 0744 GAIN ADJUST BIPOLAR OFFSET Figure 34 10 V Voltage Output Bipolar DAC Using the AD744 as an Output Buffer HIGH SPEED OP AMP APPLICATIONS AND TECHNIQUES DAC Buffers I to V Converters Digital to analog converters which use bipolar transistors to switch currents into or out of their outputs can achieve very fast settling times The AD565A for example is specified to settle to 12 bits in less than 250 ns with a current output How ever in many applications a voltage output is desirable and it would be useful perhaps essential that this I to V conversion be accomplished without increasing the settling time or without degrading the accuracy of the DAC Figure 34 is a schematic of an AD565A DAC using an AD744 output buffer The 10 pF Cr gap capacitor compensates for the DAC s output capacitance plus the 5 5 pF amplifier input capacitance Figure 35 is an oscilloscope photo of the AD744 s output volt age with a 10 V to 0 V step applied this corresponds to an all 1s to all Os code change on the DAC Since the DAC is Figure 35 Upper Trace AD744 Output Voltage for a 10 V to 0 V Step Scale 5 mV div Lower Trace Logic Input Signal Scale 5 V div connected in the 20 V span mode 1 LSB is equal to 4 88 mV Output settling time for the AD565 AD744 combination is less than 500 n
12. RCUIT BOARD WITH GROUND PLANE Figure 25 Settling Time Test Circuit REV C The error signal is thus clamped twice once to prevent overloading amplifier A2 and then a second time to avoid overloading the oscilloscope preamp A Tektronix oscilloscope preamp type 7A26 was carefully chosen because it recovers from the approximately 0 4 V overload quickly enough to allow accurate measurement of the AD744 s 500 ns settling time Amplifier A2 is a very high speed FET input op amp it provides a voltage gain of 10 amplifying the error signal output of the AD744 under test Figure 26 Settling Characteristics 0 to 10 V Step Upper Trace Output of AD744 Under Test 5 V div Lower Trace Amplified Error Voltage 0 01 div Figure 27 Settling Characteristics 0 to 10 V Step Upper Trace Output of AD744 Under Test 5 V div Lower Trace Amplified Error Voltage 0 01 div 0744 EXTERNAL FREQUENCY COMPENSATION Even though the AD744 is useable without compensation in most applications it may be externally compensated for even more flexibility This is accomplished by connecting a capacitor between Pins 5 and 8 Figure 28 a simplified schematic of the AD744 shows where this capacitor is connected This feature is useful because it allows the AD744 to be used as a unity gain voltage follower It also enables the amplifier to drive capacitive loads up to 2000 pF and greater 2 NULL COMPENSATION 6 OUTPUT NULL
13. ed as an Inverting Amplifier 11 0744 In either case the capacitance Cx causes the system to go from a one pole to a two pole response this additional pole increases settling time by introducing peaking or ringing in the op amp s output If the value of Cx can be estimated with reasonable accu racy Equation 2 can be used to choose the correct value for a small capacitor which will optimize amplifier response If the value of Cx is not known Cy should be a variable capacitor As an aid to the designer the optimum value of Cj for one spe cific amplifier connection can be determined from the graph of Figure 41 This graph has been produced for the case where the AD744 is connected as in Figures 39 and 40 with a practical minimum value for Csrgay of 2 pF and a total Cx value of 7 5 pF The approximate value of Cy can be determined for almost any application by solving Equation 2 For example the AD565 AD744 circuit of Figure 34 constrains all the variables of Equa tion 2 Gy 3 25 R 10 kQ Fo 13 MHz and Cx 32 5 pF Therefore under these conditions 10 5 pF N a N Gy 1 5 a VALUE OF CAPACITOR C gap pF IN THIS REGION 5L Ci gap OpF Gy 21TO 0 100 1k 10k 100k VALUE OF RESISTOR Figure 41 Practical Values of C vs Resistance of R for Various Amplifier Noise Gains
14. f Figure 39 This circuit models an op amp connected as an I to V converter REV C Equation 1 would completely describe the output of the system if not for the op amp s finite slew rate and other nonlinear effects Even considering these effects the fine scale settling to 0 196 will be determined by the op amp s small signal behav lor Equation 1 Where Fo the op amp s unity gain crossover frequency Gy the noise gain of the circuit amp This Equation May Then Be Solved for Equation 2 2 G 2 RCx 2nFo 1 Gy T R2nFo C In these equations capacitance Cx is the total capacitance appear ing at the inverting terminal of the op amp When modeling an I to V converter application the Norton equivalent circuit of Figure 39 can be used directly Capacitance Cy is the total capaci tance of the output of the current source plus the input capacitance of the op amp which includes any stray capacitance at the op amp s input Ccomp OPTIONAL Figure 39 A Simplified Model of the AD744 Used as a Current to Voltage Converter When Ro and Io are replaced with their Thevenin Vp and Rn equivalents the general purpose inverting amplifier model of Figure 40 is created Here capacitor Cy represents the input capacitance of the AD744 5 5 pF plus any stray capacitance due to wiring and the type of IC package employed OPTIONAL Figure 40 A Simplified Model of the AD744 Us
15. in Typ Max Min Typ Max Unit INPUT OFFSET VOLTAGE Initial Offset 0 3 1 0 0 25 0 5 mV Offset Tmn to Tmax 2 1 0 mV vs Temp 5 20 5 10 uV C vs Supply 82 95 88 100 dB vs Supply Tmn to Tmax 82 88 dB Long Term Stability 15 15 uV month INPUT BIAS CURRENT Either Input Vom 0V 30 100 30 100 pA Either Input Tax Vem 0V LK 70 C 0 7 2 3 0 7 2 3 nA A B C 85 C 1 9 6 4 1 9 6 4 nA S T 125 C 31 102 31 102 nA Either Input Vom 10 V 40 150 40 150 pA Offset Current Vem 0V 20 50 10 50 pA Offset Current Tmax Vem 70V LK 70 C 0 4 1 1 0 2 1 1 nA 85 1 3 3 2 0 6 3 2 5 125 20 52 10 52 FREQUENCY RESPONSE Gain BW Small Signal G 1 8 13 9 13 MHz Full Power Response Vo 20 V p p 1 2 1 2 MHz Slew Rate Unity Gain G 1 45 75 50 75 V us Settling Time to 0 0196 G l 0 5 0 75 0 5 0 75 us Total Harmonic f 1 kHz Distortion R122 Vo 3 Vrms 0 0003 0 0003 INPUT IMPEDANCE Differential 3 x 1095 5 3 x 1095 5 Common Mode 3 x 1095 5 3 x 10 5 5 Q pF INPUT VOLTAGE RANGE Differential 20 20 V Common Mode Voltage 14 5 11 5 14 5 11 5 V Over Max Operating Range 11 13 11 13 V Common Mode Rejection Ratio Vom 10V 78 88 82 88 dB Tuan to Tmax 76 84 80 84 dB Vom 11 V 72 84 78 84 dB Tun to Tmax 70 80 74 80 dB INPUT VOLTAGE NOISE 0 1 to 10 Hz 2 2 uV p p f 10 Hz 45 45 nV VHz f 100 Hz 22 22 nV VHz f 1kHz 18 18 nV VHz f 10 kHz 16 16 nV VHz INPUT CURRENT NOISE f 1 kHz 0 01 0 01 pA VHz OPEN LOOP
16. s Figure 15 Output Swing and Error vs Settling Time Figure 14 Large Signal Frequency Response 70 7 VOLTS rms OUTPUT 3 VOLTS rms OUTPUT 120 130 1 FREQUENCY Hz Figure 16 Total Harmonic Distortion vs Frequency Circuit of Figure 20 G 10 REV C INPUT NOISE VOLTAGE nV VHz 01 02 03 04 05 06 07 08 09 10 INPUT ERROR SIGNAL Volts FREQUENCY Hz at Summing Junction Figure 17 Input Noise Voltage Spectral Density Figure 18 Slew Rate vs Input Error Signal 20 AD744 Typical Characteristics 1000 34 TO SPECTRUM ANALYZER ERROR SIGNAL UTPU 10kQ ERROR 11 100 E e dH ON LOW RTI DISTORTION rur Late IT Tt TT ae 4 Pott ft HH SETTLING TIME ps NOT CONNECTED J 100 CLOSED LOOP VOLTAGE GAIN Figure 19 Settling Time vs Closed Loop Voltage Gain SQUARE WAVE INPUT opr 3 9 Figure 22a Unity Gain Follower Figure 22c Unity Gain Follower Small Signal Pulse Response Ccomp 5 pF Figure 22b Unity Gain Follower Large Signal Pulse Response Ccomp 5 pF Figure 23c Unity Gain Inverter Small Figure 23b Unity Gain Inverter Large Signal Pulse Response Ccoyp 0 pF Signal Pulse Response Ccoyp 5 pF Figure 23a Unity Gain Inverter REV C 0744 POWER SUPPLY BYPASSING The power supply connections to the AD744 must maintain a low impedance to gro
17. s to within a 2 44 mV 1 2 LSB error band 10 A HIGH SPEED 3 OP AMP INSTRUMENTATION AMPLIFIER CIRCUIT The instrumentation amplifier circuit shown in Figure 36 can provide a range of gains from unity up to 1000 and higher The circuit bandwidth is 4 MHz at a gain of 1 and 750 kHz at a gain of 10 settling time for the entire circuit is less than 2 us to within 0 01 for a 10 V step G 10 While the AD744 is not stable with 100 negative feedback as when connected as a standard voltage follower phase margin and therefore stability at unity gain may be increased to an accept able level by placing the parallel combination of a resistor and a small lead capacitor between each amplifier s output and its inverting input terminal The only penalty associated with this method is a small band width reduction at low gains The optimum value for gap may be determined from the graph of Figure 41 This technique can be used in the circuit of Figure 36 to achieve stable opera tion at gains from unity to over 1000 CIRCUIT GAIN AD744 20 000 1 Rg 1 5pF 20pF TRIM FOR BEST SETTLING TIME AD744 VOLTRONICS SP20 TRIMMER CAPACITOR OR EQUIVALENT RATIO MATCHED 1 METAL FILM RESISTORS 15V V 2 PIN 7 7 Taf i 7 1pF 1pF 0 1pF ni E 5 M BACH AMPLIFIER 1pF 1pF 0 1 F 15V Vs dq PIN 4 preme FOR OPTIONAL OFFSET ADJUSTMENT TRIM A1 A3 USING TRIM PROCEDURE SHOWN IN FI
18. th with adjusted for minimum settling time Into large capacitive loads the AD744 s 25 mA output current limit sets the slew rate of the amplifier in V s equal to 0 025 amps divided by the value of Cy in Slew rate is specified into rated max C except for cases marked which are specified with a 50 pF load Due to manufacturing variations in the value of the internal it is recommended that the amplifier s response be optimized for the desired gain by using a 2 to 10 pF trimmer capacitor rather than using a fixed value R1 R2 O Vout OPTIONAL Ccomp SEETABLEI aS g Figure 32 AD744 Connected as an Inverting Amplifier 0 1pF O Vour NOT CONNECTED 2 10pF Operating at Gains of 1 or Greater SEE TABLE III 1pF 0 14 F Macy dx Using Decompensation to Extend the Gain Bandwidth Product Figure 33 Using the Decompensation Connection to When the AD744 is used in applications where the closed loop Extend Gain Bandwidth gain is greater than 10 gain bandwidth product may be enhanced by connecting a small capacitor between Pins 1 and 5 Figure 33 At low frequencies this capacitor cancels the effects of the Table III Performance Summary for the Circuit of Figure 33 chip s internal compensation capacitor effectively dec R1 R2 Gain Gain 3 dB Gain BW ting th lifier Deg ere O Follower Inverter Bandwidth Product 1k 10k 11 10 2 5 MHz 25
19. that will be achieved for each case Figure 30 AD744 Connected as a Unity Gain Voltage Follower Table I Recommended Values of vs Various Capacitive Loads Max 3 dB CrioaAD Slew Rate Bandwidth Gain pF pF Vlas MHz 1 50 5 37 6 5 1 150 10 25 4 3 1 2000 25 12 5 2 0 Figures 31 and 32 show the AD744 as a voltage follower with gain and as an inverting amplifier In these cases external compensation is not necessary for stable operation How ever compensation may be applied to drive capacitive loads above 50 pF Table II gives recommended values along with expected slew rates and bandwidths for a variety of load conditions and gains for the circuits in Figures 31 and 32 Clean O Vout OPTIONAL Ccomp SEE TABLE Il Figure 31 AD744 Connected as a Voltage Follower Operating at Gains of 2 or Greater 8 REV C 0744 Table II Recommended Values of vs Various Load Conditions for the Circuits of Figures 31 and 32 Max Slew 3 dB R1 R2 Gain Gain COMP CLEAD Rate Bandwidth Q Q Follower Inverter pF pF pF Vlas MHz 4 99k 4 99 k 2 1 50 0 7 75 2 5 4 99k 4 99 k 2 1 150 5 7 37 2 3 4 99k 4 90 k 2 1 1000 20 14 1 2 4 99k 4 90 k 2 1 gt 2000 25 12 5 1 0 4990 4 99k 11 10 270 0 75 1 2 4990 4 99k 11 10 390 2 50 0 85 4990 4 99 k 11 10 1000 5 372 0 60 NOTES Bandwid
20. tics 8 Lead Plastic Package 100 C Watt 33 C Watt 8 Lead Cerdip Package Oja 110 C Watt 22 C Watt 8 Lead Metal Can Package 0j 150 C Watt 65 C Watt 8 Lead SOIC Package Oja 160 C Watt 42 C Watt For supply voltages less than 18 V the absolute maximum input voltage is equal to the supply voltage N Plastic DIP SO Small Outline IC Q Cerdip H TO 99 Metal Can METALIZATION PHOTOGRAPH Contact factory for latest dimensions Dimensions shown in inches and mm 1 NULL COMPENSATION REV C 8 NULL COMPENSATION 744 BEB 7 Vs 6 OUTPUT 5 COMPENSATION AD744 Typical Characteristics 35 o N a N e 15 VOLTS SUPPLIES a INPUT VOLTAGE SWING Volts 2 OUTPUT VOLTAGE SWING Volts OUTPUT VOLTAGE SWING Volts p p ACC 10 ree VOLTAGE VOLTS SUBBLY VOLTAGE VOLTS LOAD RESISTANCE N Figure 1 Input Voltage Swing Figure 2 Output Voltage Swing Figure 3 Output Voltage Swing vs vs Supply Voltage vs Supply Voltage Load Resistance 0 Amps QUIESCENT CURRENT mA INPUT BIAS CURRENT Vom 60 40 20 0 20 40 60 80 100 120 140 EREU UENCY S He SUPPLY VOLTAGE Volts TEMPERATURE C Figure 4 Quiescent Current vs Figure 5 Input Bias Current vs Figure 6 Output Impedance vs Supply Voltage Temperature Frequency 26 24 22 20 OUTPUT CURRENT 18 7 1
21. und over a bandwidth of 10 MHz or more This is especially important when driving a significant resistive or capacitive load since all current delivered to the load comes from the power supplies Multiple high quality bypass capacitors are recommended for each power supply line in any critical application A 0 1 ceramic and a 1 uF electrolytic capacitor as shown in Figure 24 placed as close as possible to the ampli fier with short lead lengths to power supply common will assure adequate high frequency bypassing in most applica tions A minimum bypass capacitance of 0 1 uF should be used for any application 1pF 0 1pF vy Figure 24 Recommended Power Supply Bypassing MEASURING AD744 SETTLING TIME The photos of Figures 26 and 27 show the dynamic response of the AD744 while operating in the settling time test circuit of Figure 25 The input of the settling time fixture is driven by a flat top pulse generator The error signal output from the false summing node of A1 the AD744 under test is clamped ampli fied by op amp A2 and then clamped again TO TEKTRONIX I ADT 415V gt Vs 7A26 lis i L com OSCILLOSCOPE ul queri PREAMP It 15V NVs 5pF INPUT SECTION VIA LESS THAN 1 FT 500 COAXIAL CABLE 2060 Vennon 10 2X HP2835 0 2pF 0 8pF NULL PULSE GENERATOR DATA DYNAMICS 5109 OR EQUIVALENT IF Od amp F 1 0 a MED E NOTE USE CI

ANALOG DEVICES AD744 Precision 500 ns Settling BiFET Op Amp handbook

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