G-LINK GLT41316 DATA SHEET
Contents
1. Access Time from GAS Precharge 18 aaa Fast Page mode Read Write Cycle Time to 18 21 23 nt Fast Page mode Read Modify Write 48 63 65 Cycle Time GAS Precharge Time Fast Page mode 99 6 7 7 m RAS Pulse Width Fast Page mode Hie xa RAS Hold Time from CAS Precharge SERIO Access Time from OE c RI OE to OE to Delay Time to Delay Time fb Output Buffer Turn off Delay Time from SAKANG KANG eue JOE HodTme ren WE Hold Time Hidden Refresh Cycle kak ga Refresh Time 256cycles tee 4 G Link Technology Corporation G Link Technology Corporation Taiwan 2701Northwestern Parkway 2F No 12 R amp D Rd Il Science Based Industrial Park Santa Clara CA 95051 U S A Hsin Chu Taiwan R O C Notes 8 9 G LINK GLT41316 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE June 1998 Rev 2 An initial pause of 100us is required after power up followed by any 8 RAS only Refresh or CAS before RAS Refresh cycles to initialize the internal circuit Vin min Vit mis are reference levels for measuring timing of input signals Transition times are measured between Vinimin and Vii AC measurements assume 3ns Measured with an equivalent to 2 TTL loads and 100pF For read cycles the access time is defined as follows Input Conditions Access Time trap lt trap max2. tren lt trcpimax trapimax lt trap and trop lt tacpimax tacpimax lt trop trap max treomax indicate the points which the access time changes are not the limits of operation twes tcwp tawp are non restrictive operating parameters They are included in the data sheet as electric characteristics only If twcs gt twes min the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle If towo gt tewoimin tawo gt tawo and tawo gt tawoimin then the cycle is a read modify write cycle and the data output will contain the data read from the selected address If neither of the above conditions is satisfied the condition of the data out is indeterminate tar twor and are referenced to trap max toez max define the time at which the output achieves the open circuit condition and are not referenced to or lcRP min requirement should be applicable for RAS CAS cycle preceded by any cycles Either tacHmin OF tarH min must be satisfied for a read cycle 10 twpmin is applicable for late write cycle or read modify write cycle In early write cycles twcn min should be satisfied 11 This specification is referenced to CAS falling edge in early write cycles and to WE falling edge in late write or read modify write cycles G Link Technology Corporat
3. Access Time from Column Address ta 15 1 5 CAS to Output in Low Z Output Buffer Turn off Delay from CAS 25 Transition Time Rise and Fall RAS Precharge Time simum n x uu ES HE E as 10 preme EL E EAR Eu EU em a 25 pes ps CAS to RAS Precharge Time Bon Row Address Setup Time Row Address Hold Time 2 Column Address Setup Time Column Address Hold Time Column Address Hold Time Referenced to RAS Column Address Lead Time Referenced tra to RAS Read Command Setup Time tes O Read Command Hold Time Referenced trry to RAS Read Command Hold Time Referenced tracy to CAS WE Hold Time Referenced to CAS Write Command Hold Time Referenced twcn to RAS WE Pulse Width 5i 50 ih G Link Technology Corporation G Link Technology Corporation Taiwan 2701Northwestern Parkway 2F No 12 R amp D Rd Il Science Based Industrial Park Santa Clara CA 95051 U S A Hsin Chu Taiwan R O C G LINK GLT41316 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE June 1998 Rev 2 Parameter Ipag 30 ng no Se CET om ts 0 Data In Setup Time tos Data In Hold Time p RAS toWE e 47 sa goiter ee CAS Setup Time CAS before RAS Refresh CAS Hold Time CAS before RAS 10 Refresh RAS to CAS Precharge Time CAS Precharge Time CBR Counter Test z E Cycle
4. FPM SOJ 400mil 40L GLT41316 40J4 4016 Normal SOJ 400mil 40L GLT41316 45J4 45ns Normal FPM SOJ 400mil 401 GLT41316 30TC 0 Normal FPM TSOP 400mil 441 GLT41316 35TC 35ns Normal FPM TSOP 400mil 44L GLT41316 40TC 40ns Normal FPM TSOP 400mil 441 GLT41316 45TC 45ns Normal FPM TSOP 400mil 441 Parts Numbers Top Mark Definition GLT 4 13 16 40 J4 2 1 4 DRAM SRAM CONFIG SPEED PACKAGE 6 Standard 064 8K 04 x04 SRAM T PDIP 300mil SRAM 256 256K 08 x08 12 12ns TS TSOP Type 1 7 Cache SRAM 512 512K 16 x16 15 15ns TSOP Type Il 8 Synchronous 100 1M 32 x32 20 20ns PL PLCC Burst SRAM DRAM 70 70ns 300 SOP 10 1M C EDO DRAM FB 330mil SOP 11 1M C FPM 30 30ns 445 SOP 12 1M H EDO 35 35ns J3 300mil SOJ 13 1M H FPM 40 40ns J4 400mil SOJ 20 2M EDO 72 45 45ns P PDIP 600mil 21 2M FPM L 3 EN 50 50ns Q PQFP 40 4M EDO Mix Voltage 60 60ns TQ TQFP 41 4M FPM 80 8M EDO 81 8M FPM See note Note C CDROM H7HDD Example 1 GLT710008 15T 1Mbit 128Kx8 15ns SRAM PDIP 300mil Package type 2 GLT44016 40J4 4Mbit 256Kx16 40ns 5V DRAM SOJ 400mil Package type G Link Technology Corporation G Link Technology Corporation Taiwan 2701Northwestern Parkway 2F No 12 R amp D Rd Il Science Based Industrial Park Santa Clara CA 95051 U S A Hsin Chu Taiwan R O C 2
5. Refresh Current RAS CAS trac 30ns CAS Before RAS trac 35ns trac 40ns address cycling tpc tec min address cycling tac tnc min Standby Current CMOS gt Vcc 0 2V CAS gt Vcc 0 2V lacaomo 1 1 9e Output High Voltage 5 ____ 24 v Notes 1 Icc is dependent on output loading when the device output is selected Specified is measured with the output open 2 lcc is dependent upon the number of address transitions specified is measured with a maximum of one transition per address cycle in random Read Write and Fast Page Mode 3 Specified Vi is steady state operation During transitions Vi min may undershoot to 1 0V for a period to exceed 20ns All AC parameters are measured with Vi and Vina E Voc I G Link Technology Corporation G Link Technology Corporation Taiwan 2701Northwestern Parkway 2F No 12 R amp D Rd Il Science Based Industrial Park Santa Clara CA 95051 U S A Hsin Chu Taiwan R O C G LINK GLT41316 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE June 1998 Rev 2 AC Characteristics 0 C lt lt 70 See note 1 2 Test condition 5 0V 1 0 2 4 0 Poo PAA Parameter Read Write Cycle Time 65 Kasa 70 Read Midify Write Cycle Time tawo pol Access Time from RAS lo I Time from CAS
6. 07 Don t Care G Link Technology Corporation G Link Technology Corporation Taiwan 2701Northwestern Parkway 2F No 12 R amp D Ra Il Science Based Industrial in Chu Taiwan 11 G LINK GLT41316 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE June 1998 Rev 2 Read Modify Write Cycle RA 4 tcRP gt Address Mit Seo trw Ca 7222 OE Vit 77 TERI YA Don t Care Link ogy id orporatio G Link Technology Corporation Taiwan 2F No 12 R amp D Rd Il Science Based Industrial Park a a Cla bapor 95051 USA Hsin Chu Taiwan R O C G LINK GL141316 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE 998 Rev 2 Fast Page Read Cycle tRAsP trp RASV Ait EFE Address VH ROW Pip cou LUMN corum IA le K7 ViL YA ADDR ADDRESS 7 EW 225 Miz AA 14 ansa ELE M ums a LID VoH VALID Paa DQ VoL Ot DATA OUT DATA OUT Port 777 Don t care G eus Corporation G Link 2 Hat 2701Northwestern Parkway 2F No 12 R amp D Rd ial Park Santa se a CA 95051 U S A Hsin Chu Taiwan A G LINK GLT41316 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE June 1998 Rev 2 Fas 4 a SIER NOTE Dou RAS Vit tcRP CAS Ya iL E 7 hib Address V ROM FS ADDR pb Rr
7. 0 G LINK GLT41316 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE June 1998 Rev 2 Package Information 400mil 40 pin Small Outline J form Package SOJ 1 Unit 0 440 005 0 440 0 01 1 025 0 01 0 01 368 0 02 0 0 G Link Technology Corporation G Link Technology Corporation Taiwan 2701Northwestern Parkway 2F No 12 R amp D Rd Il Science Based Industrial Park Santa Clara CA 95051 U S A Hsin Chu Taiwan R O C 21 G LINK GLT41316 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE June 1998 Rev 2 40 44 Lead Thin Small Outline Package TSOP Type 11 0 400 0 004 0 039 0 002 Sao PO G Link Technology Corporation G Link Technology Corporation Taiwan 2701Northwestern Parkway 2F No 12 R amp D Rd Il Science Based Industrial Park Santa Clara CA 95051 U S A Hsin Chu Taiwan R O C 22
8. 454861741316 G LINK GLT41316 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE Features 65 536 words by 16 bits organization Fast access time and cycle time Dual WE Input Low power dissipation Read Modify Write RAS Only Refresh CAS Before RAS Refresh Hidden Refresh and Test Mode Capability 256 refresh cycles per 4ms Available in 40 pin 400 mil SOJ and 40 44 pin TSOP Il Single 5 0V 10 Power Supply All inputs and Outputs are TTL compatible x Fast Page Mode operation June 1998 Rev 2 Description The GLT41316 is a 65 536 x 16 bit high performance CMOS dynamic random access memory The GLT41316 offers Fast Page mode and has both BYTE WRITE and WORD WRITE access cycles via two WE pins The GLT41316 has symmetric address and accepts 256 cycle refresh in 4ms interval All inputs are TTL compatible Fast Page Mode operation allows random access up to 256x16 bits within a page with cycle times as short as 18ns The GLT41316 is best suited for graphics and DSP applications requiring high performance memories HIGHPERFORMANCE 1 30 35 40 45 Max RAS Access Time trac Max Column Address Access Time taa Min Fast Page Mode Cycle Time tpc Min Read Write Cycle Time tac Max CAS Access Time tcac G Link Technology Corporation 2701Northwestern Parkway Santa Clara CA 95051 U S A G Link Technology Corporation Taiwan 2F No 12 R amp D Rd Il Scienc
9. By salle dos RP MMMM tps l tu KZ mn UZI Don t Care G Link Technolo gy Corporation G Link Technolo gy Corporation Taiwan 2701Northwestern Parkway 2F No 12 R amp D Rd Il Science Based Industrial lara CA 95051 U S A i G LINK GLT41316 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE June 1998 Rev 2 Fast Page Mode Late Write Cycle RAS Vit CAS yi tres Address 7 RON Wf COLUMN E ADDRESS wiw dr 77777 a YEUX OU yea OC een G Link Technology Corporation G Link Technology Corporation Taiwan 2701Northwestern Parkway 2F No 12 R amp D Rd Il Science Based Industrial Park Santa Clara CA 95051 U S A Hsin Chu Taiwan R O C G LINK GLT41316 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE June 1998 Rev 2 Fast Page Read Modify Write Cycle NOTE Dour OPEN RAS Vit ee LE 2 52 p ECT m i nae ee ss 2 Sai n toED Wott ER OU DU MG AL ALID EE VALID VALI VALID VALID DATA OUT DATA IN DATA OUT DATA IN Don t Care G Link Technology Corporation G Link Technology Corporation Taiwan 2701Northwestern Parkway 2F No 12 R amp D Rd Il Science Based Industrial Park Santa Clara CA 95051 U S A Hsin Chu Taiwan R O C nN G LINK GLT41316 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE June 1998 Rev 2 CAS Before RAS Refresh Cycle trec tcrp mace VH Rema
10. e Based Industrial Park Hsin Chu Taiwan R O C G LINK GLT41316 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE June 1998 Rev 2 Pin Configuration GLT41316 TSOP Type Il SOJ Top View Top View Vec Lj 1 Vss 1 40 I Vss Doo O 2 DQ15 2 39 I 3 DQ 4 3 38 DQ2 O 4 DQ13 4 37 OO O 5 DQ 12 5 36 I DQ O 6 DQ 11 6 35 I DQs O 7 DQ10 7 34 O 8 DQ 9 8 33 I O 9 DQ 8 9 32 DQs NC O NC 10 31 NC O Mss UW O CAS 11 30 Vss a E RE 13 28 ED OE RAS O NC HU Ao Lj NC 14 27 OO NC A1 NC 15 26 LIU NC fan A2 A7 16 25 NC gt 17 24 A7 A4 A5 18 23 Vcc C Vss 2 HI pg LIII ss Pin Descriptions aa Inputs Row Address Strobe Column Address Strobe Read Upper Byte Write Enable Read Lower Byte Write Enable E Output Enable Do DQis Data Inputs Outputs 45V Power Suppl E s TC NC NoComnection G Link Technology Corporation G Link Technology Corporation Taiwan 2701Northwestern Parkway 2F No 12 R amp D Rd Il Science Based Industrial Park Santa Clara CA 95051 U S A Hsin Chu Taiwan R O C G LINK GLT41316 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE June 1998 Rev 2 Absolute Maximum Ratings Capacitance Ta 25 C 5 10 Vss 0V Operating Tempe
11. ion G Link Technology Corporation Taiwan 2701Northwestern Parkway 2F No 12 R amp D Rd Il Science Based Industrial Park Santa Clara CA 95051 U S A Hsin Chu Taiwan R O C G LINK GL141316 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE Ju ine 1998 Rev 2 Read Cycle Note Dn OPEN 2 m ct O a O 2 o U p 2 o I PS 1 pl B Lj S HA tasR ROW Addressy ADDRESS ht YY i MU CO ZA Da Vel OPEN moro Don t Care gt G Link Technology Corporation G Link Technology Corporation Taiwan 2701Northwestern Parkw 2F No 12 R amp D Rd Il Science Based Industrial Park Santa Clara CA 95051 U S A i i i NO G LINK GL141316 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE June 1998 Rev 2 Early Write Cycle NOTE Dour OPEN tcRP __ CAS Vit 7 7 Mm PCI Ta Address Vi XJ OUS IC pag L WCH AT ye Wt CC CCC tDHR pa 774 wn III Don t Care G Link Technolo gy Corporation G Link Technolo gy Corporation Taiwan 2701Northwestern Parkway 2F No 12 R amp D Rd Il Science Based Industrial Park G LINK GLT41316 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE June 1998 Rev 2 Late Write Cycle OE Controlled Write NOET Dour OPEN PC 5 l __ m Bm Address V KEKA EEK uil mm n c vt uu MMMM tDH Vit CX
12. rature T4 ambient Symbol Parameter Max Unit WAA AMA TAREN 0 C to 70 C Storage Temperature plastic 55 C to 150 C _ Address Input 5 pF Voltage Relative to Vss 1 0V to 7 0V Cno RAS CAS UW LW OE 7 pF Short Circuit Output Current 50mA Power 1 0W Data Input Output 7 pF Note Operation above Absolute Maximum Ratings Note Capacitance is sampled and not 100 tested can adversely affect device reliability Electrical Specifications e WE means UW and LW e All voltages are referenced to GND e After power up wait more than 100us and then execute eight CAS before RAS or RAS only refresh cycles as dummy cycles to initialize internal circuit Block Diagram xN Output BA Buffer 256 X16 Sense Sense Amplifier er ry Yo 5 Column Decoder Decoder Q lt 88 11 da T G Link Technology Corporation G Link Technology Corporation Taiwan 2701Northwestern Parkway 2F No 12 R amp D Rd Il Science Based Industrial Park Santa Clara CA 95051 U S A Hsin Chu Taiwan R O C G LINK GLT41316 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE June 1998 Rev 2 Truth Table GLT41316 gt ROW COL Data Out AD ROW COL Lower Byte Data In Upper Byte High Z OW COL Lower Byte High Z Upper Byte Data In ROW COL Data O
13. rk Address WE Don t care DQ Hi Z RAS Only Refresh Cycle paa Remark Address WE Dontcare DQ Hi Z G Link Technology Corporation G Link Technology Corporation Taiwan 2701Northwestern Parkway 2F No 12 R amp D Rd Il Science Based Industrial Park Santa Clara CA 95051 U S A Hsin Chu Taiwan R O C 2174 G LINK GLT41316 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE June 1998 Rev 2 Hidden Refresh Cycle Read tas de ee X 77 N 7 E Address Mit 77 ELIO ENZ 2 MMM WII MM tcac ee Da 8 open UN Don t Care G Link Technology Corporation G Link Technology Corporation Taiwan 2701Northwestern Parkway 2F No 12 R amp D Rd Il Science Based Industrial Park G LINK GLT41316 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE June 1998 Rev 2 Hidden Refresh Cycle Write NOTE Dour OPEN tRAS trp tras trp mp Al AA CASVE 777 7 7 en Address yj DEC 2 9 twcH wa o 4t ZZZ DA Mt LLL KOO Don t Care G Link Technology Corporation G Link Technology Corporation Taiwan 2701Northwestern Parkway 2F No 12 R amp D Rd Il Science Based Industrial Park Clara CA 95051 U S A i i G LINK GLT41316 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE June 1998 Rev 2 Ordering Information GLT41316 30J4 301 Normal FPM SOJ 400mil 40L GLT41316 35J4 35ns Normal
14. ut Data In ROW COL Data Out Data Out ROW COL Data In Data In Fast Page H gt L L2H ROW COL Mode Read Write H gt L L H Hidden ROW COL Refresh RAS Only Refresh CBR Refresh Notes 1 These READ cycles are always WORD READ cycles Write Word Early Write Write Lower Byte Early Read Write Fast Page Mode Read Fast Page Mode Write ROW COL EN L L 2 These WRITE cycles may also be BYTE READ cycles either UW or LW active 3 EARLY WRITE only G Link Technology Corporation G Link Technology Corporation Taiwan 2701Northwestern Parkway 2F No 12 R amp D Rd Il Science Based Industrial Park Santa Clara CA 95051 U S A Hsin Chu Taiwan R O C G LINK GLT41316 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE June 1998 Rev 2 and Operating Characteristics 1 2 0 C to 70 C EL 5V 10 Vss 0V unless otherwise specified bas Bess d dk Time d Leakage Current OV lt Vy 5 5V 10 10 uA any input pin All other pins not under test 0V for High Z State Output is disabled Hiz Operating Current trac 30ns Random READ WRITE trac 3515 trac 4005 penes Current TTL RAS CAS at Vu iE m other inputs 2Vss_ Refresh Current trac 30ns RAS Only Rae sae cans _ trac 40ns tnc tac min Operating Current DAG AG trac 30ns EDO Page Mode Aah Mik 225 trac 35ns trac 40ns trac 45ns
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G LINK GLT41316 DATA SHEET