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FLEX 8000 Programmable Logic Device Family handbook

1. Pin Name 225 Pin 232 Pin 240 Pin 240 Pin 280 Pin 304 Pin BGA PGA PQFP PQFP PGA R FP EPF8820A EPF81188A EPF81188A EPF81500A EPF81500A EPF81500A nSP 2 A15 C14 237 237 VV1 304 MSELO 2 B14 G15 21 19 N1 26 MSEL1 2 R15 L15 40 38 H3 51 nSTATUS 2 P2 L3 141 142 G19 178 nCONFIG 2 R1 R4 117 120 B18 152 DCLK 2 B2 C4 184 183 U18 230 CONF DONE 2 1A1 G3 160 161 M16 204 ns L4 P1 133 134 F18 167 nRS K5 N1 137 138 G18 171 RDCLK F1 G2 158 159 M17 202 nCS D1 E2 166 167 N16 212 CS C1 E3 169 170 N18 215 RDYnBUSY J3 K2 146 147 J17 183 CLKUSR G2 H2 155 156 K19 199 ADD17 M14 R15 58 56 E3 73 ADD16 L12 T17 56 54 E2 71 ADD15 M15 P15 54 52 F4 69 ADD14 L13 M14 47 45 G1 60 ADD13 L14 M15 45 43 H2 58 ADD12 K13 M16 43 41 H1 56 ADD11 K15 K15 36 34 J3 47 ADD10 J13 K17 34 32 K3 45 ADD9 J15 J14 32 30 K4 43 ADD8 G14 J15 29 27 L1 34 ADD7 G13 H17 27 25 L2 32 ADD6 G11 H15 25 23 M1 30 ADD5 F14 F16 18 16 N2 20 ADD4 E13 F15 16 14 N3 18 ADD3 D15 F14 14 12 N4 16 ADD2 D14 D15 7 5 U1 8 ADD1 E12 B17 5 3 U2 6 ADDO C15 C15 3 1 V1 4 DATA A7 A7 205 199 W13 254 DATA6 D7 D8 203 197 W14 252 DATA5 A6 B7 200 196 W15 250 DATA4 A5 C7 198 194 W16 248 58 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Table 17 FLEX 8000 225 232 240 280 amp 304 Pin Package Pin Outs Part 2 of 3
2. Pin Name 160 Pin 160 Pin 192 Pin PGA 208 Pin 208 Pin 208 Pin P FP P FP EPF8636A P FP P FP P FP EPF8452A EFP8636A EPF8820A EPF8636A 7 EPF8820A 7 EPF81188A 7 nSP 2 120 1 R15 207 207 5 MSELO 2 117 3 n5 04 4 21 MSEL1 2 84 nSTATUS 2 37 nCONFIG 2 40 DCLK 2 1 CONF_DONE 4 2 nWS 30 nRS 71 RDCLK 73 ncs 29 cs 27 RDYnBUSY 1125 CLKUSR 76 ADD17 78 ADD16 91 ADD15 92 ADD14 94 ADD13 95 ADD12 96 ADD11 97 ADD10 98 ADD9 99 ADD8 101 ADD7 102 ADD6 103 ADD5 104 ADD4 105 ADD3 106 ADD2 109 ADD1 110 ADDO 123 DATA7 144 DATA6 150 56 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Table 16 FLEX 8000 160 192 amp 208 Pin Package Pin Outs Part 2 of 2 Pin Name 160 Pin 160 Pin 192 Pin PGA 208 Pin 208 Pin 208 Pin P FP PQFP EPF8636A PQFP P FP P FP EPF8452A EFP8636A EPF8820A 1 EPF8636A 7 EPF8820A 7 EPF81188A 7 DATA5 152 129 F17 169 174 172 DATA4 170 DATA3 168 DATA2 166 DATA1 163 DATAO 161 SDOUT 3 119 TDI 4 TDO 4 95 B9 TCK 4 57 U8 74 30 TMS 4 59 U7 76 32 TRST 6 40 R3 54 54 Dedicated 5 36 85 116 6 35 87 116 1A5 U5 U13 17 45 112 17 36 121 113 41 116 nputs 8 A13 150 140 146 VCCINT 21 41 53 67 14 5 26 85 C8 C9 C10 15 6 33 110 15 6 27 48 14 20 35 48 5 0 V 80 81
3. Symbol Parameter Conditions Min Typ Max Unit Vin High level input voltage 2 0 Vecint V 0 3 Vi Low level input voltage 0 3 0 8 V VoH 5 0 V high level TTL output lou 4 mA DC Note 7 2 4 V voltage Vocio 4 75 V 3 3 V high level TTL output lon 4 mA DC Note 7 2 4 V voltage Vccio 3 00 V 3 3 V high level CMOS output lop 0 1 mA DC Note 7 Vccio 0 2 V voltage Vccio 3 00 V VoL 5 0 V low level TTL output voltage lo 12 mA DC Note 7 0 45 V Vccio 4 75 V 3 3 V low level TTL output voltage lox 12 mA DC Note 7 0 45 V Vccio 3 00 V 3 3 V low level CMOS output lo 0 1 mA DC Note 7 0 2 V voltage Vccio 3 00 V li Input leakage current Vi Vcc or ground 10 10 HA loz Tri state output off state current Vo Vec or ground 40 40 HA loco Voc supply current standby Vi ground no load 0 5 10 mA FLEX 8000 5 0 V Device Capacitance Note 8 Symbol Parameter Conditions Min Max Unit Cin Input capacitance Vin 0 V f 1 0 MHz 10 pF Cout Output capacitance Vout 0 V f 1 0 MHz 10 pF 28 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Notes to tables 1 Seethe Operating Reguirements for Altera Devices Data Sheet in this data book 2 Minimum DC input is 0 3 V During transitions the inputs may undershoot to 2 0 V or overshoot to 7 0 V for periods shorter than 20 ns under no load conditions 3 The max
4. Pin Name 225 Pin 232 Pin 240 Pin 240 Pin 280 Pin 304 Pin BGA PGA P FP P FP PGA R FP EPF8820A EPF81188A EPF81188A EPF81500A EPF81500A EPF81500A DATA3 B5 D7 196 193 W17 246 DATA2 E6 B5 194 190 V16 243 DATA1 D5 A3 191 189 U16 241 DATAO C4 A2 189 187 V17 239 SDOUT 3 K1 N2 135 136 F19 169 TDI F15 4 63 12 B1 12 80 12 TDO J2 4 117 12 C17 12 149 12 TCK J14 4 116 12 A19 12 148 12 TMS J12 4 64 12 C2 12 81 12 TRST 6 P14 115 A18 145 Dedicated Inputs F4 L1 K12 C1 C17 R1 110 51 130 18 49 131 F1 F16 P3 112 64 164 8 E15 R17 171 172 P19 217 VCCINT F5 F10 ET E4 H4 L4 20 42 64 66 18 40 60 62 B17 D3 D15 124 54 77 5 0 V L2 K4 M12 P12 L14 114 128 150 91 114 129 E8 E10 E12 144 79 115 P15 H13 H14 E14 172 236 151 173 209 E14 R7 R9 162 191 218 H14 B15 R14 U1 236 R11 R13 266 301 C13 R14 T14 VCCIO H3 H2 P6 N10 M13 19 41 65 81 117 39 61 78 D14 E7 E9 122 53 78 99 5 0 V or 3 3 V R6 P10 N10 M5 K13 K5 199 116 140 194 108 130 E11 E13 R6 1119 137 163 R14 N13 H13 H5 F5 1162 186 202 1152 174 191 R8 R10 R12 193 220 244 H15 H12 E10 E8 N8 1220 235 205 221 235 T13 T15 262 282 300 D12 A14 F13 B10 A10 B6 C6 A2 C3 M4 R2 GND B1 D4 E14 A1 D6 E11 18 9 30 31 16 7 28 29 1D4 D5 D16 19 11 36 38 F
5. 38 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet EPF8282AV Logic Element Timing Parameters Symbol A 3 Speed Grade A 4 Speed Grade Unit Min Max Min Max LUT 3 2 7 3 ns CLUT 0 0 14 ns RLUT 1 5 5 1 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns EPF8282AV External Timing Parameters Symbol A 3 Speed Grade A 4 Speed Grade Unit Min Max Min Max DRR 24 8 50 1 ns topH 1 0 1 0 ns Altera Corporation 39 FLEX 8000 Programmable Logic Device Family Data Sheet EPF8452A Internal Timing Parameters EPF8452A I O Element Timing Parameters Symbol A 2 Speed Grade A 3 Speed Grade A 4 Speed Grade Unit Min Max Min Max Min Max tiop 0 7 0 8 0 9 ns 1 9 ns loE 1 9 ns tioco 1 1 0 ns OCOMB 0 1 ns tiosu ns loH ns tiocLR 1 2 ns 1 7 ns 1 7 ns ns 5 2 ns 1 8 ns 1 8 ns ns zx3 4 9 5 1 5 3 ns EPF8452A Interconnect Timing Parameters Symbol A 2 Speed Grade A 3 Speed Grade A 4 Speed Grade Unit Min Max Min Max Min Max li ABCASC 0 3 0 4 0 4 ns LABCARRY 0 3 0 4 0 4 ns LOCAL 0 5 0 5 0 7 ns trow 5 0 5 0 5 0 ns coL 3 0 3 0 3 0 ns DIN C 5 0 5 0 5 5 ns DIN D 7 0 7 0 7 5 ns DIN IO 5 0 5 0 5 5 ns 40 Altera Corporation FLEX 8000 Pr
6. Table 9 FLEX 8000 LE Timing Parameters Note 1 Symbol Parameter LUT LUT delay for data in GLUT LUT delay for carry in RLUT LUT delay for LE register feedback Cascade gate delay Cascade chain routing delay Carry in to carry out delay Data in to carry out delay LE register feedback to carry out delay LE register control signal delay LE register clock high time LE register clock lovv time LE register clock to output delay Combinatorial delay LE register setup time before clock LE register recovery time after asynchronous preset clear or load LE register hold time after clock LE register preset delay CLR LE register clear delay Table 10 FLEX 8000 Interconnect Timing Parameters Oo Note 1 Symbol Parameter tL ABCASC Cascade delay between LEs in different LABs ti ABCARRY Carry delay between LEs in different LABs LOCAL LAB local interconnect delay trow Row interconnect routing delay Note 4 coL Column interconnect routing delay DIN C Dedicated input to LE control delay DIN D Dedicated input to LE data delay Note 4 DIN IO Dedicated input to IOE control delay Table 11 FLEX 8000 External Reference Timing Characteristics Note 5 Symbol Parameter torr Register to register delay via 4 LEs 3 row interconnects and 4 local interconnects Note 6 ODH Output data hold time after clock Note 7
7. XZ skejaq skejaq Kejaq nd no JeisiDeu O I erea indino exe Jou05 IXZ 4190 181s16ey O I i Zx Hol i 00 nsol i zao swooo 140 ooo lt co Aejag Bunnoy osvo epeose5 1 Hi 9 joujuoD Jeisibou ns 09 EH Jejsibeu skejaq Ael q eie5 Aejag 101 peoseo 31 snore 31 snore WO UJ opeoseo wo Uj Aue9 MOHj 35 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet EPF8282A Internal Timing Parameters EPF8282A I O Element Timing Parameters Symbol A 2 Speed Grade A 3 Speed Grade A 4 Speed Grade Unit Min Max Min Max Min Max tiop 0 7 0 8 0 9 ns tioc 1 7 1 8 1 9 ns DE 1 7 1 8 1 9 ns tloco 1 0 1 0 1 0 ns tiocomB 0 3 0 2 0 1 ns tiosu 1 4 1 6 1 8 ns tion 0 0 0 0 0 0 ns OCLR 1 2 12 1 2 ns tin 1 5 1 6 1 7 ns top1 1 1 1 4 1 7 ns oD2 gt E ns tops 4 6 4 9 5 2 ns tyz 1 4 1 6 1 8 ns zx 1 4 1 6 1 8 ns zxe ns zx3 4 9 5 1 5 3 ns EPF8282A Interconnect Timing Parameters Symbol A 2 Speed Grade A 3 Speed Grade A 4 Speed Grade Unit Min Max Min Max Min Max LABCASC 0 3 0 3 0 4 ns tL ABCARRY 0 3 0 3 0 4 ns LOCAL 0 5 0 6 0 8 ns ROW 4 2 4 2 4 2 ns COL 2 5 2 5 2 5 ns
8. 13 23 53 73 13 24 53 19 26 82 1C3 D14 14 33 94 Inputs 8 73 73 74 99 N2 R15 113 VCCINT 17 38 59 117 38 59 16 20 37 56 19 32 49 18 28 70 B2 C4 D3 13 24 46 80 80 70 87 59 82 90 111 D8 D12 192 114 G3 G12 1160 H4 H13 J3 J12 M4 M7 M9 M13 N12 VCCIO 16 40 60 23 47 57 69 91 69 79 112 122 104 127 141 137 149 159 54 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Table 15 FLEX 8000 84 100 144 amp 160 Pin Package Pin Outs Part 3 of 3 Pin Name 84 Pin 84 Pin 100 Pin 100 Pin 144 Pin 160 Pin 160 Pin PLCC PLCC T FP T FP T FP PGA P FP EPF8282A EPF8452A EPF8282A EPF8452A EPF8820A EPF8452A EPF8820A EPF8636A EPF8282AV Note 1 GND 5 26 47 68 15 26 47 12 13 30 44 119 44 69 1 7 17 27 C12 D4 12 13 34 68 52 63 80 194 39 54 D7 D9 35 51 63 94 80 81 D13 G4 175 80 83 100 101 G13 H3 193 103 128 142 H12 J4 115 126 J13 L1 131 143 M3 M8 155 M12 M15 N4 No Connect 2 6 13 30 N C 37 42 43 50 52 56 63 80 87 92 93 99 Total User I O Pins 64 64 74 64 108 116 116 Altera Corporation 55 FLEX 8000 Programmable Logic Device Family Data Sheet Table 16 FLEX 8000 160 192 amp 208 Pin Package Pin Outs Part 1 of 2
9. 2 This pin is a dedicated pin and is not available as a user I O pin 3 SDOUT will drive out during configuration After configuration it may be used as a user I O pin By default the MAX PLUS II software will not use SDOUT as a user I O pin the user can override the MAX PLUS II software and use SDOUT as a user I O pin If the device is not configured to use the JTAG BST circuitry this pin is available as a user I O pin JTAG pins are available for EPF8636A devices only These pins are dedicated user I O pins TRST is a dedicated input pin for JTAG use This pin must be grounded if JTAG BST is not used Pin52isa Vcc pin on EPF8452A devices only Unused dedicated inputs should be tied to ground on the board SDOUT does not exist in the EPF8636GC192 device 10 These pins are no connect N C pins for EPF8636A devices only They are user I O pins in EPF8820A devices 11 EPF8636A devices have 132 user I O pins EPF8820A devices have 148 user I O pins not used TRST must be grounded TMS TDI and TCK should be tied to Vcc The information contained in the FLEX 8000 Programmable Logic Device Family Data Sheet version 9 11 supersedes information published in previous versions Revision History Version 9 11 Change The FLEX 8000 Programmable Logic Device Family Data Sheet version 9 11 contains the following change Figure 14 has been updated for accuracy 12 For EPF81500A devices these pins are dedicated JTAG pins and ar
10. Carry In 4 Input LUT Cascade In LUT LE Out Cascade Out Cascade Out CLRN LE Out Carry Out Carry In Cascade In PRN 3 Input D Q LE Out LUT h b 3 nput SER N LUT Carry Out Cascade Out Carry In PRN 3 Input 5 LUT D Q LE Out e gt CLRN 3 Input LUT Carry Out Cascade Out 11 FLEX 8000 Programmable Logic Device Family Data Sheet 12 Normal Mode The normal mode is suitable for general logic applications and wide decoding functions that can take advantage of a cascade chain In normal mode four data inputs from the LAB local interconnect and the carry in signal are the inputs to a 4 input LUT Using a configurable SRAM bit the MAX PLUS II Compiler automatically selects the carry in or the DATA3 signal as an input The LUT output can be combined with the cascade in signal to form a cascade chain through the cascade out signal The LE Out signal the data output of the LE is either the combinatorial output of the LUT and cascade chain or the data output Q of the programmable register Arithmetic Mode The arithmetic mode offers two 3 input LUTs that are ideal for implementing adders accumulators and comparators One LUT provides a 3 bit function the other generates a carry bit As shown in Figure 6 the first LUT uses
11. DIN C 5 0 5 0 5 5 ns DIN D 7 2 7 2 7 2 ns DIN IO 5 0 5 0 5 5 ns 36 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet EPF8282A LE Timing Parameters Symbol A 2 Speed Grade A 3 Speed Grade A 4 Speed Grade Unit Min Max Min Max Min Max 2 5 3 2 ns 0 0 0 0 ns 1 1 1 5 ns 0 0 0 0 ns 0 7 0 9 ns 0 5 0 6 ns 0 5 0 7 ns 1 1 1 5 ns 2 0 2 5 ns 4 0 ns 4 0 ns 0 5 0 6 ns 0 5 0 6 ns 1 2 ns 1 5 ns PRE 0 6 0 7 0 8 ns tein 0 6 0 7 0 8 ns EPF8282A External Timing Parameters Symbol A 2 Speed Grade A 3 Speed Grade A 4 Speed Grade Unit Min Max Min Max Min Max tpRR 15 8 19 8 24 8 ns ODH 1 0 1 0 1 0 ns Altera Corporation 37 FLEX 8000 Programmable Logic Device Family Data Sheet EPF8282AV Internal Timing Parameters EPF8282AV 1 0 Element Timing Parameters A 3 Speed Grade A 4 Speed Grade Unit Max Min Max 0 9 2 2 ns 1 9 2 0 ns 1 9 2 0 ns 1 0 2 0 ns 0 1 0 0 ns 2 8 ns 0 2 ns 1 2 2 3 ns 1 7 3 4 ns 1 7 4 1 ns ns 5 2 7 1 ns 1 8 4 3 ns 1 8 4 3 ns ns 5 3 8 3 ns EPF8282AV Interconnect Timing Parameters Symbol A 3 Speed Grade A 4 Speed Grade Unit Min Max Min Max LABCASC 13 ns tLABCARRY 0 8 ns LOCAL 1 5 ns trow 6 3 ns tcoL 3 8 ns DIN C 8 0 ns DIN D 10 8 ns DIN IO 9 0 ns
12. asynchronous modes which are chosen during design entry LPM functions that use registers will automatically use the correct asynchronous mode See Figure 7 Clear only Preset only Clear and preset Load with clear Load with preset Load without clear or preset Altera Corporation 13 FLEX 8000 Programmable Logic Device Family Data Sheet Figure 7 FLEX 8000 LE Asynchronous Clear amp Preset Modes Asynchronous Clear Asynchronous Preset Asynchronous Clear amp Preset VCC LABCTRL or LABCTRL1 p LABCTRL2 PRN PRN D Q D Q o CLRN CLRN LABCTRL1 or LABCTRL2 LABCTRL2 Asynchronous Load with Clear LABCTRL1 NOT Asynchronous D e Load b l DATA3 Data D Q NoT CLRN LABCTRL2 Clear Asynchronous Load with Preset LABCTRL1 NOT Asynchronous Load e 34 LABCTRL2 Preset DATAS3 e Data CLRN Asynchronous Load without Clear or Preset NOT LABCTRL1 Asynchronous be p Load L DATA3 D PRN Q Data P NOT 14 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Altera Corporation Asynchronous Clear A register is cleared by one of the two LABCTRL signals When the CLRn port receives a low signal the register is set to zero Asynchronous Preset An asynchronous preset is implemented as either an asynchronous load or an asy
13. with new programming data that is loaded into the device Real time reconfiguration is performed by forcing the device into command mode with a device pin loading different programming data reinitializing the device and resuming user mode operation The entire reconfiguration process requires less than 100 ms and can be used to dynamically reconfigure an entire system In field upgrades can be performed by distributing new configuration files Configuration Schemes The configuration data for a FLEX 8000 device can be loaded with one of six configuration schemes chosen on the basis of the target application Both active and passive schemes are available In the active configuration schemes the FLEX 8000 device functions as the controller directing the loading operation controlling external EPROM devices and completing the loading process The clock source for all active configuration schemes is an oscillator on the FLEX 8000 device that operates between 2 MHz and 6 MHz In the passive configuration schemes an external controller guides the FLEX 8000 device Table 14 shows the data source for each of the six configuration schemes Table 14 Data Source for Configuration Configuration Scheme Acronym Data Source Active serial AS Altera Configuration EPROM Active parallel up APU Parallel EPROM Active parallel down APD Parallel EPROM Passive serial PS Serial data path Passive parallel synchronous PPS Intelligent host Pas
14. 100 121 1106 R8 R9 R10 1137 119 141 50 102 114 133 147 160 R14 131 147 VCCIO 25 41 60 70 D3 D4 D9 132 55 78 91 126 55 69 87 13 19 34 49 5 0 V or 80 107 121 1D14 D15 G4 1102 138 159 102 131 159 169 87 106 3 3 V 140 149 160 1614 L4 L14 1182 193 206 173 191 206 1123 140 156 P4 P9 P14 174 192 GND 13 14 28 46 115 16 36 37 C4 D7 D8 19 20 46 47 115 16 37 38 111 12 27 28 60 75 93 107 145 51 75 84 1 D10 D11 H4 160 67 96 60 78 96 42 43 60 78 108 126 140 186 96 97 H14 K4 K14 1109 111 124 109 110 120 196 105 115 155 117 126 131 P7 P8 P10 125 151 164 130 142 152 122 132 139 154 P11 171 200 164 182 200 1148 155 159 165 183 201 No Connect 12 3 38 39 70 12 39 82 119 C6 C12 C13 11 2 3 16 17 11 2 3 50 51 11 2 51 52 53 N C 82 83 118 119 C14 E3 E15 118 25 26 27 152 53 104 154 103 104 148 F3 J3 J4 34 35 36 50 105 106 107 157 158 207 J14 J15 N3 51 52 53 154 155 156 208 N15 P3 P15 1104 105 106 157 208 R4 10 107 121 122 123 130 131 132 139 140 141 154 155 156 157 208 Total User 116 114 132 148 11 1132 148 144 I O Pins Altera Corporation 57 FLEX 8000 Programmable Logic Device Family Data Sheet Table 17 FLEX 8000 225 232 240 280 amp 304 Pin Package Pin Outs Part 1 of 3
15. Channels per Row Columns Channels per Column EPF8282A 2 168 13 16 EPF8282AV EPF8452A 2 168 21 16 EPF8636A 3 168 21 16 EPF8820A 4 168 21 16 EPF81188A 6 168 21 16 EPF81500A 6 216 27 16 Figure 9 shows the interconnection of four adjacent LABs with row column and local interconnects as well as the associated cascade and carry chains 17 FLEX 8000 Programmable Logic Device Family Data Sheet Figure 9 FLEX 8000 Device Interconnect Resources Each LAB is named according to its physical row A B C etc and column 1 2 3 etc position within the device oE IOE See Figure 11 for details Column EL See Figure 10 Interconnect Row amp 277 for details Interconnect M L P s 1 i I NERE rgi 1 _ I sen I 8 IOE y A Y A A rog 8 x Z bs D d LAB LAB A2 Al gt b 1 i m zn 1 8 IOE Y A Y A A re IOE 8 L3 LAB LAB B1 gt B2 gt LAB Local hb N m Interconnect ru E Cascade amp Carry Chain oE oE IOE IOE 1 0 Element 18 An IOE contains a bidirectional I O buffer and a register that can be used either as an input register for external data that requires a fast setup time or as an output register for data that requires fast clock to output performance IOEs can be used as input output or
16. Devices except EPF8282A 200 mi a o Vecinr 5 0 V Room Temperature o lo Output Current mA Typ lo Output Current mA Typ Vo Output Voltage V 30 200 150 o o a o Vecint 5 0 V I Vccio 3 3 V Room Temperature Vo Output Voltage V Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Figure 17 Output Drive Characteristics of EPF8282A Devices with 5 0 V V cio 150 loL 120 Voc 5 0 V Room Temperature 90 60 lol Output Current mA Typ Vo Output Voltage V Figure 18 shows the typical output drive characteristics of EPF8282AV devices Figure 18 Output Drive Characteristics of EPF8282AV Devices 100 75 50 Vec 3 3 V Room Temperature 25 lol Output Current mA Typ Vo Output Voltage V Altera Corporation 31 FLEX 8000 Programmable Logic Device Family Data Sheet Timi ng Model The continuous high performance FastTrack Interconnect routing structure ensures predictable performance and accurate simulation and timing analysis This predictable performance contrasts with that of FPGAs which use a segmented connection scheme and hence have unpredictable performance Timing simulation and delay prediction are available with the MAX PLUS II Simulator and Timing Analyzer or with industry standard EDA tools The Simulator offers both pre synthesis functional simu
17. IOE can drive up to two row 7 V V N channels Row Interconnect 168 216 Each IOE is driven by an n to 1 multiplexer Note 1 n 13 for EPF8282A and EPF8282AV devices n 21 for EPF8452A EPF8636A EPF8820A and EPF81188A devices n 27 for EPF81500A devices Column to IOE Connections Two IOEs are located at the top and bottom of the column channels see Figure 12 When an IOE is used as an input it can drive up to two separate column channels The output signal to an IOE can choose from 8 of the 16 column channels through an 8 to 1 multiplexer 20 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Altera Corporation Figure 12 FLEX 8000 Column to IOE Connections Each IOE is Each IOE can drive driven by an up to two column 8 to 1 Signals multiplexer Column Interconnect In addition to general purpose I O pins FLEX 8000 devices have four dedicated input pins These dedicated inputs provide low skew device wide signal distribution and are typically used for global clock clear and preset control signals The signals from the dedicated inputs are available as control signals for all LABs and I O elements in the device The dedicated inputs can also be used as general purpose data inputs because they can feed the local interconnect of each LAB in the device Signals enter the FLEX 8000 device either from the I O pin
18. and the interconnect including the row and column FastTrack Interconnect LAB local interconnect and carry and cascade interconnect paths Each parameter shown in Figure 19 is expressed as a worst case value in the Timing Parameters tables in this data sheet Hand calculations that use the FLEX 8000 timing model and these timing parameters can be used to estimate FLEX 8000 device performance Timing simulation or timing analysis after compilation is required to determine the final worst case performance Table 12 summarizes the interconnect paths shown in Figure 19 ia p For more information on timing parameters go to Application Note 76 Understanding FLEX 8000 Timing in this data book Table 12 FLEX 8000 Timing Model Interconnect Paths Source Destination Total Delay LE Out LE in same LAB li OCAL LE Out LE in same row different LAB trow LOCAL LE Out LE in different row tco trow LOCAL LE Out IOE on column coL LE Out IOE on row trow IOE on row LE in same row ROW LOCAL IOE on column Any LE tco trow LOCAL 34 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Model Timing Figure 19 FLEX 8000 Utd O gy1 ewes 8V11X N u T11X N 0 Ul 211X N Ol nO ap29se9 1no epeoseo osvosvn avi avi XON l ewes Ul 311XeN o 311X9N 01 jno Aue9 InO ueo AHHVOSVT shejaq Indu pejeoipeg
19. bidirectional pins The MAX PLUS II Compiler uses the programmable inversion option to automatically invert signals from the row and column interconnect where appropriate Figure 10 shows the IOE block diagram Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Figure 10 FLEX 8000 IDE Numbers in parentheses are for EPF81500A devices only VO Controls to Row or Column Interconnect q Programmable 22 nversion VCC e a from Row or Column Interconnect CLRN Slew Rate Control Cc O o 0 PVS EBENE aoda9ooo z c x Ww l o 9 Row to IOE Connections Figure 11 illustrates the connection between row interconnect channels and IOEs An input signal from an IOE can drive two separate row channels When an IOE is used as an output the signal is driven by an n to 1 multiplexer that selects the row channels The size of the multiplexer varies with the number of columns in a device EPF81500A devices use a 27 to 1 multiplexer EPF81188A EPF8820A EPF8636A and EPF8452A devices use a 21 to 1 multiplexer and EPF8282A and EPF8282AV devices use a 13 to 1 multiplexer Eight IOEs are connected to each side of the row channels Altera Corporation 19 FLEX 8000 Programmable Logic Device Family Data Sheet Figure 11 FLEX 8000 Row to IOE Connections Numbers in parentheses are for EPF81500A devices See Note 1 Each
20. in a row that can drive the peripheral bus correlates to the number of columns in the FLEX 8000 device EPF8282A and EPF8282AV devices use 13 channels EPF8452A EPF8636A EPF8820A and EPF81188A devices use 21 channels and EPF81500A devices use 27 channels The first LE in each LAB is the source of the row channel signal The six peripheral control signals 12 in EPF81500A devices can be accessed by each IOE Figure 13 FLEX 8000 Peripheral Bus Numbers in parentheses are for EPF81500A devices Peripheral Control Signals Programmable 7 Inversion Dedicated 4 gt Inputs I p 2 gt Row Channels gt n Note 1 go o o We Sooo ogos m x g a S Note 1 n 13 for EPF8282A and EPF8282AV devices n 21 for EPF8452A EPF8636A EPF8820A and EPF81188A devices n 27 for EPF81500A devices 22 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Table 5 lists the source of the peripheral control signal for each FLEX 8000 device by row Table 5 Row Sources of FLEX 8000 Peripheral Control Signals Peripheral EPF8282A Eprg452A EPF8636A EPF8820A EPF81188A EPF81500A Control Signal EPF8282AV CLKO Row A Row A Row E CLK1 0E1 Row B Row B Row B CLRO Row A Row A Row F CLR1 0E0 Row B Row B Row C OE2 Row A Row A Row A OE3 Row B Row B Row A OE4 Row B OE5 Row C OE6 Row D O
21. output Asynchronous Load without Clear or Preset When implementing an asynchronous load without the clear or preset LABCTRL1 implements the asynchronous load of DATA3 by controlling the register preset and clear 15 FLEX 8000 Programmable Logic Device Family Data Sheet FastTrack Interconnect In the FLEX 8000 architecture connections between LEs and device I O pins are provided by the FastTrack Interconnect a series of continuous horizontal row and vertical column routing channels that traverse the entire FLEX 8000 device This device wide routing structure provides predictable performance even in complex designs In contrast the segmented routing structure in FPGAs requires switch matrices to connect a variable number of routing paths which increases the delays between logic resources and reduces performance The LABs within FLEX 8000 devices are arranged into a matrix of columns and rows Each row of LABs has a dedicated row interconnect that routes signals both into and out of the LABs in the row The row interconnect can then drive I O pins or feed other LABs in the device Figure 8 shows how an LE drives the row and column interconnect Figure 8 FLEX 8000 LAB Connections to Row amp Column Interconnect 16 Column Channels PO Row Channels Note 1 Each LE drives one row channel LE1 eee LE2 Y toLocal to Local Each LE dr
22. 25 78 EPF81188A t hy 8 N D TE RYN FLEX 8000 Programmable Logic Device Family September 1998 ver 9 11 Data Sheet Features m Low cost high density register rich CMOS programmable logic device PLD family see Table 1 2 500 to 16 000 usable gates 282to 1 500 registers m System level features n circuit reconfigurability ICR via external Configuration EPROM or intelligent controller Fully compliant with the peripheral component interconnect PCI standard Built in Joint Test Action Group JTAG boundary scan test BST circuitry compliant with IEEE Std 1149 1 1990 on selected devices MultiVolt I O interface enabling device core to run at 5 0 V while I O pins are compatible with 5 0 V and 3 3 V logic levels Low power consumption typical specification less than 0 5 mA in standby mode m Flexible interconnect FastTrack Interconnect continuous routing structure for fast predictable interconnect delays Dedicated carry chain that implements arithmetic functions such as fast adders counters and comparators automatically used by software tools and megafunctions Dedicated cascadechain that implements high speed high fan in logic functions automatically used by software tools and megafunctions Tri state emulation that implements internal tri state nets B Powerful I O pins Programmable output slew rate control reduces switching noise m Peripheral register for fast setup
23. 7 F8 F9 E7 E9 G4 152 53 72 90 150 51 71 85 E4 E5 E6 65 67 90 F12 G6 G7 G5 G13 108 115 129 192 101 118 E15 E16 F5 1 108 116 G8 G9 G10 1614 J5 J13 1139 151 161 1119 140 141 F15 G5 G15 128 150 H1 H4 H5 K4 K14 L5 1173 185 187 1162 163 184 H5 H15 J5 1151 175 177 H6 H7 H8 1113 N4 N7 193 211 229 1185 186 198 J15 K5 K15 206 208 231 H9 H10 H11 N9 N11 N14 208 214 228 L5 L15 M5 1232 237 253 J6 J7 J8 J9 M15 N5 265 273 291 J10 K6 K7 N15 P4 P5 K8 K9 K11 P15 P16 R4 L15 N3 P1 R5 R15 R16 T4 T5 T16 U17 Altera Corporation 59 FLEX 8000 Programmable Logic Device Family Data Sheet Notes to tables Table 17 FLEX 8000 225 232 240 280 amp 304 Pin Package Pin Outs Part 3 of 3 Pin Name 225 Pin 232 Pin 240 Pin 240 Pin 280 Pin 304 Pin BGA PGA P FP P FP PGA R FP EPF8820A EPF81188A EPF81188A EPF81500A EPF81500A EPF81500A No Connect 61 62 119 10 21 23 25 N C 120 181 182 35 37 39 40 239 240 41 42 52 55 66 68 146 147 161 173 174 176 187 188 189 190 192 194 195 205 207 219 221 233 234 235 236 302 303 Total User I O 148 180 180 177 204 204 Pins 1 Perform a complete thermal analysis before committing a design to this device package See Application Note 74 Evaluating Power for Altera Devices in this data book for more information
24. 8000 Devices 1 000 1 500 LEs 800 600 1 000 LEs 400 500 LEs loc Supply Current mA 200 L lt lt 0 30 60 Frequency MHz 3 3 V FLEX 8000 Devices 100 90 200 LEs 80 70 150 LEs 60 50 100 LEs 40 Icc Supply Current mA 30 50 LEs 20 l L 0 30 60 Frequency MHz The FLEX 8000 architecture supports several configuration schemes to load a design into the device s on the circuit board This section summarizes the device operating modes and available device configuration schemes For more information go to Application Note 33 Configuring FLEX 8000 Devices and Application Note 38 Configuring Multiple FLEX 8000 Devices 51 FLEX 8000 Programmable Logic Device Family Data Sheet 52 Operating Modes The FLEX 8000 architecture uses SRAM elements that require configuration data to be loaded whenever the device powers up and begins operation The process of physically loading the SRAM programming data into the device is called configuration During initialization which occurs immediately after configuration the device resets registers enables I O pins and begins to operate as a logic device The I O pins are tri stated during power up and before and during configuration The configuration and initialization processes together are called command mode normal device operation is called user mode SRAM elements allow FLEX 8000 devices to be reconfigured in circuit
25. Altera Corporation 33 FLEX 8000 Programmable Logic Device Family Data Sheet Notes to tables 1 Internal timing parameters cannot be measured explicitly They are worst case delays based on testable and external parameters specified by Altera Internal timing parameters should be used for estimating device performance Post compilation timing simulation or timing analysis is required to determine actual worst case performance These values are specified under FLEX 8000 3 3 V Device Recommended Operating Conditions on page 29 For the fop and tzx3 parameters Vcc o 3 3 V or 5 0 V The trow and tp p delays are worst case values for typical applications Post compilation timing simulation or timing analysis is required to determine actual worst case performance External reference timing characteristics are factory tested worst case values specified by Altera A representative subset of signal paths is tested to approximate typical device applications For more information on test conditions see Application Note 76 Understanding FLEX 8000 Timing in this data book This parameter is a guideline that is sample tested only and is based on extensive device characterization This parameter applies to global and non global clocking and for LE and I O element registers The FLEX 8000 timing model shows the delays for various paths and functions in the circuit See Figure 19 This model contains three distinct parts the LE the IOE
26. E7 Row D OE8 m Rovv E OE9 Row F 0 utp ut This section discusses slew rate control and MultiVolt 1 O interface R operation for FLEX 8000 devices Configuration Slew Rate Control The output buffer in each IOE has an adjustable output slew rate that can be configured for low noise or high speed performance A slow slew rate reduces system noise by slowing signal transitions adding a maximum delay of 3 5 ns The slow slew rate setting affects only the falling edge of a signal The fast slew rate should be used for speed critical outputs in systems that are adequately protected against noise Designers can specify the slew rate on a pin by pin basis during design entry or assign a default slew rate to all pins on a global basis p For more information on high speed system design go to Application Note 75 High Speed Board Designs in this data book Altera Corporation 23 FLEX 8000 Programmable Logic Device Family Data Sheet IEEE 1149 1 JTAG Boundary Scan Support MultiVolt 1 0 Interface The FLEX 8000 device architecture supports the MultiVolt I O interface feature which allows EPF81500A EPF81188A EPF8820A and EPF8636A devices to interface with systems with differing supply voltages These devices in all packages except for EPF8636A devices in 84 pin PLCC packages can be set for 3 3 V or 5 0 V I O pin operation These devices have one set of Vcc pins for internal operation and input buffers VCCINT a
27. FP PGA RQFP EPF8282A 68 78 EPF8282AV 78 EPF8452A 68 68 120 120 EPF8636A 68 118 136 136 EPF8820A 112 120 152 152 152 EPF81188A 148 184 184 EPF81500A 181 208 208 Note 1 FLEX 8000 device package types include plastic J lead chip carrier PLCC thin quad flat pack TOFP plastic quad flat pack PQFP power quad flat pack ROFP ball grid array BGA and pin grid array PGA packages General Description Altera s Flexible Logic Element MatriX FLEX family combines the benefits of both erasable programmable logic devices EPLDs and field programmable gate arrays FPGAs The FLEX 8000 device family is ideal for a variety of applications because it combines the fine grained architecture and high register count characteristics of FPGAs with the high speed and predictable interconnect delays of EPLDs Logic is implemented in LEs that include compact 4 input look up tables LUTs and programmable registers High performance is provided by a fast continuous network of routing resources Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet FLEX 8000 devices provide a large number of storage elements for applications such as digital signal processing DSP wide data path manipulation and data transformation These devices are an excellent choice for bus interfaces TTL integration coprocessor functions and high speed controllers The high pin count packages can integrate multiple 32 bit buses into a
28. and clock to output delay Table 1 FLEX 8000 Device Features Feature EPF8282A EPF8452A EPF8636A EPF8820A EPF81188A EPF81500A EPF8282AV Usable gates 2 500 4 000 6 000 8 000 12 000 16 000 Flipflops 1 500 Logic array blocks LABs 162 Logic elements LEs 1 296 Maximum user I O pins 208 JTAG BST circuitry Yes Altera Corporation 1 A DS F8000 09 11 FLEX 8000 Programmable Logic Device Family Data Sheet and More Features m Fabricated on an advanced SRAM process Available in a variety of packages with 84 to 304 pins see Table 2 W Software design support and automatic place and route provided by the Altera MAX PLUS II development system for 486 and Pentium based PCs and Sun SPARCstation HP 9000 Series 700 800 and IBM RISC System 6000 workstations m Additional design entry and simulation support provided by EDIF 200 and 3 0 0 netlist files library of parameterized modules LPM Verilog HDL VHDL and other interfaces to popular EDA tools from manufacturers such as Cadence Exemplar Logic Mentor Graphics OrCAD Synopsys Synplicity and Veribest Table 2 FLEX 8000 Package Options amp 1 0 Pin Count Note 1 Device 84 Pin 100 144 160 160 192 208 225 232 240 280 304 PLCC Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin T FP T FP PQFP PGA PGA PQFP BGA PGA PO
29. and fall times lt 3 ns JIG capacitance FLEX 8000 5 0 V Device Absolute Maximum Ratings Note 1 The following tables provide information on absolute maximum ratings recommended operating conditions operating conditions and capacitance for 5 0 V and 3 3 V FLEX 8000 devices Symbol Parameter Conditions Min Max Unit Voc Supply voltage With respect to ground Note 2 2 0 7 0 V Vi DC input voltage 2 0 7 0 V lout DC output current per pin 25 25 mA sra Storage temperature No bias 5 150 C TAMB Ambient temperature Under bias 65 135 C Ty Junction temperature Ceramic packages under bias 150 C PQFP and RQFP under bias 135 C FLEX 8000 5 0 V Device Recommended Operating Conditions Symbol Parameter Conditions Min Max Unit Supply voltage for internal logic and Notes 3 4 4 75 4 50 5 25 5 50 V input buffers Supply voltage for output buffers Notes 3 4 4 75 4 50 5 25 5 50 V 5 0 V operation Supply voltage for output buffers Notes 3 4 3 00 3 00 3 60 3 60 V 3 3 V operation Input voltage VccINT V Output voltage Vecio V Operating temperature For commercial use 70 C For industrial use 85 C tn Input rise time ns te Input fall time 40 ns Altera Corporation 27 FLEX 8000 Programmable Logic Device Family Data Sheet FLEX 8000 5 0 V Device DC Operating Conditions Notes 5 6
30. athematical functions carry chain logic supports very fast counters and comparators 8 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Altera Corporation Figure 4 FLEX 8000 Carry Chain Operation Carry In s1 LE Carry Chain sn Carry Chain LUT i Carry Out Carry Chain Cascade Chain With the cascade chain the FLEX 8000 architecture can implement functions that have a very wide fan in Adjacent LUTs can be used to compute portions of the function in parallel the cascade chain serially connects the intermediate values The cascade chain can use a logical AND or logical OR via De Morgan s inversion to connect the outputs of adjacent LEs Each additional LE provides four more inputs to the effective width of a function with a delay as low as 0 6 ns per LE FLEX 8000 Programmable Logic Device Family Data Sheet The MAX PLUS II Compiler can create cascade chains automatically during design processing designers can also insert cascade chain logic manually during design entry Cascade chains longer than eight LEs are automatically implemented by linking LABs together The last LE of an LAB cascades to the first LE in the next LAB in the row Figure 5 shows how the cascade function can connect adjacent LEs to form functions with a wide fan in These examples show functions of 4n variables implemented with n LES For a device with an A 2 speed grade
31. ce to valid output ns tusxz Update register valid output to high impedance ns S e For detailed information on JTAG operation in FLEX 8000 devices refer to Application Note 39 JTAG Boundary Scan Testing in Altera Devices Generic Testi ng Each FLEX 8000 device is functionally tested and specified by Altera Complete testing of each configurable SRAM bit and all logic functionality ensures 100 configuration yield AC test measurements for FLEX 8000 devices are made under conditions equivalent to those shown in Figure 15 Designers can use multiple test patterns to configure devices during all stages of the production flow 26 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Operating Conditions Figure 15 FLEX 8000 AC Test Conditions Power supply transients can affect AC measurements Simultaneous transitions of multiple outputs should be avoided for accurate measurement Threshold tests must not be performed under AC conditions Large amplitude fast ground current transients normally occur as the device outputs discharge the load capacitances When these transients flow through the parasitic inductance between the device ground pin and the test system ground significant reductions in observable noise immunity can result Numbers in VCC 4640 703 Q Device to Test Output System C gt 250 Q 8 06 KQ C1 includes Device input rise
32. e not available as user I O pins If JTAG BST is 60 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Version 9 10 Changes The FLEX 8000 Programmable Logic Device Family Data Sheet version 9 10 contains the following changes m Updated timing information for A 4 speed grade EPF8282AV devices m Added timing information for A 3 speed grade EPF8282AV devices ANU S RYAN 101 Innovation Drive San Jose CA 95134 2020 408 544 7000 Applications Hotline 800 800 EPLD Customer Marketing 408 544 7104 Literature Services 408 544 7144 61 CLA p Printed on Recycled Paper Altera MAX MAX PLUS MAX PLUS II AHDL FLEX FLEX 8000 FastTrack Interconnect and specific device designations are trademarks and or service marks of Altera Corporation in the United States and other countries Altera products are protected under numerous U S and foreign patents and pending applications maskwork rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service NSAI described herein except as expressly agreed to in writing by Altera Corporation Altera customers are advised to obtain the lates
33. imum V c rise time is 100 ms 4 Numbers in parentheses are for industrial temperature range devices 5 Typical values are for TA 25 C and Vcc 5 0 V 6 These values are specified under FLEX 8000 5 0 V Device Recommended Operating Conditions on page 27 7 Theloy parameter refers to high level TTL or CMOS output current the lor parameter refers to low level TTL or CMOS output current 8 Capacitance is sample tested only FLEX 8000 3 3 V Device Absolute Maximum Ratings Note 1 Parameter Conditions Min Max Unit Supply voltage With respect to ground Note 2 2 0 5 3 V DC input voltage 2 0 5 8 V DC output current per pin 25 25 mA TsrG Storage temperature No bias 65 150 C TAMB Ambient temperature Under bias 65 135 C Ty Junction temperature Plastic packages under bias 135 C FLEX 8000 3 3 V Device Recommended Operating Conditions Parameter Conditions Min Max Unit Supply voltage Note 3 3 0 3 6 V Input voltage 0 Voc V Output voltage 0 Voc V TA Operating temperature For commercial use 0 70 C R nput rise time 40 ns F nput fall time 40 ns FLEX 8000 3 3 V Device DC Operating Conditions Note 4 Symbol Parameter Conditions Min Typ Max Unit High level input voltage J Voc 0331 V Low level input voltage 0 8 V High level output voltage lop 0 1 mA DC Note 5 V Low leve
34. is called programmable inversion and is available for all four LAB control signals Logic Element The logic element LE is the smallest unit of logic in the FLEX 8000 architecture with a compact size that provides efficient logic utilization Each LE contains a 4 input LUT a programmable flipflop a carry chain and cascade chain Figure 3 shows a block diagram of an LE Figure 3 FLEX 8000 LE Carry In Cascade In DATA P ooku i DATA2 p ti i Carry Cascade LE Out DATA3 LUT i Chain Chain DATA4 Clear LABCTRL1 Preset LABCTRL2 Logic Clock Select LABCTRL3 LABCTRL4 Y Y Carry Out o Cascade Out Altera Corporation The LUT is a function generator that can quickly compute any function of four variables The programmable flipflop in the LE can be configured for D T JK or SR operation The clock clear and preset control signals on the flipflop can be driven by dedicated input pins general purpose I O pins or any internal logic For purely combinatorial functions the flipflop is bypassed and the output of the LUT goes directly to the output of the LE FLEX 8000 Programmable Logic Device Family Data Sheet The FLEX 8000 architecture provides two dedicated high speed data paths carry chains and cascade chains that connect adjacent LEs without using local interconnect paths The carry chain supports high speed counters and adders the cascade chain im
35. ives up to Feedback Feedback two column channels Note 1 See Table 4 for the number of row channels 16 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Altera Corporation Each LE inan LAB can drive up to two separate column interconnect channels Therefore all 16 available column channels can be driven by the LAB The column channels run vertically across the entire device and share access to LABs in the same column but in different rows The MAX PLUS II Compiler chooses which LEs must be connected to a column channel A row interconnect channel can be fed by the output of the LE or by two column channels These three signals feed a multiplexer that connects to a specific row channel Each LE is connected to one 3 to 1 multiplexer In an LAB the multiplexers provide all 16 column channels with access to 8 row channels Each column of LABs has a dedicated column interconnect that routes signals out of the LABs into the column The column interconnect can then drive I O pins or feed into the row interconnect to route the signals to other LABs in the device A signal from the column interconnect which can be either the output of an LE or an input from an I O pin must transfer to the row interconnect before it can enter an LAB Table 4 summarizes the FastTrack Interconnect resources available in each FLEX 8000 device Table 4 FLEX 8000 FastTrack Interconnect Resources Device Rows
36. l output voltage lo 4 mA DC Note 5 0 45 V Input leakage current V I Vcc or ground 10 HA loz Tri state output off state current Vo Vcc or ground 40 40 HA loco Voc supply current standby Vi ground no load Note 6 0 3 10 mA Altera Corporation 29 FLEX 8000 Programmable Logic Device Family Data Sheet FLEX 8000 3 3 V Device Capacitance Note 7 Symbol Parameter Conditions Min Max Unit Cin Input capacitance Vin 0 V f 1 0 MHz 10 pF Cour Output capacitance Vout 0 V f 1 0 MHz 10 pF Notes to tables 1 See the Operating Requirements for Altera Devices Data Sheet in this data book 2 Minimum DC input is 0 3 V During transitions the inputs may undershoot to 2 0 V or overshoot to 5 3 V for periods shorter than 20 ns under no load conditions 3 The maximum V e rise time is 100 ms Vcc must rise monotonically 4 These values are specified under FLEX 8000 3 3 V Device Recommended Operating Conditions on page 29 5 Thelon parameter refers to high level TTL output current the lor parameter refers to low level TTL output current 6 Typical values are for TA 25 Cand Vcc 3 3 V 7 Capacitance is sample tested only Figures 16 and 17 show the typical output drive characteristics of 5 0 V FLEX 8000 devices The output driver is compliant with the PCI Local Bus Specification Revision 2 1 Figure 16 Output Drive Characteristics of 5 0 V FLEX 8000
37. lation to evaluate logic design accuracy and post synthesis timing simulation with 0 1 ns resolution The Timing Analyzer provides point to point timing delay information setup and hold time prediction and device wide performance analysis Tables 8 through 11 describe the FLEX 8000 timing parameters and their symbols Table 8 FLEX 8000 Internal Timing Parameters Note 1 Symbol Parameter tiop IOE register data delay lioc IOE register control signal delay CE Output enable delay tioco IOE register clock to output delay locomB OE combinatorial delay tiosu IOE register setup time before clock IOE register recovery time after asynchronous clear tion IOE register hold time after clock tioctR IOE register clear delay tin Input pad and buffer delay topi Output buffer and pad delay slow slew rate off V ccio 5 0 V C1 35 pF Note 2 tope Output buffer and pad delay slow slew rate off V ccio 3 3 V C1 35 pF Note 2 tops Output buffer and pad delay slow slew rate on C1 35 pF Note 3 tyz Output buffer disable delay C1 5 pF zxt Output buffer enable delay slow slew rate off Vccio 5 0 V C1 35 pF Note 2 zxe Output buffer enable delay slow slew rate off Vccio 3 3 V C1 35 pF Note 2 zx3 Output buffer enable delay slow slew rate on C1 35 pF Note 3 32 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet
38. ly Data Sheet Internal Tri State Emulation Internal tri state emulation provides internal tri stating without the limitations of a physical tri state bus In a physical tri state bus the tri state buffers output enable signals select the signal that drives the bus However if multiple output enable signals are active contending signals can be driven onto the bus Conversely if no output enable signals are active the bus will float Internal tri state emulation resolves contending tri state buffers to a low value and floating buses to a high value thereby eliminating these problems The MAX PLUS II software automatically implements tri state bus functionality with a multiplexer Clear amp Preset Logic Control Logic for the programmable register s clear and preset functions is controlled by the DATA3 LABCTRL1 and LABCTRL2 inputs to the LE The clear and preset control structure of the LE is used to asynchronously load signals into a register The register can be set up so that LABCTRL1 implements an asynchronous load The data to be loaded is driven to DATA3 when LABCTRLI is asserted DATA3 is loaded into the register During compilation the MAX PLUS II Compiler automatically selects the best control signal implementation Because the clear and preset functions are active low the Compiler automatically assigns a logic high to an unused clear or preset The clear and preset logic is implemented in one of the following six
39. nchronous clear If DATA3 is tied to VCC asserting LABCTRL1 asynchronously loads a 1 into the register Alternatively the MAX PLUS II software can provide preset control by using the clear and inverting the input and output of the register Inversion control is available for the inputs to both LEs and IOEs Therefore if a register is preset by only one of the two LABCTRL signals the DATA3 input is not needed and can be used for one of the LE operating modes Asynchronous Clear amp Preset When implementing asynchronous clear and preset LABCTRL1 controls the preset and LABCTRL2 controls the clear The DATA3 input is tied to VCC therefore asserting LABCTRL1 asynchronously loads a 1 into the register effectively presetting the register Asserting LABCTRL2 clears the register Asynchronous Load with Clear When implementing an asynchronous load with the clear LABCTRL1 implements the asynchronous load of DATA3 by controlling the register preset and clear LABCTRL2 implements the clear by controlling the register clear Asynchronous Load with Preset When implementing an asynchronous load in conjunction with a preset the MAX PLUS II software provides preset control by using the clear and inverting the input and output of the register Asserting LABCTRL2 clears the register while asserting LABCTRL1 loads the register The MAX PLUS II software inverts the signal that drives the DATA3 signal to account for the inversion of the register s
40. nd another set for I O output drivers VCCIO The VCCINT pins must always be connected to a 5 0 V power supply With a 5 0 V Vcc r level input voltages are at TTL levels and are therefore compatible with 3 3 V and 5 0 V inputs The VCCIO pins can be connected to either a 3 3 V or 5 0 V power supply depending on the output requirements When the VCCIO pins are connected to a 5 0 V power supply the output levels are compatible with 5 0 V systems When the VCCIO pins are connected to a 3 3 V power supply the output high is at 3 3 V and is therefore compatible with 3 3 V or 5 0 V systems Devices operating with Vccjo levels lower than 4 75 V incur a nominally greater timing delay of fop instead of topj See Table 7 on page 26 The EPF8282A EPF8282AV EPF8636A EPF8820A and EPF81500A devices provide JTAG BST circuitry FLEX 8000 devices with JTAG circuitry support the JTAG instructions shown in Table 6 Figure 14 shows the timing requirements for the JTAG signals Table 6 EPF8282A EPF8282AV EPF8636A EPF8820A amp EPF81500A JTAG Instructions JTAG Instruction Description SAMPLE PRELOAD Allows a snapshot of the signals at the device pins to be captured and examined during normal device operation and permits an initial data pattern to be output at the device pins EXTEST Allows the external circuitry and board level interconnections to be tested by forcing a test pattern at the output pins and capturing test result
41. ndard PC and UNIX workstation based EDA tools The MAX PLUS II software runs on 486 and Pentium based PCs and Sun SPARCstation HP 9000 Series 700 800 and IBM RISC System 6000 workstations The MAX PLUS II software interfaces easily with common gate array EDA tools for synthesis and simulation For example the MAX PLUS II software can generate Verilog HDL files for simulation with tools such as Cadence Verilog XL Additionally the MAX PLUS II software contains EDA libraries that use device specific features such as carry chains which are used for fast counter and arithmetic functions For instance the Synopsys Design Compiler library supplied with the MAX PLUS II development system includes DesignWare functions that are optimized for the FLEX 8000 architecture For more information on the MAX PLUS II software go to the MAX PLUS II Programmable Logic Development System amp Software Data Sheet in this data book The FLEX 8000 architecture incorporates a large matrix of compact building blocks called logic elements LEs Each LE contains a 4 input LUT that provides combinatorial logic capability and a programmable register that offers sequential logic capability The fine grained structure of the LE provides highly efficient logic implementation Eight LEs are grouped together to form a logic array block LAB Each FLEX 8000 LAB is an independent structure with common inputs interconnections and control signals The LAB architectu
42. ns tyz 1 4 1 8 ns zxt 1 4 1 8 ns zxe 1 9 2 3 ns zx3 4 9 5 1 5 3 ns EPF81500A Interconnect Timing Parameters Symbol A 2 Speed Grade A 3 Speed Grade A 4 Speed Grade Unit Min Max Min Max Min Max li ABCASC 0 3 0 3 0 4 ns li ABCARRY 0 3 0 3 0 4 ns LOCAL 0 5 0 6 0 8 ns trow 6 2 6 2 6 2 ns coL 3 0 3 0 3 0 ns DIN C 5 0 5 0 5 5 ns DIN D 8 2 8 2 8 7 ns DIN IO 5 0 5 0 5 5 ns Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet EPF81500A LE Timing Parameters Symbol A 2 Speed Grade A 3 Speed Grade A 4 Speed Grade Unit Min Max Min Max Min Max ti ut 2 0 2 5 3 2 ns CLUT 0 0 0 0 0 0 ns RLUT 0 9 1 1 1 5 ns GATE 0 0 0 0 0 0 ns CASC PRE 0 6 CLR 0 6 0 7 0 8 ns EPF81500A External Timing Parameters Symbol A 2 Speed Grade A 3 Speed Grade A 4 Speed Grade Unit Min Max Min Max Min Max torr 16 1 20 1 25 1 ns ODH 1 0 1 0 1 0 ns Altera Corporation 49 FLEX 8000 Programmable Logic Device Family Data Sheet Power Consumption 50 The supply power for FLEX 8000 devices P can be calculated with the following eguation P Pint Pio IcCsrANDBY Iccactive X Vecl Pijo Typical Iccsranppy Values are shown as Icco in the FLEX 8000 5 0 V Device DC Operating Conditions table on page 28 and the FLEX 8000 3 3 V Device DC Operating Condi
43. ocal interconnect The LAB provides the coarse grained structure of the FLEX 8000 architecture This structure enables FLEX 8000 devices to provide efficient routing high device utilization and high performance Figure 2 shows a block diagram of the FLEX 8000 LAB Figure 2 FLEX 8000 Logic Array Block Dedicated Inputs Row Interconnect 24 4 ne y 8 LAB Local Interconnect 4 M Gagana See Figure 8 32 channels Cascade In for details from LAB 8 716 g on Left X LAB Control Signals Column to Row Interconnect Column Interconnect Carry Out and Cascade Out to LAB on Right 6 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Each LAB provides four control signals that can be used in all eight LEs Two of these signals can be used as clocks and the other two for clear preset control The LAB control signals can be driven directly from a dedicated input pin an I O pin or any internal signal via the LAB local interconnect The dedicated inputs are typically used for global clock clear or preset signals because they provide synchronous control with very low skew across the device FLEX 8000 devices support up to four individual global clock clear or preset control signals If logic is required on a control signal it can be generated in one or more LEs in any LAB and driven into the local interconnect of the target LAB This process
44. ogrammable Logic Device Family Data Sheet EPF8452A LE Timing Parameters Symbol A 2 Speed Grade A 3 Speed Grade A 4 Speed Grade PRE 0 6 0 7 0 8 ns CLR 0 6 0 7 0 8 ns EPF84524 External Timing Parameters Symbol A 2 Speed Grade A 3 Speed Grade A 4 Speed Grade Unit Min Max Min Max Min Max DRR 16 0 20 0 25 0 ns ODH 1 0 1 0 1 0 ns Altera Corporation 41 FLEX 8000 Programmable Logic Device Family Data Sheet EPF8636A Internal Timing Parameters EPF8636A I O Element Timing Parameters Symbol A 2 Speed Grade A 3 Speed Grade A 4 Speed Grade Unit Min Max Min Max Min Max tiop 0 7 0 8 0 9 ns tioc 1 7 1 8 1 9 ns loE 1 7 1 8 1 9 ns tioco 1 0 1 0 1 0 ns tIOCOMB 0 3 0 2 0 1 ns tiosu 1 4 1 6 1 8 ns tion 0 0 0 0 0 0 ns tlocLrR 1 2 1 2 1 2 ns tin 1 5 1 6 1 7 ns topi 1 1 1 4 1 7 ns tope 1 6 1 9 2 2 ns tops 4 6 4 9 5 2 ns xz 14 1 6 1 8 ns zxt 1 4 1 6 1 8 ns tzx2 1 9 2 1 2 3 ns zx3 4 9 5 1 5 3 ns EPF8636A Interconnect Timing Parameters Symbol A 2 Speed Grade A 3 Speed Grade A 4 Speed Grade Unit Max Min Max Min Max LABCASC 0 3 0 4 0 4 ns LABCARRY 0 3 0 4 0 4 ns LOCAL 0 5 0 5 0 7 ns trow 5 0 5 0 5 0 ns coL 3 0 3 0 3 0 ns DIN C 5 0 5 0 5 5 ns DIN D 7 0 7 0 7 5 ns DIN IO 5 0 5 0 5 5 ns 42 Alte
45. plements wide input functions with minimum delay Carry and cascade chains connect all LEs in an LAB and all LABs in the same row Heavy use of carry and cascade chains can reduce routing flexibility Therefore the use of carry and cascade chains should be limited to speed critical portions of a design Carry Chain The carry chain provides a very fast less than 1 ns carry forward function between LEs The carry in signal from a lower order bit moves forward into the higher order bit via the carry chain and feeds into both the LUT and the next portion of the carry chain This feature allows the FLEX 8000 architecture to implement high speed counters and adders of arbitrary width The MAX PLUS II Compiler can create carry chains automatically during design processing designers can also insert carry chain logic manually during design entry Figure 4 shows how an n bit full adder can be implemented in n 1 LES with the carry chain One portion of the LUT generates the sum of two bits using the input signals and the carry in signal the sum is routed to the output of the LE The register is typically bypassed for simple adders but can be used for an accumulator function Another portion of the LUT and the carry chain logic generate the carry out signal which is routed directly to the carry in signal of the next higher order bit The final carry out signal is routed to another LE where it can be used as a general purpose signal In addition to m
46. ra Corporation FLEX 8000 Programmable Logic Device Family Data Sheet EPF8636A LE Timing Parameters Symbol A 2 Speed Grade A 3 Speed Grade A 4 Speed Grade Unit Min Max Max LUT 2 0 3 0 ns CLUT 0 0 0 1 ns RLUT 0 9 1 6 ns GATE 0 0 0 0 ns cASC 0 6 0 9 ns c co 0 4 0 6 ns CGEN 0 4 0 8 ns CGENR 0 9 1 5 ns 1 6 2 4 ns toy 4 0 ns top 4 0 ns tco 0 4 0 6 ns COMB 0 4 0 6 ns tsu 0 8 ns tH 0 9 ns PRE 0 6 0 8 ns CLR 0 6 0 8 ns EPF8636A External Timing Parameters Symbol A 2 Speed Grade A 3 Speed Grade A 4 Speed Grade Unit Min Max Min Max Min Max DRR 16 0 20 0 25 0 ns ODH 1 0 1 0 1 0 ns Altera Corporation 43 FLEX 8000 Programmable Logic Device Family Data Sheet EPF8820A Internal Timing Parameters 44 EPF8820A I O Element Timing Parameters Symbol A 2 Speed Grade A 3 Speed Grade A 4 Speed Grade Unit Min Max Min Max Min Max tioD 0 7 0 8 0 9 ns tioc 1 7 1 8 1 9 ns loE 1 7 1 8 1 9 ns tioco 1 0 1 0 1 0 ns tiocomB 0 3 0 2 0 1 ns tiosu 1 4 1 6 1 8 ns OH 0 0 0 0 0 0 ns JOCLR 1 2 1 2 1 2 ns N 1 5 1 6 1 7 ns top1 1 1 1 4 1 7 ns tope 1 6 1 9 22 ns tops 4 6 4 9 5 2 ns tyz 1 4 1 6 1 8 ns zx 1 4 1 6 1 8 ns zxe 1 9 2 1 2 3 ns zx3 4 9 5 1 5 3 ns EPF8820A Interconnec
47. re provides a coarse grained structure for high device performance and easy routing Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Figure 1 shows a block diagram of the FLEX 8000 architecture Each group of eight LEs is combined into an LAB LABs are arranged into rows and columns The I O pins are supported by I O elements IOEs located at the ends of rows and columns Each IOE contains a bidirectional I O buffer and a flipflop that can be used as either an input or output register Figure 1 FLEX 8000 Device Block Diagram VO Element IE 4 i FastTrack Interconnect Logic Array Block LAB IOE 2 4 IOE e IOE Tm IOE Logic gt Element LE Signal interconnections within FLEX 8000 devices and between device pins are provided by the FastTrack Interconnect a series of fast continuous channels that run the entire length and width of the device IOEs are located at the end of each row horizontal and column vertical FastTrack Interconnect path Altera Corporation 5 FLEX 8000 Programmable Logic Device Family Data Sheet Logic Array Block A logic array block LAB consists of eight LES their associated carry and cascade chains LAB control signals and the LAB l
48. requires less than 100 ms real time changes can be made during system operation For information on how to configure FLEX 8000 devices go to the following documents Configuration EPROMs for FLEX Devices Data Sheet BitBlaster Serial Download Cable Data Sheet ByteBlaster Parallel Port Download Cable Data Sheet Application Note 33 Configuring FLEX 8000 Devices Application Note 38 Configuring Multiple FLEX 8000 Devices FLEX 8000 Programmable Logic Device Family Data Sheet Functional Description FLEX 8000 devices contain an optimized microprocessor interface that permits the microprocessor to configure FLEX 8000 devices serially in parallel synchronously or asynchronously The interface also enables the microprocessor to treat a FLEX 8000 device as memory and configure the device by writing to a virtual memory location making it very easy for the designer to create configuration software The FLEX 8000 family is supported by Altera s MAX PLUS II development system a single integrated package that offers schematic text including the Altera Hardware Description Language AHDL VHDL and Verilog HDL and waveform design entry compilation and logic synthesis simulation and timing analysis and device programming The MAX PLUS II software provides EDIF 2 0 0 and 3 0 0 library of parameterized modules LPM VHDL Verilog HDL and other interfaces for additional design entry and simulation support from other industry sta
49. s top3 4 6 4 9 5 2 ns tyz 1 4 1 6 1 8 ns zxt 1 4 1 6 1 8 ns zxe 19 21 23 ns zx3 4 9 5 1 5 3 ns EPF81188A Interconnect Timing Parameters Symbol A 2 Speed Grade A 3 Speed Grade A 4 Speed Grade Unit Min Max Min Max Min Max li ABCASC 0 3 0 3 0 4 ns LABCARRY 0 3 0 3 0 4 ns LOCAL 0 5 0 6 0 8 ns trow 5 0 5 0 5 0 ns coL 3 0 3 0 3 0 ns DIN C 5 0 5 0 5 5 ns DIN D 7 0 7 0 7 5 ns DIN IO 5 0 5 0 5 5 ns 46 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet EPF81188A LE Timing Parameters Symbol A 2 Speed Grade A 3 Speed Grade A 4 Speed Grade EPF81188A External Timing Parameters Symbol A 2 Speed Grade A 3 Speed Grade A 4 Speed Grade Unit Min Max Min Max Min Max torr 16 0 20 0 25 0 ns ODH 1 0 1 0 1 0 ns Altera Corporation 47 FLEX 8000 Programmable Logic Device Family Data Sheet EPF81500A Internal Timing Parameters 48 EPF81500A 1 0 Element Timing Parameters Symbol A 2 Speed Grade A 3 Speed Grade A 4 Speed Grade Unit Min Max Min Max Min Max lop 0 7 0 8 0 9 ns tioc 1 7 1 9 ns loE 1 7 1 9 ns tioco 1 0 1 0 ns tioCOMB 0 3 0 1 ns tiosu 1 4 1 6 1 8 ns tion 0 0 0 0 0 0 ns tiocLrR 1 2 1 2 ns tin 1 5 1 7 ns top1 1 1 1 7 ns tope 1 6 2 2 ns tops 4 6 5 2
50. s at the input pins BYPASS Places the 1 bit bypass register between the TDI and TDO pins which allows the BST data to pass synchronously through the selected device to adjacent devices during normal device operation 24 Altera Corporation Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Figure 14 EPF8282A EPF8282AV EPF8636A EPF8820A amp EPF81500A JTAG Waveforms TDI X X c tice x lt lcu z Uc tupsu ti gt Up Captured T H ma 7 P tuszx tusco tsxz lt Signal i to Be I Y Driven i Table 7 shows the timing parameters and values for EPF8282A EPF8282AV EPF8636A EPF8820A and EPF81500A devices 25 FLEX 8000 Programmable Logic Device Family Data Sheet Table 7 JTAG Timing Parameters amp Values Symbol Parameter EPF8282A Unit EPF8282AV EPF8636A EPF8820A EPF81500A Min Max tucp TCK clock period 100 ns tucH TCK Clock high time ns tucL TCK clock low time ns tjpsu JTAQ port setup time ns tupH JTAG port hold time ns typco JTAG port clock to output ns typzx JTAG port high impedance to valid output ns typxz JTAG port valid output to high impedance ns yssu 1 Capture register setup time ns tusH Capture register hold time ns tusco Update register clock to output ns yszx Update register high impedan
51. s that provide general purpose input capability or from the four dedicated inputs The IOEs are located at the ends of the row and column interconnect channels I O pins can be used as input output or bidirectional pins Each I O pin has a register that can be used either as an input register for external data that requires fast setup times or as an output register for data that requires fast clock to output performance The MAX PLUS II Compiler uses the programmable inversion option to automatically invert signals from the row and column interconnect when appropriate The clock clear and output enable controls for the IOEs are provided by a network of I O control signals These signals can be supplied by either the dedicated input pins or by internal logic The IOE control signal paths are designed to minimize the skew across the device All control signal sources are buffered onto high speed drivers that drive the signals around the periphery of the device This peripheral bus can be configured to provide up to four output enable signals 10 in EPF81500A devices and up to two clock or clear signals Figure 13 shows how two output enable signals are shared with one clock and one clear signal 21 FLEX 8000 Programmable Logic Device Family Data Sheet The signals for the peripheral bus can be generated by any of the four dedicated inputs or signals on the row interconnect channels as shown in Figure 13 The number of row channels
52. single device Table 3 shows FLEX 8000 performance and LE requirements for typical applications Table 3 FLEX 8000 Performance Application LEs Used A 2 Speed Grade A 3 Speed Grade A 4 Speed Units Grade 16 bit loadable counter 16 125 95 83 MHz 16 bit up down counter 16 125 95 83 MHz 24 bit accumulator 24 87 67 58 MHz 16 bit address decode 4 4 2 4 9 6 3 ns 16 to 1 multiplexer 10 6 6 7 9 9 5 ns Altera Corporation All FLEX 8000 device packages provide four dedicated inputs for synchronous control signals with large fan outs Each I O pin has an associated register on the periphery of the device As outputs these registers provide fast clock to output times as inputs they offer quick setup times The logic and interconnections in the FLEX 8000 architecture are configured with CMOS SRAM elements FLEX 8000 devices are configured at system power up with data stored in an industry standard parallel EPROM or an Altera serial Configuration EPROM device or with data provided by a system controller Altera offers the EPC1 EPC1213 EPC1064 and EPC1441 Configuration EPROMs which configure FLEX 8000 devices via a serial data stream Configuration data can also be stored in an industry standard 32 K x 8 bit or larger EPROM or downloaded from system RAM After a FLEX 8000 device has been configured it can be reconfigured in circuit by resetting the device and loading new data Because reconfiguration
53. sive parallel asynchronous PPA Intelligent host Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Device Pin Outs Table 15 FLEX 8000 84 100 144 amp 160 Pin Package Pin Outs Part 1 of 3 Tables 15 through 17 show the pin names and numbers for the dedicated pins in each FLEX 8000 device package Pin Name 84 Pin PLCC EPF8282A 84 Pin PLCC EPF8452A EPF8636A 100 Pin T FP EPF8282A EPF8282AV 100 Pin T FP EPF8452A 144 Pin T FP EPF3820A 160 Pin PGA EPF8452A 160 Pin P FP EPF8820A Note 1 EL 2 75 75 76 110 R1 1 TATUS 2 nCONFIG 2 DCLK 2 CONF DONE 2 nWS RDYnBUSY KUSR 104 K3 105 M1 Altera Corporation 53 FLEX 8000 Programmable Logic Device Family Data Sheet Table 15 FLEX 8000 84 100 144 amp 160 Pin Package Pin Outs Part 2 of 3 Pin Name 84 Pin 84 Pin 100 Pin 100 Pin 144 Pin 160 Pin 160 Pin PLCC PLCC T FP T FP T FP PGA PQFP EPF8282A EPF8452A EPF8282A EPF8452A EPF8820A EPF8452A EPF8820A EPF8636A EPF8282AV Note 1 ADDO 78 76 78 77 106 N3 6 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATAO SDOUT 3 TDI 4 TDO 4 TCK 4 TMS 4 TRST 6 Dedicated 12 31 54 112 31 54
54. t Timing Parameters Symbol A 2 Speed Grade A 3 Speed Grade A 4 Speed Grade Unit Min Max Min Max Min Max li ABCASC 0 3 0 3 0 4 ns li ABCARRY 0 3 0 3 0 4 ns LOCAL 0 5 0 6 0 8 ns trow 5 0 5 0 5 0 ns coL 3 0 3 0 3 0 ns DIN C 5 0 5 0 5 5 ns DIN D 7 0 7 0 7 5 ns DIN IO 5 0 5 0 5 5 ns Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet EPF8820A LE Timing Parameters Symbol A 2 Speed Grade A 3 Speed Grade A 4 Speed Grade Unit Min Max Min Max Min Max ti ut 2 0 2 5 3 2 ns CLUT 0 0 0 0 0 0 ns RLUT 0 9 1 1 1 5 ns GATE 0 0 0 0 0 0 ns CASC 0 8 ns EPF8820A External Timing Parameters Symbol A 2 Speed Grade A 3 Speed Grade A 4 Speed Grade Unit Min Max Min Max Min Max torr 16 0 20 0 25 0 ns ODH 1 0 1 0 1 0 ns Altera Corporation 45 FLEX 8000 Programmable Logic Device Family Data Sheet EPF81188A Internal Timing Parameters EPF81188A 1 0 Element Timing Parameters Symbol A 2 Speed Grade A 3 Speed Grade A 4 Speed Grade Unit Min Max Min Max Min Max lop 0 7 0 8 0 9 ns tioc 1 7 18 19 ns loE 1 7 1 8 1 9 ns tioco 1 0 1 0 1 0 ns IOCOMB 0 3 0 2 0 1 ns tiosu 1 4 1 6 1 8 ns tion 0 0 0 0 0 0 ns OCLR 1 2 12 12 ns tin 1 5 1 6 1 7 ns top1 1 1 1 4 1 7 ns tope 1 6 1 9 2 2 n
55. t version of device specifications before relying on any published information and before placing orders for products or services Copyright 1998 Altera Corporation All rights reserved LS EN ISO 9001 Altera Corporation
56. the LUT delay is approximately 1 6 ns the cascade chain delay is 0 6 ns With the cascade chain 4 2 ns is needed to decode a 16 bit address Figure 5 FLEX 8000 Cascade Chain Operation AND Cascade Chain d 3 0 di7 4 di 4n 1 4 n 1 OR Cascade Chain 10 LE Operating Modes The FLEX 8000 LE can operate in one of four modes each of which uses LE resources differently See Figure 6 In each mode seven of the ten available inputs to the LE the four data inputs from the LAB local interconnect the feedback from the programmable register and the carry in and cascade in from the previous LE are directed to different destinations to implement the desired logic function The three remaining inputs to the LE provide clock clear and preset control for the register The MAX PLUS II software automatically chooses the appropriate mode for each application Design performance can also be enhanced by designing for the operating mode that supports the desired application Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Figure 6 FLEX 8000 LE Operating Modes Normal Mode DATA1 DATA2 DATA3 DATA4 Arithmetic Mode DATA1 DATA2 Up Down DATA1 ena DATA2 nclr DATA3 data DATA4 nload Clearable Counter Mode DATA1 ena DATA2 nclr DATA3 data DATA4 nload Altera Corporation Carry In Cascade In
57. the carry in signal and two data inputs from the LAB local interconnect to generate a combinatorial or registered output For example in an adder this output is the sum of three bits a b and the carry in The second LUT uses the same three signals to generate a carry out signal thereby creating a carry chain The arithmetic mode also supports a cascade chain Up Down Counter Mode The up down counter mode offers counter enable synchronous up down control and data loading options These control signals are generated by the data inputs from the LAB local interconnect the carry in signal and output feedback from the programmable register Two 3 input LUTs are used one generates the counter data and the other generates the fast carry bit A 2 to 1 multiplexer provides synchronous loading Data can also be loaded asynchronously with the clear and preset register control signals without using the LUT resources Clearable Counter Mode The clearable counter mode is similar to the up down counter mode but supports a synchronous clear instead of the up down control the clear function is substituted for the cascade in signal in the up down counter mode Two 3 input LUTs are used one generates the counter data and the other generates the fast carry bit Synchronous loading is provided by a 2 to 1 multiplexer and the output of this multiplexer is ANDed with a synchronous clear Altera Corporation FLEX 8000 Programmable Logic Device Fami
58. tions table on page 29 The P value which depends on the device output load characteristics and switching frequency can be calculated using the guidelines given in Application Note 74 Evaluating Power for Altera Devices The IccacrivE value depends on the switching frequency and the application logic This value can be calculated based on the amount of current that each LE typically consumes The following equation shows the general formula for calculating cCACTIVE m HA ICC ACTIVE Kx MAX x N x togrc x MHz x LE The parameters in this equation are shown below fmax Maximum operating frequency in MHz N Total number of logic cells used in the device tog c Average percentage of logic cells toggling at each clock Constant shown in Table 13 Table 13 Values for Constant K Device K 5 0 V FLEX 8000 devices 75 3 3 V FLEX 8000 devices 60 This calculation provides an Icc estimate based on typical conditions with no output load The actual Icc value should be verified during operation because this measurement is sensitive to the actual pattern in the device and the environmental operating conditions Figure 20 shows the relationship between Icc and operating frequency for several LE utilization values Altera Corporation Configuration amp Operation Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Figure 20 FLEX 8000 l ceacrye VS Operating Frequency 5 0 V FLEX

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