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National Semiconductor DM54161/DM74161/DM74163 Synchronous 4-Bit Counters handbook

1. 5 4 75 5 5 25 High Level Input Voltage 2 2 Vit Low Level Input Voltage 0 8 0 8 V High Level Output Current 0 8 0 8 mA loL Low Level Output Current 16 16 mA Clock Frequency Note 6 0 25 0 25 MHz tw Pulse Width Clock 25 25 Ws ots 6 Clear 20 20 150 Setup Time Data 20 20 ore 6 Enable P 34 34 Re Load 25 25 Clear Note 5 20 20 tH Hold Time Note 6 0 0 ns Free Air Operating Temperature 55 125 0 70 Electrical Characteristics Over recommended operating free air temperature range unless otherwise noted Symbol Parameter Conditions Min AUT Max Units Vi nput Clamp Voltage Voc Min lj 12 1 5 V High Level Output Voc Min Max 24 34 V Voltage Vit Min VoL Low Level Output Voc Min Max 02 04 Voltage Min nput Current Max Voc Max 5 5V 1 PA nput Voltage High Level Input Vcc Max Enable T 80 Current Vi 2 4V Clock 80 pA Others 40 Low Level Input Voc Max Enable T 3 2 Current Vi 04V Clock 3 2 Others 1 6 Electrical Characteristics Over recommended operating free air temperature range unless otherwise noted Continued Symbol Parameter Conditions Min Typ Max Units Note 1 los Short Circuit Vcc Max DM54 20 57 Output Current Note 2 m DM74 20 57 Supply Current Vcc Max DM54 85 A with Outputs High Note
2. 2 78 D 541611E QN vationat Semiconductor DM54161 DM74161 DM74163 Synchronous 4 Bit Counters October 1992 General Description These synchronous presettable counters feature an inter nal carry look ahead for application in high speed counting designs The 161 and 163 are 4 bit binary counters The carry output is decoded by means of a NOR gate thus pre venting spikes during the normal counting mode of opera tion Synchronous operation is provided by having all flip flops clocked simultaneously so that the outputs change co incident with each other when so instructed by the count enable inputs and internal gating This mode of operation eliminates the output counting spikes which are normally associated with asynchronous ripple clock counters A buffered clock input triggers the four flip flops on the rising positive going edge of the clock input waveform These counters are fully programmable that is the outputs may be preset to either level As presetting is synchronous setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable input The clear function for the 161 is asynchronous and a low level at the clear input sets all four of the flip flop out puts low regardless of the levels of clock load or enable inputs The clear function for the 163 is synchronous and a low level at the cl
3. 3 DM74 59 94 IocL Supply Current Vcc Max DM54 91 ith Outputs Low Note 4 bs wi DM74 63 101 Note 1 All typicals are at Voc 5V Ta 25 C Note 2 Not more than one output should be shorted at a time Note 3 is measured with the LOAD high then again with the LOAD low with all inputs high and all outputs open Note 4 lcc is measured with the CLOCK high then again with the CLOCK input low with all inputs low and all outputs open Note 5 Applies to 163 which has synchronous clear inputs Note 6 TA 25 C and 5V Switching Characteristics at voc 5V and TA 25 C See Section 1 for Test Waveforms and Output Load Symbol Parameter Prom Input Tu B Units To Output Min Max Maximum Clock 25 MHz Frequency Propagation Delay Time Clock to 35 ns Low to High Level Output Ripple Carry Propagation Delay Time Clock to 35 As High to Low Level Output Ripple Carry Propagation Delay Time Clock 20 h amp Low to High Level Output Load High to Q Propagation Delay Time Clock 23 ns High to Low Level Output Load High to Q tpiH Propagation Delay Time Clock 25 is Low to High Level Output Load Low to Q Propagation Delay Time Clock 29 ng High to Low Level Output Load Low to Q Propagation Delay Time Enable T to 16 bs Low to High Level Output Ripple Carry Propagation Delay Ti
4. 50 aa 0 280 0 203 0 406 0 125 0 150 0 030 0 015 7 112 3 175 3 810 0 1 0762 10 381 MIN 0 014 0 023 0 100 0 010 0 040 0 356 0 584 0 0504 s 2 540 0 254 9332570015 N16E REV F 1016 Rev F 1 270 0 254 255 1 016 16 Lead Molded Dual In Line Package Order Number DM74161N or DM74163N NS Package Number N16E DM54161 DM74161 DM74163 Synchronous 4 Bit Counters Physical Dimensions inches millimeters Continued 0 050 0 080 11 270 2 032 0 004 0 006 0 102 0 152 0 026 0 040 0 660 1 0 660 1 016 1 LIFE SUPPORT POLICY La 0371 0 390 8 423 9 806j 0 007 0 018 0 050 0 005 TYP 0 178 0 457 r 1 270 0 127 De gt lt 0 000 miN TYP 0 250 0 370 6 350 9 398 1 m 0 245 0 275 Nut 6 223 6 985 DETAIL gt PIN NO 1 0 250 0 370 IDENT 6 350 9 398 0 015 0 019 0 381 0 482 TYP W164 REV 16 Lead Ceramic Flat Package W Order Number DM54161W or DM54163AW NS Package Number W16A DETAIL A 0 008 0 012 0 203 0 305 NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are
5. REF i tsetup W CLEAR VREF VREF istrup VREF VREF teu bE teu MEASURE AT tye OR TL F 6551 7 Note The input pulses are supplied by generators having the following characteristics PRR lt 1 MHz duty cycle lt 50 Zour 500 For 161 and 163 tr 10 ns t lt 10 ns Vary PRR to measure fmax Note B Enable P and enable T setup times are measured at o Note C For 161 and 163 1 5 Physical Dimensions inches millimeters i x 9 005 0 020 R 51 TYP 0 13 0 0 037 0 005 0 508 0 94 0 15 0 290 0 320 0 13 005 BTE 13 GLASS SEALANT Y 0 020 0 080 0 200 0 51 1 52 189 m MAX TYP oaia oF 0 15 B 0 125 0 200 EU d 2 03 BOTH ENDS 0 01840 003 p A 419 0 46 0 08 5 REV L 2 542025 16 Lead Ceramic Dual In Line Package J Order Number DM54161J or DM54163AJ NS Package Number J16A 0 740 0 780 dud 18 80 19 81 0090 22 725 2 286 INDEX AREA 0 250 0 010 6 350 0 254 PIN NO 1 PIN NO 1 IDENT IDENT OPTION 01 OPTION 02 0 065 0 130 0 005 50 150 10 005 0 060 49 0 300 0 320 1 651 5 302 0 127 1 524 A F el 620 8428 0 145 0 200 3 683 5 080 95 5 0 008 0 016 jo 09
6. ear input sets all four of the flip flop out puts low after the next clock pulse regardless of the levels of the enable inputs This synchronous clear allows the count length to be modified easily as decoding the maxi mum count desired can be accomplished with one external NAND gate The gate output is connected to the clear input to synchronously clear the counter to all low out puts Low to high transitions at the clear input of the 163 are also permissible regardless of the logic levels on the clock enable or load inputs The carry look ahead circuitry provides for cascading coun ters for n bit synchronous applications without additional gating Instrumental in accomplishing this function are two count enable inputs and a ripple carry output Both count enable inputs P and T must be high to count and input T is fed forward to enable the ripple carry output The ripple car ry output thus enabled will produce a high level output pulse with a duration approximately equal to the high level portion of the Qa output This high level overflow ripple carry pulse can be used to enable successive cascaded stages High to low level transitions at the enable P or T inputs of the 161 through 163 may occur regardless of the logic level on the clock Features Synchronously programmable Internal look ahead for fast counting Carry output for n bit cascading Synchronous counting Load control line Diode clamped input
7. intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1 800 272 9959 Fax 1 800 737 7018 N National Semiconductor Europe Fax Email Deutsch Tel English Tel Fran ais Tel Italiano Tel 49 0 180 530 85 86 cnjwge tevm2 nsc com 49 0 180 530 85 85 49 0 180 532 78 32 49 0 180 532 93 58 49 0 180 534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel 852 2737 1600 Fax 852 2736 9960 National Semiconductor Japan Ltd Tel 81 043 299 2309 Fax 81 043 299 2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications
8. me Enable T to 16 his High to Low Level Output Ripple Carry Propagation Delay Time Clear Note 7 38 h amp High to Low Level Output toQ Note 7 Propagation delay for clearing is measured from the clear input for the 161 or from the clock input transition for the 163 Logic Diagrams DATA A 3 DATA B 4 DATA 5 DATA D 5 LOAD 9 d ENABLE P 7 ENABLE T 10 I RIPPLE 15 CARRY OUTPUT TL F 6551 3 Logic Diagrams continued 163 DATA 3 DATA 8 4 DATA C 5 DATA D 8 LOAD 7 gt c rs 1 ENABLE P 7 ENABLE T 10 RIPPLE 15 CARRY OUTPUT CLOCK 2 TL F 6551 8 Logic Diagrams continued A PX um X m ua Eu EH EM EE XR UE RM XR UR RM RM RR OW DATA Um m EH HD UR UM UR GR m m m c a INPUTS CLOCK 161 CLOCK 163 ENABLE P ENABLE T OUTPUTS RIPPLE CARRY OUTPUT 1 Clear outputs to zero 2 Reset to binary twelve 161 163 Synchronous Binary Counters Typical Clear Preset Count and Inhibit Sequences CLEAR ASYNCHRONOUS i 3 ASYNCHRONOUS ne Sa I 12 13 14 15 0 1 2 CLEAR PRESET 3 Count to thir
9. s Connection Diagram RIPPLE CARRY OUTPUT 04 09 CLEAR CLOCK A B Dual In Line Package OUTPUTS DATA INPUTS Order Number DM54161J DM54161W DM74161N or DM74163N See NS Package Number J16A N16E or W16A ENABLE Qc Qp T LOAD D ENABLE GND P TL F 6551 1 91995 National Semiconductor Corporation TL F 6551 RRD B30M105 Printed in U S A 19 UNOD g y SNOUOAYOUAS 9LvZINQ L9LPZINQ L9 LvSING Absolute Maximum Ratings note If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage 7M Input Voltage 5 5V Note The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaran teed The device should not be operated at these limits The parametric values defined in the Electrical Characteristics table are not guaranteed at the absolute maximum ratings The Recommended Operating Conditions table will define Operating Free Air Temperature Range DM54 DM74 Storage Temperature Range the conditions for actual device operation 55 C to 125 C 0 C to 70 65 C to 150 C Recommended Operating Conditions Symbol Parameter DM54161 DM74161 and 163 Units Min Nom Max Min Nom Max Vcc Supply Voltage 4 5 5 5
10. teen fourteen fifteen zero one and two 4 Inhibit TL F 6551 5 Parameter Measurement Information Switching Time Waveforms tw cLock 30v _ CLOCK INPUT VREF ov t PHL MEASURE AT tq 1 MEASURE AT ty 2 OUTPUT VoL 4 tPLH MEASURE AT tya 4 MEASURE AT ty 9 Vou OUTPUT 0 VoL M MEASURE AT 4 8 MEASURE AT tya 4 OUTPUT Yoh Q REF V ipu MEASURE AT tua iq __ 1 NOTE MEASURE ty g Vou OUTPUT 9 VoL i PHL 4 MEASURE tys 10 OR Vou N 16 NOTE B RIPPLE CARRY VREF OUTPUT TL F 6551 6 Note The input pulses are supplied by generators having the following characteristics PRR lt 1 MHz duty cycle lt 50 Zour 500 For 161 and 163 tr lt 10 ns t lt 10 ns Vary PRR to measure fmax Note B Outputs and carry are tested at 1g for 161 163 where tpn is the bit time when all outputs are low Note C For 161 and 163 1 5V Parameter Measurement Information continued CLOCK INPUT 161A CLEAR INPUT LOAD INPUT DATA INPUTS A B C ANDD Q OUTPUTS 161A ENABLE P OR ENABLE T CARRY CLOCK INPUT 163A Q OUTPUTS 163A 3 0V ov 3 0V ov 5 0 ov Switching Time Waveforms VREF A 7 VREF Em VREF Ney V

National Semiconductor DM54161/DM74161/DM74163 Synchronous 4-Bit Counters handbook

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