Am71LS/81LS/95/96/97/98 handbook
Contents
1. Am71 81LS98 Y Ys Yi As Yo Yo Ac Ys Ys A Ya Ys CONNECTION DIAGRAMS Top Views Am71 81LS96 Am71 81LS97 G A Yi A Ya s Ys Ay Ya GND LIC 491 LIC 492 LIC 493 LIC 494 4 158 Am71LS 81LS 95 96 97 98 MAXIMUM RATINGS above which the useful life may be impaired 65 C to 150 C Storage Temperature Temperature Ambient Under Bias 55 C to 125 C Supply Voltage to Ground Potential 0 5V to 7 0V DC Voltage Applied to Outputs for HIGH Output State 0 5V to tVec max DC Input Voltage 0 5V to 7 0V DC Output Current 150mA ELECTRICAL CHARACTERISTICS The Following Conditions Apply Unless Otherwise Specifi 30mA to 5 0mA DC Input Current ied COML Ta OC to 70 C Voc 5 0V 5 MIN 4 75V MAX 25V MIL TA 55 C to t125C Voc 5 0V 10 MIN 4 50V MAX 5 50V Am71 81LS95 Am71 81LS96 DC CHARACTERISTICS OVER OPERATING RANGE Am71 81LS97 Am71 81LS98 Typ Parameters Description Test Conditions Min Note 1 Max Units Vin High Level Input Voltage 2 Volts Vi T Low Level Input Voltage 08 Volts Vi Input Clamp Voltage Vcc Min lj 18mA 1 5 Volts High Level Output Current ME 1 mA VI T OH i2. AJAM T1LSO5ft py S1LS95 Am71 81LS96 Am71 81LS97 Am71 81LS98 Three State Octal Buffers DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION Three state outputs drive bus line directly The Am71 81LS95 Am71 81LS96 Am71 81LS97 and Am71 Typical propagation delay 81LS98 are octal buffers fabricated using Advanced Low Am71 81LS95 Am71 81LS97 13ns Power Schottky technology The 20 pin package provides im Am71 81LS96 Am71 81LS98 10ns proved printed circuit board density for use in memory ad Typical power dissipation dress and clock driver applications Am71 81LS95 Am71 81LS97 BOmW The Am71 81LS95 and Am71 81LS97 present true data at the Am71 81L596 Am71 81L898 Bor outputs while the Am71 81LS96 and Am71 81LS98 are invert PNP inputs reduce DC loading on bus lines ing The Am71 81LS95 and Am71 81LS96 have a common Am71 81L896 and Am71 81LS98 are inverting enable for all eight buffers with access through a 2 input NOR Am71 81LS95 and Am71 81LS97 are non inverting gate The Am71 81LS97 and Am71 81LS98 octal buffers have 20 pin hermetic and molded DIP packages four buffers enabled from one common line and the other four 100 product assurance testing to MIL STD 883 buffers enabled from another common line In all cases the requirements outputs are placed in the three state condition by applying a high logic level to the enable pins All parts feature low current PNP inputs LOGIC DIAGRAMS Am71 81LS95 Am71 81LS96 Am71 81LS97
3. OL p ON uoa 4 161 Package Type Molded DIP Hermetic DIP Hermetic DIP Dice Temperature Range 0 C to 70 C 0 C to 70 C 55 C to 125 C 0 C to 70 C Am71LS 81LS 95 96 97 98 ORDERING INFORMATION Order Number Am71 81LS95 Am71 81LS96 Am71 81LS97 Am71 81LS98 DM81LS95N DM81LS96N DM81LS97N DM81LS98N DM81LS95J DM81LS96J DM81LS97J DM81LS98J DM71LS95J DM71LS96J DM71LS97J DM71LS98J AMB1LS95X AMB1LS96X AM81LS97X AM81LS98X 4 162
4. k Output Disable Time from Low Level 4 160 Am71LS 81LS 95 96 97 98 SWITCHING CHARACTERISTICS TEST CONDITIONS LOAD CIRCUIT FOR VOLTAGE WAVEFORMS THREE STATE OUTPUTS ENABLE AND DISABLE TIMES THREE STATE OUTPUTS POINT vec OUTPUT TN CONTROL RL LOW LEVEL 13V 13V ENABLING J gy tz t 5 WAVEFORM 1 o 45V s amp S S4 CLOSED FROM OUTPUT 1 13V CLOSED 15V UNDER TEST SZ OPEN t 7 DSV on tn M tuz f to IN3064 S OPEN f RT at Von J 13V S4 amp S2 15V S2 CLOSED CLOSED 1 a L WAVEFORM 2 sv LIC 495 LIC 496 Notes 1 Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control 2 Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control 3 In the examples above the phase relationships between inputs and outputs have been chosen arbitrarily 4 Pulse generator characteristics PRR lt 1MHz ZouT 509 tr lt 15ns tf lt 6ns 5 When measuring tp H and tpHL switches S4 and Sg are closed APPLICATIONS Am71 81LS96 USED AS SYSTEM AND OR MEMORY BUS DRIVER S MEMORY ADDRESS REGISTER OUTPUT sme I SYSTEM AND OR MEMORY ADDRESS BUS LIC 497 INDEPENDENT 4 BIT BUS DRIVERS RECEIVERS IN A SINGLE PACKAGE Am71 81LS98 OUTPUT OM PORTS BUS OUTPUT PORT CONTROL INPUT TO PORTS DATA pau ah BUS INPUT PORT CONTR
5. nda icti COML 26 Vec Min Viy 2 0V VoH High Level Output Voltage eas 0 8V tn Volts i 79 T MIL lon 1 0mA COM L 16 loL Low Level Output Current MIL EN mA a 4 a Vcc Min Vin 2 0V VoL Low Level Output Voltage Vy 0 8V i Off State High Impedance Voc Max Viy 2 0V O OFF State Output Current ViL 0 8V Input Current at Maximum a l Input Voltage Vcc Max Vi 7 0V T 1 ly High Level Input Current Voc Max Vj 2 7V u Both G Inputs at 2 0V Vi 0 5V 50 Low Leve A Input Voc Max Both G ds at 0 4V Vi 2 647 038 It Input Current cc p aur p mA G Input Vj 04V 0 36 los Short Circuit Output Current Voc Max Note 2 30 60 130 mA Supply G Var Max Am71 81LS95 Am71 81LS97 16 26 mA 1 cc E A cc Max Am71 81LS96 Am71 81LS98 3 21 Notes 1 All typical values are at Vcc 5 0V TA 25 C 2 Not more than output should be shorted at a time and duration of the short circuit should not exceed one second SWITCHING CHARACTERISTICS Vcc 5 0V Ta 25 C Am71 81LS95 Am71 81LS96 Am71 81LS97 Am71 81LS98 Parameters Description Test Conditions Min Typ Max Min Typ Max Units t Propagation Delay Time PLH Low to High Level Output t Propagation Delay Time ns PHL High to Low Level Output C 15pF Ry 2kQ tH Output Enable Time to High Level ns tzL Output Enable Time to Low Level ns t Output Disable Time from HIGH Level HZ utpu is e m ol e C 5pF RL 2
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Am71LS/81LS/95/96/97/98 handbook