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FAIRCHILD 74ABT16952 16-Bit Registered Transceiver with 3-STATE Outputs handbook

1. if a Hur DOITNUITANTTOONTTONTUNININT DD00D0U00000CI0000 000000000 8 1 i S 9 2 TYP 7 E i OT C amp ee g i g 5 6 TYP 4 05 O l N eai geile M Ga ee JL 0 5 TYP LAND PATTERN RECOMMENDATION 0 90 eae SEE DETAIL A afoje is LEAD TIPS F X 1 1 MAX aaa JER l y CFE LS 0 10 0 05 TYP as 0 09 0 20 TYP J oe fa 0 5 TYP I alle 0 17 0 27 TYP 0 13M a BE e rs GAGE PLANE ated i Neh gauge Pane PLANE 0 60 79 15 DETAIL A TYPICAL 56 Lead Thin Shrink Small Outline Package TSSOP JEDEC MO 153 6 1mm Wide Package Number MTD56 MTDS6 REV B LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems 2 A critical component in any component of a life support s nd no ALVLS UUM I M 9SULIL p319 S1H 4 49 94 TS69L LEV which a are intended for surgical implant into the body or b support or sustain life and c whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be rea sonably expected to result in a significant injury to the user device or system whose failure to perform can be rea sonably expe
2. CPAB CPBA CEA CEB OEAB OEBA Output Control OE Internal Output Function Q X Z Disable Outputs Lk L L Enable Outputs L H H Register Function Table Applies to A or B Register Inputs Internal D cP CE Q Function X X H NC Hold Data L Ea L L Load Data H a L H HIGH Voltage Level L LOW Voltage Level X Immaterial Z HIGH Impedance 7 LOW to HIGH Transition NC No Change Connection Diagram Pin Assignment for SSOP OEAB CPAB CEA Yoo Vec Ag By AS B Ma B4 GND GND As Bs Ag Bg Ay By Ag Ba Ag By Mo Bio GND GND AY By Aiz Bz M3 Biz Vec Veo Avg B4 Als Bis GND GND Th Ti CPAB CPBAy OEAB DEBA 1999 Fairchild Semiconductor Corporation DS011647 prf www fairchildsemi com s nd no ALVLS E UUM I M 9SULIL p319 S1H 4 49 94 ZS69L LEVEL 74ABT16952 Block Diagram CPAB CEA Ay gt a gt Gi am o n for either byte 1 or byte 2 gt J a a Register A Register B OEBA 8 CPBA CEB n www fairchildsemi com Absolute Maximum Ratings oie 1 Storage Temperature 65 C to 150 C Ambient Temperature under Bias 55 C to 125 C Junction Temperature under Bias 55 C to 150 C Vec Pin Potential to Ground Pin 0 5V to 7 0V Input Voltage Note 2 0 5V to 7 0V Input Current Note 2 30 mA to 5 0 mA Voltage Applied to Any Output in t
3. Ba PZH Output Enable Time 1 5 5 5 5 5 5 ns PzL OEAB or OEBA to 15 5 5 5 5 5 An or Ba PHZ Output Disable Time 1 5 6 0 5 6 0 ns PLZ OEAB or OEBA to 1 5 6 0 5 6 0 A or Ba AC Operating Requirements Ta 25 C Ta 40 C to 85 C Symbol Parameter MEETRIS FE ee Units C 50 pF C 50 pF Min Max Min Max s H Setup Time HIGH 2 5 2 5 ns s L or LOW A or Bn 2 5 2 5 to CPAB or CPBA H H Hold Time HIGH 1 5 1 5 ns H L or LOW A or Bn 1 5 1 5 to CPAB or CPBA s H Setup Time HIGH 25 25 ns s L or LOW CEA or CEB 2 5 2 5 to CPAB or CPBA H H Hold Time HIGH 1 5 1 5 ns H L or LOW CEA or CEB 1 5 15 to CPAB or CPBA tw H Pulse Width 3 0 3 0 iw L HIGH or LOW 3 0 3 0 ns to CPAB or CPBA Capacitance Symbol Parameter Typ Units Conditions Ta 25 C Cin Input Capacitance 5 pF Vec OV Non I O Pins Co Note 5 Output Capacitance 11 pF Vec 5 0V An Bn Note 5 Cio is measured at frequency f 1 MHz per MIL STD 883 Method 3012 www fairchildsemi com AC Loading 7V OPEN bg ALL OTHER 5000 5000 50 pF NEGATIVE PULSE POSITIVE PULSE AMP V ov AMP V ov Includes jig and probe capacitance VM 1 5V FIGURE 1 Standard AC Test Load FIGURE 2 Test Input Signal Levels Amplitude Rep Rate tw t t 3 0V 1 MHz 500 ns 2 5 ns 2 5 ns FIGURE 3 Input Signal Requirements AC Waveforms DATA Y X Vm 1 5 OUTPUT IN CONTROL feu
4. tPLH tezu Vm DATA OUT DATA t OUT PZL Vm DATA OUT tPLH teu FIGURE 4 Propagation Delay Waveforms for Inverting and Non Inverting Functions CLOCK OR a ce CONTROL INPUT DATA fees cl IN s L tou 7 t lt gt s H Vm CLOCK OR oa ae OUT Vm LH FIGURE 5 Propagation Delay Pulse Width Waveforms FIGURE 6 3 STATE Output HIGH and LOW Enable and Disable Times FIGURE 7 Setup Time Hold Time and Recovery Time Waveforms www fairchildsemi com cS69LLEVPZ 74ABT16952 Physical Dimensions inches millimeters unless otherwise noted 0 720 0 730 18 30 18 54 56 29 0 398 0 417 10 10 10 60 Se 0 010 0 25 c le OJO 0 291 0 299 7 40 7 59 0 005 0 009 l te 28 0 13 0 22 fosi 20 08 aa ale 0 635 ale GAUGE re eae y a21 o s NP oos J AN eeose M losi 1 01 DETAIL E TYP 0 096 0 108 450x To 590 63 2 44 2 74 SEATING PLANE N SEE DETAIL E Z Z Y YOO O SAAR ABARRAEERRRRRRRRR AU CQ 0 004 0 10 t 0 025 ve 0 019 jy ve ete 0 635 0 25 0 8 TYP Wss6a EV F 56 Lead Shrink Small Outline Package SSOP JEDEC MO 118 0 300 Wide Package Number MS56A www fairchildsemi com 6 Physical Dimensions inches millimeters unless otherwise noted Continued
5. 0 0 54ABT 1692C 0 0 Ea FAIRCHILD SEMICONDUCTOR Tw 74ABT 16952 November 1993 Revised January 1999 16 Bit Registered Transceiver with 3 STATE Outputs General Description The ABT16952 is a 16 bit registered transceiver Two 8 bit back to back registers store data flowing in both directions between two bidirectional buses Separate clock clock enable and 3 STATE output enable signals are provided for each register The output pins are guaranteed to source 32 mA and to sink 64 mA Features E Separate clock clock enable and 3 STATE output enable provided for each register E A and B output sink capability of 64 mA source capability of 32 mA Guaranteed latchup protection E High impedance glitch free bus loading during entire power up and power down cycle E Nondestructive hot insertion capability Ordering Code Order Number Package Number Package Description 74ABT16952CSSC MS56A 56 Lead Shrink Small Outline Package SSOP JEDEC MO 118 0 300 Wide 74ABT16952CMTD MTD56 56 Lead Thin Shrink Small Outline Package TSSOP JEDEC MO 153 6 1mm Wide Devices also available in Tape and Reel Specify by appending the letter suffix X to the ordering code Pin Descriptions Pin Names Description Ao A15 Data Register A Inputs B Register 3 STATE Outputs Bo Bis5 Data Register B Inputs A Register 3 STATE Outputs Clock Pulse Inputs Clock Enable Output Enable Inputs
6. cted to cause the failure of the life support device or system or to affect its safety or effectiveness www fairchildsemi com Fairchild does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications
7. he Disable or Power Off State in the HIGH State Current Applied to Output in LOW State Max 0 5V to 5 5V 0 5V to Vcc twice the rated lop mA DC Electrical Characteristics 500 mA 10V DC Latchup Source Current Over Voltage Latchup I O Recommended Operating Conditions Free Air Ambient Temperature 40 C to 85 C Supply Voltage 4 5V to 5 5V Minimum Input Edge Rate AV At Data Input 50 mV ns Enable Input 20 mV ns Clock Input 100 mV ns Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under these conditions is not implied Note 2 Either voltage limit or current limit is sufficient to protect inputs Symbol Parameter Min Typ Max Units Vec Conditions Vin Input HIGH Voltage 2 0 Vv Recognized HIGH Signal Vit Input LOW Voltage 0 8 V Recognized LOW Signal Vep Input Clamp Diode Voltage 1 2 V Min lin 18 mA Non I O Pins Vou Output HIGH Voltage 2 5 loH 3 mA Ap Bn 2 0 loH 32 mA An Bn VoL Output LOW Voltage 0 55 loL 64 mA An Bn Vip nput Leakage Test 4 75 Vv 0 0 lip 1 9 uA Non I O Pins All Other Pins Grounded IH nput HIGH Current 1 uA Max Viy 2 7V Non l O Pins Note 4 Vin Vcc Non I O Pins BVI nput HIGH Current 7 uA Max Vin 7 0V Non l O Pins Breakdown Test BVIT nput HIGH Current 100 uA Max V 5 5V A Bn Breakdow
8. n Test 1 0 IL nput LOW Current 1 uA Max Viy 0 5V Non I O Pins Note 4 1 Vin 0 0V Non I O Pins iHt lozy Output Leakage Current 10 uA OV 5 5V Vout 2 7V Ap Bn OEA or OEB 2 0V ittloz_ Output Leakage Current 10 uA OV 5 5V Vout 0 5V An Bn OEA or OEB 2 0V os Output Short Circuit Current 100 275 mA Max Vout OV Ap Bn CEX Output HIGH Leakage Current 50 uA Max Vout Voc An Bn Z2 Bus Drainage Test 100 uA 0 0V Vout 5 5V An Bn All Others GND CCH Power Supply Current 1 0 mA Max All Outputs HIGH CCL Power Supply Current 60 mA Max All Outputs LOW cez Power Supply Current 1 0 mA Max Outputs 3 STATE All Others GND CCT Additional Ig Input 2 5 mA Max V Voc 2 1V All Others at Voc or GND locp Dynamic Icc No Load Outputs Open Note 4 0 18 mA MHz Max OEA or OEB GND Non l O GND or Vcc One Bit toggling 50 duty cycle Note 3 Note 3 For 8 bit toggling Iccp lt 1 4 mA MHz Note 4 Guaranteed but not tested www fairchildsemi com cS691LLEVPZ 74ABT16952 AC Electrical Characteristics SSOP Package Ta 25 C Ty 40 C to 85 C Symbol Parameter Mees ue NGC T SMR SRN Units C 50 pF C 50 pF Min Max Min Max Mak Max Clock 200 200 MHz Frequency PLH Propagation Delay 1 5 5 3 5 5 3 ns PHL CPAB or CPBA to 1 5 5 3 5 5 3 An or

FAIRCHILD 74ABT16952 16-Bit Registered Transceiver with 3-STATE Outputs handbook

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